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Slide-5 (8086 Maximum Mode)

The document discusses the maximum mode configuration of the 8086 microprocessor which allows it to work alongside other processors like the 8087 and 8089 for improved performance through multiprocessing, though it makes the system more complex; key aspects of maximum mode covered include the use of components like the 8288 bus controller, request and grant pins for bus access, and status signals to indicate memory/I/O operations. The maximum mode differs from the minimum mode in how control signals are generated and bus requests are handled, as well as supporting multiple processors.

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Hafsaa Binte Harun
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58 views13 pages

Slide-5 (8086 Maximum Mode)

The document discusses the maximum mode configuration of the 8086 microprocessor which allows it to work alongside other processors like the 8087 and 8089 for improved performance through multiprocessing, though it makes the system more complex; key aspects of maximum mode covered include the use of components like the 8288 bus controller, request and grant pins for bus access, and status signals to indicate memory/I/O operations. The maximum mode differs from the minimum mode in how control signals are generated and bus requests are handled, as well as supporting multiple processors.

Uploaded by

Hafsaa Binte Harun
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Embedded Systems and

Interfacing
EEE 315
Fahim Mahmud
Assistant Professor
Dept. of EEE
CUET
Class outline

 What is maximum mode?


 Maximum mode diagram of 8086
 Change of pins in maximum mode
 Request and Grant
 Lock
 Status signals
 Difference between minimum and maximum mode of 8086
What is maximum mode?

 When there are multiple processors in the system, it is known as maximum


mode.
 In our context, if 8086 has 8087 (math co-processor) and/or 8089 (IO
processor) working alongside it, then we have what maximum mode
configuration of 8086.
 Maximum mode gives a boost in performance due to multiprocessing.
 However, the system becomes more complex and expensive.
Maximum mode configuration of 8086
Components in maximum mode

 8086 microprocessor
 8284 clock generator
 8282 latch
 8286 data transreceiver
 8288 bus controller
 Other processors (8087, 8089)
Change of pins in maximum mode
V.V.I EXAM
Request and Grant (RQ’/GT’)

 By default 8086 is the bus master (BM) in the system.


 When any other processor wants to become the BM, it gives request (low
pulse) on the RQ’/GT’ pin.
 8086 completes the current machine cycle and releases the bus and gives
grant signal (low pulse) to the pin.
 Other processor becomes the BM, finishes its jobs and then gives a release
signal. 8086 becomes the BM again.
 There are 2 RQ’/GT’ pins so that 2 processors (8087 and 8089) can be
connected to 8086. If both processors request for bus simultaneously, the
one connected to ‘0’ subscript gets higher priority.
Request and Grant (RQ’/GT’)
LOCK

 When an interrupt occurs, 8086 completes the current instruction and


executes the ISR. It’s because stopping at the middle of an instruction is not
possible because 8086 will always return to the next instruction after
executing ISR.
 However, in case of bus request, 8086 completes the current machine
cycle and then releases the bus. If 8086 is doing something important and
doesn’t want to release the bus, it makes LOCK’ = 0. In the code we write
as: LOCK MOV AL, [2000H]
 LOCK is an instruction prefix.
Status signals (S0, S1, S2)
 If there are multiple processors in the system, all of them would need to
read and write (control signals) at some time.
 If all the processors generate control signals individually, we would have to
give connections from all of them to each and every I/O device. The
configuration would become complicated.
 Instead, we use a bus controller (8288). The bus master (8086, 8087 or 8089)
gives the status signal to 8288. Based on the combination of status signals,
8288 produces the appropriate control signal (memory read, write etc.)
and gives them to memory or I/O devices.
 Since 8288 generates the control signals, it also needs to know when to
generate what signal. Therefore, there is a clock connection to 8288 from
8284 clock generator.
 8288 has ALE connection to STB of 8282, DEN’ and DT/R’ connection 8286
because 8288 controls all the operation here. It’s like the control center.
Status signals (S0, S1, S2)…

S2 S1 S0 Processor operation 8288 signal


0 0 0 Int. acknowledgement INTA’
0 0 1 I/O Read IORC’
0 1 0 I/O Write IOWR’/AIOWR’
0 1 1 Halt None
1 0 0 Instruction fetch MEMR’
1 0 1 Memory read MEMR’
1 1 0 Memory write MEMWR’/AMEMWR’
1 1 1 Inactive None
Difference between min and max
mode
 In max mode, control signals are generated by 8288 bus controller whereas
in min mode, 8086 generates the control signals.
 ALE and DT/R’ are given by 8288 in max mode. On the other hand, 8086
sends these signals in min mode.
 In max mode, bus request is handled by RQ/GT’ as opposed to HOLD and
HLDA in min mode.
 There are multiple processors in max mode. So, it’s faster than min mode.
 Max mode configuration is more complex and expensive than min mode.

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