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Design and implementation of digital clock with stopwatch on FPGA

Conference Paper · June 2017

DOI: 10.1109/ICCONS.2017.8250622

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 International Conference on Intelligent Computing and Control Systems
ICICCS 2017

Design and Implementation of Digital Clock with

Stopwatch on FPGA
Revati Muley1, Bhushan Patil1, Rabinder Henry1
PPCRC, International Institute of Information Technology, Pune, India
[email protected]

Abstract— This paper reports the design and development of Counter module consist of second, minute, hour
field programmable gate array based digital clock with counter which are updated by internal clock signal. Internal
additional feature of stopwatch. The implementation includes clock signal is generated on the completion of every counter
two different coding techniques. The performance has been and it will be updated by preceding counter. The stopwatch
comparatively analyzed based on these techniques. The
module displays up to 60 minutes. It has separate clear and
portability of reconfigurable platform allows for application to
various designs. The architecture has been implemented and start switch.
verified experimentally on a test board. Display module is nothing but seven segment
common anode display. A switch is provided to choose
Keywords—Digital Clock; Reconfigurable Platform;Stopwatch between Digital clock and stopwatch Top module combines
Counter Module, Stopwatch Module and Display Module. The
I. INTRODUCTION desired functions are implemented in these modules as shown
in Figure. Modular view is shown in Figure 1.
Nowadays in many real time operations and linear control
systems FPGA (Field Programmable Gate Array) based
implementation has become the benchmark. FPGA includes
arrays of configurable logic blocks [1] and a hierarchy of
programmable interconnects [2]. The term ‘field
programmable’ highlights the customization of the IC
(Integrated Circuits) by the designer, rather than by the foundry
manufacturing the FPGA [3]. Time to delivery, low cost design
and development of integrated circuits can be attributed to
flexibility, quality of performance and amount of power
consumed by FPGA systems [4].
A digital clock displays the time digitally. Instead of using
the rotary mechanism of electromechanical clock, it uses digital
counters to count second, minute and hours. Each sixty seconds
make a minute and each sixty minutes an hour. After twenty
four hours the clock resets and starts from initial condition. In
stopwatch, separate switches are provided to start and clear it.
It can count up to 60 minutes [5].
In this work FPGA board is used as a platform to
implement digital clock and stopwatch. Xilinx ISE Design
Suite is used for development and VHDL [6] (VHSIC (very
high speed integrated circuit) Hardware Description Fig.1 Modular view of design.
Language) for implementation. From Figure 1 it can be observed that four output
data lines of counter module and stopwatch module are
multiplexed. As described before switch allows selection of
desired output on a seven segment display between digital
II. DESIGN OVERVIEW clock and stopwatch.
System design consists of Top down approach [5]. This III. IMPLEMENTATION
system mainly performs two functions i.e. Digital clock and
Stopwatch. These functions are implemented using counter A. Software Implementation
module, stopwatch module and display module.
Xilinx ISE (Integrated Synthesis Environment) Web pack
platform is used for development of the complete system.

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 International Conference on Intelligent Computing and Control Systems
ICICCS 2017

VHDL is used to describe hardware design in digital clock and

stopwatch. Programming logic is developed by sequential as
well as concurrent coding techniques [7,9]. In sequential
coding ‘nested – if’[8] loops while in concurrent coding ‘when
–else’ [9]statements have been used.
On-board 32 MHz crystal oscillator provides stable and
high frequency clock. This is given to frequency divider block
which will divide the frequency up to 1 Hz. This will generate
the 1 sec count and acts as a basic count for whole design. The
second’s generator count will drive second’s counter, as it
reaches to 60, it will update minute counter. And on
completion of 60 mins, hour counter will get start. As counter
reaches 23 hours, 59 minutes, 59 seconds then digital clock
gets reset to 00:00:00 and starts counting again [10]. The flow
of design for digital clock has shown in Figure 2.
In the stopwatch module, derived 1 sec pulse from counter
module is feed as an input to this block. It will start counting as
start switch activated. It counts up to 60 minutes. The design
flow of stopwatch is shown in Figure 3.
The display module is executing a count. Four common
anode seven segment displays is used for display purpose. For
every one millisecond each display will get refreshed with the
help of a multiplexer.

Fig.3 Flow chart for stopwatch.

B. Hardware Implementation
Papilio platform is used for hardware implementation. The
LogicStart is an open source MegaWing for the Papilio
development platform that provides you with everything you
need to get started with VHDL and FPGA development [11]. It
is most widely used in development of FPGA design. The
board provides a set of features that make it suitable for use in
a laboratory environment, for implementation of various design
projects, as well as for the development of digital systems.
Figure 4 shows working module of design.
In the design, specification [12] of device as follows:
x FAMILY: SPARTAN 3E.
Fig. 2 Flow chart of digital clock. x DEVICE: XC3S500E.
x PACKAGE: VQ100.
x SPEED: -4.

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 International Conference on Intelligent Computing and Control Systems
ICICCS 2017

IV. RESULT

Due to different coding techniques some parameters

in Synthesis reports are varying [15]. The extracted parameters
are tabulated in table 1.
With concurrent statement code the results obtained
like power required, area occupied, maximum frequency are
comparatively efficient than sequential code. Therefore with
less power and maximum frequency system can be
implemented by concurrent code.

Table 1 : Comparison of parameter for concurrent and sequential code .

S. Parameters Concurrent Sequential
No Code Code
A Device utilization report
Fig.4 Development board.
1 Number of slices 87 88
2 Number of slice flip flop 80 80
3 Number of 4 input LUTs 170 173
B Timing report
1 Maximum frequency(MHz) 162.136 139.782
For accessing the both features of design i.e. digital clock 2 Minimum input required time 5.009 6.036
and stopwatch, separate switch is assigned. Four 2:1 after clock(nsec)
multiplexer [13,14] is used with common select switch for 3 Maximum output required 8.046 8.934
selection of display. Also for clear, reset and start switch time before clock(nsec)
different switches have assigned. Figure 5 shows RTL 4 Maximum combinational 8.957 9.934
Schematic view of design. path delay(nsec)
C Memory usage(kilobytes) 263536 263568
D Power report
Static power(mWatt) 33.59 81.53
2 Dynamic power 0.00 0.00
(mWatt)
3 Total power(mWatt) 33.59 81.53

V. CONCLUSION
In this paper, Digital clock is capable of displaying
minutes and 12 /24 hours while stopwatch is displaying up to
60 minutes. Digital clock along with stopwatch, in two VHDL
coding techniques has implemented and verified. Because of
two different coding techniques, it is observed that there are
changes in occupied areas, power required and timing reports.
By division of the counter maximum clock frequency of
system is improved. In future this system would be expanded
with additional features like alarm clock, storage of laps in
stopwatch and date month year calendar.

REFERENCES
[1] Clive Maxfield, “FPGAs Instant Access” ,Newnes, 2008, chapter 2, pp
Fig. 5 RTL schematic view. 25-26 .
[2] Wayne Wolf, “FPGA – Based System Design ”, Pearson Education,
2005,Chapter 3 , pp 133-135.
[3] Pong P.Chu, “FPGA Protoyping by VHDL Examples- Xilinx Spartan 3
Version” , John Wiley & Sons, 2008,Chapter 2,pp11-12.

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 International Conference on Intelligent Computing and Control Systems
ICICCS 2017

[4] M. Senthil Sivakumar, R. Thandaiah Prabu and I. Jayanandan “Design [9] Volnei A. Pedroni, “Circuit Design With VHDL”,published by MIT
of digital clock calendar using FPGA,” IETE 45th mid term symposium Press,Cambrigde,Massachusetts,London England, 2004, chapter 5 , pp
on broadband-technologies and services for rural India MTS 14, 2014. 65-70.
[10] Juan-hua Zhu , Ang Wu , Juan-Fang Zhu “ Research and design of
[5] G.S.M. Galadanci and S.M. Gana “Design, implementation and digital clock based on FPGA,” Advanced Materials Research, Vol. 187,
simulation of 12/24 hours digital clock with stopwatch and date pp.741-745,2011.
indicator”,G.S.M Galdanci Int. Journal of Engineering Research and [11] Mike Field, “Introducing the Spartan 3E and VHDL,” Logicstart
Application, Vol.4, Issue 8 (Version 1),August 2014, pp 34-56. Megawing , 12 Apr 2012,Chapter 4 ,pp 8-10/119.
[12] Xilinx, “Spartan-3E FPGA family data sheet,” DS312 July 19 2013
[6] Jayaram Bhasker,“A VHDL Primer”, Pearson Prentice Hall, 3rd ,Module 1, pp 2
Edition,2005,chapter 1,pp 21-22. [13] Volnei A. Pedroni, “Circuit Design With VHDL”, MIT
Press,Cambrigde, Massachusetts,London England, 2004, chapter 5,pp
68-72.
[14] Stepen Brown and Zvonko Vranesic,”Fundamentals of Digital Logic
[7] Jayaram Bhasker,“A VHDL Primer”, Pearson Prentice Hall, 3 rd with VHDL design,second edition, published by Mc Graw hill,2005,
Edition,2005,chapter 5,pp 125-127. chapter 6,pp 350-351.
[15] Naresh Grover and M. K. Soni, “Simulation and Optimization of VHDL
code for FPGA-based design using Simulink,” Published Online June
[8] Volnei A. Pedroni, “Circuit Design With VHDL”, MIT 2014 in MECS , I.J. Information Engineering and Electronic Business
Press,Cambrigde, Massachusetts,London England, 2004, chapter 6,pp Academic,vol 3,pp. 22-27,2014.
91-96.

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