INSTITUTE OF AERONAUTICAL ENGINEERING

(Autonomous)
Dundigal, Hyderabad -500 043

INFORMATION TECHNOLOGY
COURSE DESCRIPTOR

Course Title DIGITAL LOGIC DESIGN

Course Code AEC020

Programme B.Tech

Semester III CSE | IT

Course Type Core

Regulation IARE - R16

Theory Practical

Course Structure Lectures Tutorials Credits Laboratory Credits

3 1 4 3 2
Chief
Mrs. G Bhavana, Assistant Professor , ECE
Coordinator
Course Faculty Mrs. G Bhavana, Assistant Professor , ECE

I. COURSE OVERVIEW:
The course will make them learn the basic theory of microprocessor and their applications in
detail. Subsequently the course covers important concepts like how to write an assembly
language programming. They will learn to write an assembly language programming for
interfacing various I/O modules. They will learn to design different advance architectures to
design a new communication interfaces.

II. COURSE PRE-REQUISITES:

Level Course Code Semester Prerequisites Credits
Fundamentals of Electrical and
UG AEC005 II 4
Electronics Engineering

III. MARKS DISTRIBUTION:

CIA
Subject SEE Examination Total Marks
Examination
Digital Logic Design 70 Marks 30 Marks 100

IV. DELIVERY / INSTRUCTIONAL METHODOLOGIES:

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 ✔ Chalk & Talk ✔ Quiz ✔ Assignments ✘ MOOCs

✔ LCD / PPT ✔ Seminars ✘ Mini Project ✘ Videos

✘ Open Ended Experiments

V. EVALUATION METHODOLOGY:
The course will be evaluated for a total of 100 marks, with 30 marks for Continuous Internal
Assessment (CIA) and 70 marks for Semester End Examination (SEE). Out of 30 marks allotted
for CIA during the semester, marks are awarded by taking average of two CIA examinations or
the marks scored in the make-up examination.

Semester End Examination (SEE): The SEE is conducted for 70 marks of 3 hours duration.
The syllabus for the theory courses is divided into five units and each unit carries equal
weightage in terms of marks distribution. The question paper pattern is as follows. Two full
questions with “either” or “choice” will be drawn from each unit. Each question carries 14
marks. There could be a maximum of two sub divisions in a question.

The emphasis on the questions is broadly based on the following criteria:

50 % To test the objectiveness of the concept.

To test the analytical skill of the concept OR to test the application skill of
50 %
the concept.

Continuous Internal Assessment (CIA):

CIA is conducted for a total of 30 marks (Table 1), with 25 marks for Continuous Internal
Examination (CIE), 05 marks for Quiz/ Alternative Assessment Tool (AAT).

Table 1: Assessment pattern for CIA

Component Theory
Total Marks
Type of Assessment CIE Exam Quiz / AAT

CIA Marks 25 05 30

Continuous Internal Examination (CIE):

Two CIE exams shall be conducted at the end of the 8th and 16th week of the semester respectively. The
CIE exam is conducted for 25 marks of 2 hours duration consisting of two parts. Part–A shall
have five compulsory questions of one mark each. In part–B, four out of five questions have to
be answered where, each question carries 5 marks. Marks are awarded by taking average of
marks scored in two CIE exams.

Quiz / Alternative Assessment Tool (AAT):

Two Quiz exams shall be online examination consisting of 25 multiple choice questions and are
be answered by choosing the correct answer from a given set of choices (commonly four).
Marks shall be awarded considering the average of two quizzes for every course. The AAT may
include seminars, assignments, term paper, open ended experiments, five minutes video and
MOOCs.

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VI. HOW PROGRAM OUTCOMES ARE ASSESSED:
Program Outcomes (POs) Strength Proficiency assessed
by
PO 1 Engineering knowledge: Apply the knowledge of 3 Quiz
mathematics, science, engineering fundamentals, and an
engineering specialization to the solution of complex
engineering problems.
PO 2 Problem analysis: Identify, formulate, review research 2 Assignments
literature, and analyze complex engineering problems
reaching substantiated conclusions using first principles of
mathematics, natural sciences, and engineering sciences
PO 4 Conduct investigations of complex problems: Use 2 Seminars
research-based knowledge and research methods including
design of experiments, analysis and interpretation of data,
and synthesis of the information to provide valid
conclusions.
3 = High; 2 = Medium; 1 = Low

VII. HOW PROGRAM SPECIFIC OUTCOMES ARE ASSESSED:

Program Specific Outcomes (PSOs) Strength Proficiency assessed
by
PSO 1 Professional Skills: The ability to research, understand 2 Seminars and
and implement computer programs in the areas related to Assignments
algorithms, system software, multimedia, web design, big
data analytics, and networking for efficient analysis and
design of computer-based systems of varying complexity.
PSO 2 Software Engineering Practices: The ability to apply 2 Quiz and
standard practices and strategies in software service Assignments
management using open-ended programming
environments with agility to deliver a quality service for
business success.
PSO 3 Successful Career and Entrepreneurship: The ability to - -
employ modern computer languages, environments, and
platforms in creating innovative career paths, to be an
entrepreneur, and a zest for higher studies
3 = High; 2 = Medium; 1 = Low

VIII. COURSE OBJECTIVES (COs):

The course should enable the students to:

Familiarize the basic concept of number systems, Boolean algebra principles and minimization
I
techniques for Boolean algebra.
Analyze Combination logic circuit and sequential logic circuits such as multiplexers, adders,
II
decoders flip flops and latches.
III Understand about synchronous and asynchronous sequential logic circuits.

IV Impart the basic understanding of memory organization, ROM, RAM, PLA and PAL.

IX. COURSE LEARNING OUTCOMES (CLOs):

CLO CLO’s At the end of the course, the student will have the PO’s Strength of
Code ability to: Mapped Mapping
AEC020.01 CLO 1 Understand the basic concept of number systems, PO 1 3
binary addition and subtraction for digital systems.
AEC020.02 CLO 2 Explain 2’s complement representation and PO 1 3
implement binary subtraction using 1’s and 2’s

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 CLO CLO’s At the end of the course, the student will have the PO’s Strength of
Code ability to: Mapped Mapping
complements.

AEC020.03 CLO 3 Discuss about digital logic gates, error detecting and PO 1 3
correcting codes for digital systems.
AEC020.04 CLO 4 Describe the importance of SOP and POS canonical PO 2 2
forms with examples.
AEC020.05 CLO 5 Describe minimization techniques and other PO 2 2
optimization techniques for Boolean formulas in
general and digital circuits.
AEC020.06 CLO 6 Evaluate Boolean algebra expressions by PO 2 2
minimizing algorithms like sop and pos using
Boolean Postulates and theorems.
AEC020.07 CLO 7 Solve various Boolean algebraic functions using PO 2 2
Karnaugh map and Tabulation Method.
AEC020.08 CLO 8 Understand bi-stable elements and different type’s PO 1 3
combinational logic circuits.
AEC020.09 CLO 9 Analyze the design procedures of Sequential logic PO 1 3
circuits with the help of registers.
AEC020.10 CLO 10 Discuss the concept of flip flops and latches by PO 2 2
using sequential logic circuits.
AEC020.11 CLO 11 Differentiate combinational logic circuits with PO 4 1
sequential logic circuits along with examples.
AEC020.12 CLO 12 Understand the concept of memory organization, PO 1 3
read only memory and random access memory.
AEC020.13 CLO 13 Discuss and implement combinational and PO 1 3
sequential logic circuits using PLA and PLDs.
AEC020.14 CLO 14 Explain the concept of memory hierarchy in terms of PO 1 3
capacity and access time.
AEC020.15 CLO 15 Explain about Synchronous and Asynchronous PO 2 2
Sequential Circuits: Reduction of state tables for
Mealy and Moore machines.
AEC020.15 CLO 16 Discuss about various memory concepts with respect PO 1 2
to temporary and permanent memory organizations.
3 = High; 2 = Medium; 1 = Low

X. MAPPING COURSE LEARNING OUTCOMES LEADING TO THE ACHIEVEMENT

OF PROGRAM OUTCOMES AND PROGRAM SPECIFIC OUTCOMES:
Course Program Specific
Program Outcomes (POs)
Learning Outcomes (PSOs)
Outcomes
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3
(CLOs)
CLO 1 2 2 2

CLO 2 3 1

CLO 3 3

CLO 4 2 1

CLO 5 2

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 Course Program Specific
Program Outcomes (POs)
Learning Outcomes (PSOs)
Outcomes
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3
(CLOs)
CLO 6 3 3

CLO 7 2 2

CLO 8 3 2

CLO 9 2 2

CLO 10 2

CLO 11 2

CLO 12 3

CLO 13 2 1

CLO 14 3

CLO 15 2 2 2

CLO 16 2 1
3 = High; 2 = Medium; 1 = Low

XI. ASSESSMENT METHODOLOGIES – DIRECT

CIE Exams PO 1, PO 2 SEE Exams PO 1, PO 2 Assignments PO 2 Seminars PO 4

Laboratory
- Student Viva - Mini Project - Certification -
Practices
Term Paper PO 4

XII. ASSESSMENT METHODOLOGIES - INDIRECT

✔ Early Semester Feedback ✔ End Semester OBE Feedback

✘ Assessment of Mini Projects by Experts

XIII. SYLLABUS

UNIT-I NUMBER SYSTEMS AND CODES

Review of number systems, number base conversion; Binary arithmetic: Binary weighted and non-
weighted codes; Complements: Signed binary numbers; Error Detection and Correcting Codes; Binary
logic.
UNIT -II BOOLEAN ALGEBRA AND GATE LEVEL MINIMIZATION
Postulates and theorems; representation of switching functions; SOP and POS forms; Canonical forms;
Digital logic gates; Karnaugh Maps: Minimization using three variable; four variable; five variable
KMaps; Don‘t Care Conditions; NAND and NOR implementation; Other Two-Level Implementation;
Exclusive –OR function.

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 UNIT -III DESIGN OF COMBINATIONAL CIRCUITS (CC)
Combinational Circuits: Analysis and Design Procedure; Binary adder and subtractors; Carry Look-a-head
adder; Binary multiplier.
Magnitude comparator;BCD adder; Decoders; Encoders; Multiplexers; Demultiplexer.
UNIT-IV DESIGN OF SEQUENTIAL CIRCUITS
Combinational Vs Sequential Circuits ; Latches, Flip Flops: RS flip flop, JK flip flop, T flip flop, D flip
flop, Master-Slave Flip flop, Flip Flops excitation functions; Conversion of one flip flop to another flip
flop; Shift Registers; Design of Asynchronous and Synchronous circuits; State Table, State diagram, State
Reduction and State Assignment for Mealy and Moore Machines..
UNIT -V MEMORY
Random access memory; Types of ROM; Memory decoding; Address and Data bus; Sequential memory;
Cache memory; Programmable logic arrays; Memory hierarchy in terms of capacity and access time
Text Books:
1. M. Morris Mano, Digital Design‖, Pearson Education/PHI, 3rdEdition 2001.
2. Charles H. Roth, Jr,Fundamentals of Logic Design‖, Thomson Brooks/Cole, 5 thEdition, 2004.
Reference Books:
1. C. V. S. Rao, Switching Theory and Logic Design, Pearson Education, 1stEdition, 2005.
2. M. Rafiquzzaman, Fundamentals of Digital Logic & Micro Computer Design‖, John Wiley, 5thEdition,
2005.
3. Zvi. Kohavi, Switching and Finite Automata Theory‖, Tata McGraw-Hill, 2ndEdition 1991.

XIV. COURSE PLAN:

The course plan is meant as a guideline. Probably there may be changes.
Course
Lecture Topics to be covered Learning
Reference
No Outcomes
(CLOs)
1-5 Understand the need for digital systems,review of number systems,
CLO 1 T1:1.1
number base conversion
6-10 Understand the arithmetic operations carried by digital systems. CLO 4 T1:1.5

11-15 Learn Boolean algebra and Logical operations in Boolean algebra. CLO 4 T1:2.2
Identify basic building blocks of digital systems and Minimization
16-20 using three variable; four variable; five variable K-Maps; Don‘t CLO 5 T1:2.8
Care Conditions.
21-25 Discuss the Bistable multi with triggering methods. Fixed bias, self
CLO 2 T1:3.5
bias, unsymmetrical triggering, symmetrical triggering.
26-28 Design functions using universal gates. NAND and NOR
implementation; Other Two-Level Implementation; Exclusive –OR CLO 6 T2:0.1
function.
29-30 Discuss the availability of different logic circuits.. CLO 12 T2:3.2
Design different combinational logic circuits comparators
31-35 CLO 14 T1:3.1
multiplexers.
36-40 Demonstrate the design of sequential logic circuits. CLO 10 T1:4.3

41-44 Identify the significance of Master-Slave Flip flop. CLO 13 T1:6.1

Design Flip Flops excitation functions; Conversion of one flip flop
45-52 CLO 15 R1:5.1
to another flip flop
Understand and analyze the state tables, state diagram and state
53-58 CLO 16 R1:5.3
excitation table.

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XV. GAPS IN THE SYLLABUS - TO MEET INDUSTRY / PROFESSION REQUIREMENTS:

S. N0 Description Proposed Relevance with Relevance with

actions POs PSOs
1 Practical use of number systems Seminars /
NPTEL/Assig PO 1, PO 2 PSO 1
nments
2 Applications of flipflops and latches Seminars /
PO 2, PO 4 PSO 1
NPTEL
3 Designing of circuits using flipflops
Guest Lecture PO 1, PO 2 PSO 2
and latches.

Prepared by:
Mrs. G Bhavana, Assistant Professor,ECE
HOD, IT

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