8-Bit RISC Processor Design using Verilog HDL on

FPGA

A
Dissertation
Submitted in the fulfilment of the requirements
For the award of degree
Of

MASTER OF TECHNOLOGY
In
Embedded System Design
By
JIKKU JEEMON
(Roll No. 3146510)

Under the Guidance of

Prof. A. K. GUPTA

^JMli'HcsKd •cj6>il •«!••

SCHOOL OF VLSI DESIGN AND EMBEDDED SYSTEMS

NATIONAL INSTITUTE OF TECHNOLOGY
KURUKSHETRA-136119
SESSION 2014-2016
 SCHOOL OF VLSI DESIGN AND EMBEDDED SYSTEMS

NATIONAL INSTITUTE OF TECHNOLOGY

KURUKSHETRA -136119

CERTIFICATE
This is to certify that the dissertation entitled ''''8-Bit RISC Processor
Design using Verilog HDL on FPGA" is the authentic record of work
done by Jikku Jeemon under my guidance and supervision. This
dissertation is being submitted to the National Institute of Technology,
Kurukshetra towards the fulfilment of the requirements for the award of
degree oi Master of Technology in Embedded System Design.

Date: / ^ 6 - 2.© 16 Dissertation Supervisor:

Dr. A. K. Gupta
Professor
School of VLSI Design and Embedded Systems
National Institute of Technology, Kurukshetra
 CANDIDA TE'S DECLARA TION

I hereby declare that the work being presented in this dissertation entitled
''8-Bit RISC Processor Design using Verilog HDL on FPGA'\ submitted
towards the fulfilment of the requirements for the award of degree, Master
of Technology in Embedded System Design to the School of VLSI Design
and Embedded Systems, National Institute of Technology, Kurukshetra, is
an authentic record of my work carried out from July 2015 to June 2016,
under the guidance of Prof A. K/GUPTA, School of VLSI Design and
Embedded Systems, National Institute of Technology, Kurukshetra.

I have not submitted the matter embodied in the dissertation for the award
of any other degree.

Jikku Jeemon
Roll No. 3146510
School of VLSI Design and Embedded Systems
Date:

II
 ACKNOWLEDGEMENT

I would like to express my deep gratitude and appreciation to all the people who have
helped and supported me in the process of dissertation. Without their help and support, 1
would not have been able to reach this level of satisfaction with what 1 have learnt and
accomplished during my Master's dissertation.

First and foremost, I would like to express my deep sense of respect and gratitude
towards my supervisor. Dr. A. K. Gupta, Professor, School of VLSI Design and
Embedded Systems, NIT Kurukshetra, for giving me opportunity to do my master's
dissertation under his guidance. I am very thankful for his endless support, motivation,
patience, encouragement and guidance during the study. His professional knowledge
and faith in me were very important and gave me the strength to conclude this work.

I express my grateful thanks to Dr. R. K. Sharma, Professor in School of VLSI Design

and Embedded Systems for providing 24 hour lab facility.

I would also like to thanks my friends for sharing their valuable thoughts and
knowledge, which motivated me to do better.

Finally, none of this would have been possible without incredible support of my parents.
They were always supporting me and encouraging me with their best wishes.

Jikku Jeemon
Roll No. 3146510
School of VLSI Design and Embedded Systems

III
 LIST OF FIGURES
Figure 2.1 Archilectureof 8-bit RISC processor [17] 6

Figure 2.2 Architecture of 8-bit RISC processor [18] 7

Figure 2.3 Computer architecture of 16-bit RISC processor [19] 8

Figure 3.1 8-bit RISC processor architecture 10

Figure 3.2 pipelining architecture 11

Figure 3.3 Block diagram of PCU 12

Figure 3.4 Block diagram of IM 13

Figure 3.5 Block diagram of Control unit 14

Figure 3.6 Block diagram of DM 15

Figure 3.7 Block diagram of Accumulator 16

Figure 3.8 Block diagram of Register set 18

Figure 3.9 Block Diagram of ALU unit 19

Figure 3.10 Block diagram of AND block 19

Figure 3.11 Block diagram of OR block 20

Figure 3.12 Block diagram of XOR block 20

Figure 3.13 Block diagram of ADD block 20

Figure 3.14 Block diagram of SUB block 21

Figure 3.15 Block diagram of Flag register 21

Figure 3.16 4-bit Flag register 22

Figure 3.17 Block diagram of I/O Module 22

Figure 3.18 INTCON register 23

Figure 3.19 Block diagram of Interrupt Module 23

Figure 3.20 UART serial communication protocol 24

IV
Figure 3.21 Block diagram of Serial Module 24

Figure 4.1 Simulation of Program Counter Unit 45

Figure 4.2 Simulation of Instruction Memory 46

Figure 4.3 Simulation of Data Memory 46

Figure 4.4 Simulation of accumulator 47

Figure 4.5 Simulation of Register set 48

Figure 4.6 Simulation of ALU unit 48

Figure 4.7 Simulation of interrupt module part 1 49

Figure 4.8 Simulation ofinterrupt module part 2 49

Figure 4.9 Simulation of serial module 50

Figure 4.10 Simulation of Control unit 51

Figure 4.11 Simulation results ofproposed processor part 1 54

Figure 4.12 Simulation results ofproposed processor part II 54

Figure 4.13 Simulation results of proposed processor part III 55

V
 LIST OF TABLES
Table 3.1 Instruction set 27

Table 4.1 Twenty-instruction program for simulation 53

Table 4.2 Device utilization of the Spartan-3E Starter kit FPGA board 54

VI
 LIST OF ABBREVIATIONS

Abbreviations Meaning

ALU Arithmetic Logic Unit

B Borrow flag

C Carry flag

DM Data Memory

FPGA Field Programmable Gate Array

HDL Hardware Description Language

IM Instruction Memory

IR Instruction Register

ISA Instruction Set Architecture

I/O Input/Output

LPU Low Power Unit

P Parity flag

PC Program Counter

PCR Program Counter Register

PCS Program Counter Save

PCU Program Counter Unit

RISC Reduced Instruction Set Computer

UART Universal Asynchronous Receiver Transmitter

Z Zero flag

VII
 ABSTRACT

RISC is a design technique used to reduce the amount of area required, complexity of
instruction set, instruction cycle and cost during the implementation of the design. This
dissertation presents an 8-bit RISC processor design using Verilog Hardware
Description Language (HDL) on FPGA board. The proposed processor is designed
using Harvard architecture, having separate instruction and data memory. The salient
feature of proposed processor is pipelining, used for improving performance, such that
on every clock cycle one instruction will be executed. Another important feature is that
instruction set contains only 34 instructions, which is very simple, easy to learn and
compact. The proposed processor has 8-bit ALU, Two 8-bit I/O ports, serial-in/serial-
out ports, Eight 8-bit general-purpose registers, 4-bit flag register and priority based
three interrupts. In RTL coding one can reduce the dynamic power by using clock-
gating technique, is used for specific modules that will be clocked only when
corresponding control signals are enabled. The proposed processor is physically verified
on Xilinx Spartan 3E Starter Board FPGA at 25MHz clock frequency, which will work
on 2.5 voltage supply.

VIII
 TABLE OF CONTENTS
CERTIFICATE I

CANDIDATE'S DECLARATION II

ACKNOWLEDGEMENT Ill

LIST OF FIGURES IV

LIST OF TABLES VI

LIST OF ABBREVIATIONS VII

ABSTRACT VIII

Chapter 1 INTRODUCTION 1

1.1 Importance of 8-bit RISC processor 2

1.2 This Work 2

Chapter 2 LITERATURE REVIEW 4

2.1 Brief History of 8-bit processor 4

2.2 Related Works 5

Chapter 3 DESIGN OF 8-BIT RISC PROCESSOR 9

3.1 Architecture of 8-bit RISC processor 9

3.2 Description of Functional Modules 11

3.2.1 Program Counter Unit (PCU) 11

3.2.2 Instruction Memory (IM) 12

3.2.3 Control Unit 13

3.2.4 Data Memory (DM) 15

3.2.5 Accumulator (A) 16

3.2.6 Register Set 17

3.2.8 ALU unit 18

IX
 3.2.8 Flag Register 21

3.2.9 I/O Module 22

3.2.10 Interrupt Module 22

3.2.11 Serial Module 24

3.3 List of control signals, I/O bus and Flags 25

3.4 Instruction Set Architecture 26

3.5 Sourx;e Code 28

Chapter 4 RESULTS AND DISCUSSIONS 45

Chapter 5 CONCLUSION 56

REFERENCES 57

APPENDIX A 59

APPENDIX B 64

X
 Chapter 1
INTRODUCTION
With the rapid development of the silicon technology and fall in the cost of the
integrated circuit, the usage of RISC processor is increasing extensively in every field.
The architecture principle Reduced Instruction Set Computer is commonly known as
RISC. RISC processors allow special load and store operations to access memory. The
other operations are performed on register-to-register basis. This feature makes
instruction set design more clear and simple as it allows execution of instructions at
one-instruction-per-cycle rate. Simple and transparent addressing modes allow fast
address computation of operands. Thus, the usage of RISC architecture reduces amount
of area required, complexity of instruction set, instruction cycle and cost of the
hardware ([1] and [2]). RISC processor's range of application includes signal
processing, convolution application, commercial data processing, used in
supercomputers such as the K computer, smart phones, tablets and real-time embedded
systems. Pipelining, a typical feature in RISC processors, is an implementation
technique in which multiple operations are performed at same time. It is a form of
parallelism at instruction-level using a single processor, which significantly improves
the performance of the processor. Pipelining increases instruction throughput but does
not reduce instruction latency, which is the time to complete a single instruction from
start to end [3].

The role of reconfigurable processor in embedded system design has increased greatly
during the past decades. Due to the advancement in Field Programmable Gate Array
(FPGA), we have reached a point where architecture of processor can be modified by
programming [4]. Clock power is a vital component of overall dynamic power
consumption, which should be minimized in design to reduce power consumption. One
of the methods to reduce clock power is clock-gating (ANDing) ([5] and [6]), which
dynamically terminates the clock signals in unused modules of the total hardware. This
avoids the urmecessary power dissipation cropped up by charging and discharging of
clock signal at unused gate.
Asynchronous serial communication has advantages of high reliabihty, simple because
it does not require synchronization both communicating sides and cheap because it
requires less hardware, hence is extensively used as a mode of communication between
computer and peripherals. Universal Asynchronous Receiver Transmitter (UART) is a
type of serial communication protocol, which is mostly used for short-distance, low
speed, low-cost data exchange between computer and peripherals. Asynchronous serial
communication is usually implemented by UART, which allows full-duplex
communication in serial link ([7] and [8]).

1.1 Importance of 8-bit RISC processor

Modem electronic devices such as desktops, laptops, notebooks, or tablets are using 32-
bit and 64-bit processors. 16-bit processors can be found in larger systems such as
traffic lights, systems controlling power plants and factory controllers. 16-bit embedded
processors are also used in consumer electronics including video game consoles, DVD
players, digital cameras, scanners and printers. Several household appliances including
microwave ovens and washing machines also uses 16-bit embedded processors.

However, 8-bit computers are used extensively as controllers for simple computational
tasks. According to the divide and conquer principle, a common personal computer is
divided into smaller ones (commonly 8-bit) which share information with the main
computer (32 or 64-bit). An 8-bit processor generally handles the drivers for almost
every component card inside a computer. 8-bit type processors are extensively used in
home appliances and industrial specific systems [9]. 8-bit or 16-bit processors are better
than 32-bit processors for system on a chip and microcontrollers that require
extremely low power for functioning and survival.

1.2 This Work

The objective of this dissertation is to design an 8-bit RISC processor and implement it
on Spartan 3E Starter kit FPGA using Verilog Hardware Description Language (HDL).
The processor is designed using Harvard architecture, having separate instruction and
data memory. Its most important feature is that its instruction set is very simple,
contains only 34 instructions, which is easy to learn. Another important feature is
pipelining, used for improving performance, such that on every clock cycle one
instruction will be executed. It is planned to design an 8-bit RISC processor having the
following main features.
 Harvard Architecture
• 256 K X 16 Instruction Memory
• 4 K X 8 Data Memory
8-bit system data bus
3 Interrupts
Eight 8-bit General Purpose Registers
clockfrequency= 25MHz
Two 8-bit I/O Ports
Serial-in and serial-out ports
2.5V voltage supply
Clock gating for power reduction
The dissertation is organized in five chapters. A brief outline of each chapter is
described below:

Chapter 2 presents previous work done related to the proposed processor as available
in literature.

Chapter 3 discusses the design and architecture of proposed processor, description of

functional modules and instruction set architecture.

Chapter 4 describes simulation results. The simulation of the proposed 8-bit RISC
processor is carried out in Xilinx's simulation tool ISim.

Chapter 5 concludes the work with brief summary of this dissertation.

 Chapter 2
LITERATURE REVIEW

This chapter presents the background for this work. Section 2.1 of this chapter presents
brief history of 8-bit processor. In Section 2.2, the related works are described.

2.1 Brief History of 8-bit processor

The evolution of the 8-bit processors is a history of the advancement of semiconductor

technology from first transistors, to the quantum leap of multiple transistors on a chip,
the integrated circuit (IC). 8-bit processors operate on 8-bit wide data, and normally
have a 16-bit address. They require backingfi"omsubsidiary chips such as memory and
I/O devices. The microcontrollers, as opposed to the CPU's, incorporate memory and
I/O on the same chip.

The Intel's 8008 was the first 8-bit monolithic microprocessor to market in April 1972.
It operated up to 0.8 MHz, had 3,500 transistors in a PMOS technology, with 10-micron
line width. There were 48 instructions. The address space was 16 kilobytes, but direct
addressing was not supported [10].

The Intel's 8080 was a great improvement over the prior 8008 chip, incorporating many
features into the chip that required the use of external hardware with the 8008. The 8080
a superset of 8008, an NMOS design, with 8-bit words and a 16-bit address bus was
released in 1974. It required ±5 volts and +12 volts and had six general-purpose
registers and accumulator. It used 6,000 transistors, maximum rating of 0.8 watts, had
48 instructions and operated at 2 MHz [11].

The Intel's 8085 was an advanced version of the 8080 and featured simplified hardware
that needed only a single +5V supply, it included a clock-generator and bus-controller
circuits on the chip and was introduced in 1976. It was binary compatible with the 8080,
but required less supporting hardware, allowing simpler and less expensive
microcomputer systems. The 8085 used a multiplexed data/address bus to reduce chip
pin-out. This required external de-multiplexing of the 16-bit address and the 8-bit data.
It had 48 basic instructions, maximum rating of 1.5 watts, operated up to 6 MHz,
featured serial in/out port and supported four vectored interrupts [12].
Reduced instruction set computer (RISC) is a CPU design technique based on the
perception that a simpHfied instruction set yields higher performance when linked with
a microprocessor architecture which can perform those instructions using fewer clock
cycles per instruction. The term RISC was coined by David Patterson of the Berkeley
RISC project, although similar concepts had appeared before [13].

The CDC 6600 designed by Seymour Cray in 1964 used a load/store architecture with
only two addressing modes (register-register, and register-immediate constant) and 74
opcodes, with the basic clock cycle/instruction issue rate being 10 times faster than the
memory access time [14].

IBM 801 is the first recognized RISC system, which was started in 1975 by John Cocke
and completed in 1980. The 801 was eventually produced in a single-chip form as
the ROMP (Research Office products Micro Processor) in 1981 .It was designed for
small tasks and was used in the IBM RT-PCin 1986, which turned out to be a
commercial failure. However, the 801 inspired several research projects, including new
ones at IBM that would eventually lead to the IBM POWER instruction set architecture
[15].

The most public RISC designs, however, were the results of university research
programs run with fiinding fi-om the DARPA VLSI Program. The Berkeley
RISC project started in 1980 under the direction of David Patterson and Carlo H.
Sequin. Berkeley RISC was based on gaining performance by pipelining and an
aggressive use of a technique known as register windowing. Berkeley RISC project
delivered the RISC-I processor in 1982 consisting of only 44,420 transistors (compared
with averages of about 100,000 in newer CISC designs of the era). RISC-I had only 32
instructions, and yet completely outperformed any other single-chip design. They
followed this up with the 40,760 transistor, 39 instruction RISC-II in 1983, which ran
over three times as fast as RISC-I [16].

2.2 Related Works

The design of an 8-bit RISC processor comprises of control unit, general-purpose

registers, barrel shifter, arithmetic and logical unit, universal shift register and
accumulator has been reported [17]. The architecture of this 8-bit RISC processor is
shown in Figure 2.1. Control unit follows instruction cycle of 3 stages fetch, decode and
execute cycle. According to the instruction fetched, the control unit generate signals to
-met
decode and execute the instruction. The architecture supports 16 instructions for
arithmetic, logical, shifting and rotational operations. Instruction and data are fetched
sequentially in order to reduce the latency in the machine cycle. Pipeline structure has
been incorporated for fetch, decode and execute. This pipeline structure helps in
enhancing the speed of operation. This processor can be used for mathematical
computation in portable calculators as well as in gaming tool kit.

CwrtrriUnit
Iiuauc&(m Register

ZZEEE
Instnictkm decoder

1
Untvosal Band
Siift Register SUfi
rotate:

ALU Accmmdator

Figure 2.1 Architecture of 8-bit RISC processor [17]

Another related work [18], describes an 8-bit RISC processor that consists of arithmetic
logic unit, control unit, shifter and rotator. The architecture of this processor is shown in
Figure 2.2. The processor is designed with load/store (Von Neumann) architecture, one
shared memory for instructions (program) and data with one data bus and one address
bus between processor and memory. Instruction and data are fetched in sequential order
so that the latency incurred between the machine cycles can be reduced. In'this design,
most instructions are of uniform length and similar structure, arithmetic operations are
restricted to CPU registers and only load and store instructions access memory. Three
stages of pipelining have been incorporated in the design, which increases the speed of
operation. This processor can be used as a systolic core to perform mathematical
computations like solving polynomial and differential equations.
 y
^
CCfytTROL
na^TmicTi0N RE@isn»i
liKtT
m s m U C S n O N DECODER

^
ISI li _«_
UmVGRSAt

SJIMIiiRSi
*S^ ^N
> ACCUMUtAtOn

H^&atB

Figure 2.2 Architecture of 8-bit RISC processor [18]

The design of a 16-bit processor has been reported [19] with customised instruction set
for soft-core RISC processor. Instruction Set Architecture (ISA) contains 35 basic
instructions. Among all soft-core processors, RISC design is widely adopted for its
single clock cycle instructions and less resource requirement compared to CISC
approach. The computer architecture of 16-bit RISC processor is shown in Figure 2.3. It
describes the custom simulation of a RISC soft-core processor's instruction set that is
based on Microchip PIC16C5X architecture. Memory address remapping algorithm is
introduced to remap the memory address to correct physical memory address due to
memory banking scheme being applied. Simulation process is done on a highly
customizable Java based computer architecture simulator. It provides features to insert
customized instruction in an assembly language and has the ability to perform
simulation at microcode level to variety of CPU architectures.
 tON<^-3t!

r^A
m OUT

Figure 2.3 Computer architecture of 16-bit RISC processor [19]

 Chapter 3
DESIGN OF 8-BIT RISC PROCESSOR

This chapter presents a design of an 8-bit RISC processor. Section 3.1 presents the
architecture of proposed processor. The architecture of the proposed processor is shown
in the figure 3.1. Section 3.2 presents the description of functional modules. Section 3.3
describes the instruction set architecture.

3.1 Architecture of 8-bit RISC processor

The 8-bit RISC processor is designed using Harvard architecture, having separate
instruction memory and data memory. The Figure 3.1 shows the complete architecture
of proposed system. The proposed processor is having 8-bit ALU, Two 8-bit I/O ports,
serial-in and serial-out ports, Eight 8-bit general registers, 3 interrupts and 4-bit flag
register having zero flag (Z), carry flag (C), borrow flag (B) and parity flag (P). The
proposed RISC processor is running at 25MHz and on 2.5 voltage supply. The 8-bit
SYSTEM DATABUS used for transferring data between different modules and 8-bit
Accumulator used for arithmetic and logical operations are also integral part of the
proposed processor. The Instruction Memory (IM) and Data Memory (DM) have
different address and data buses for communicating between different modules. The
interrupt module contains three interrupts, which are priority based. The proposed
processor's most important feature is that its instruction set is very simple, contains only
34 instructions, which is easy to learn.

Another important feature is pipelining, used for improving performance and provides a
way to reduce average execution time per instruction. The reduction can be observed as
decreased the number of clock cycles per instruction (CPI), as falling off in the clock
cycle time, or as a combinational effect. The pipelining architecture used for the
proposed processor is shown in Figure 3.2. The proposed processor requires only two
clock cycles for the execution of an instruction (jump instruction is an exception (TX2
also)), i.e. one fetch (TFl) and one execution cycle (TXl), which are mutually
exclusive. By the pipelining technique, while executing one instruction next instruction
is fetched, such that on every clock cycle one instruction will be executed. For efficient
reduction of power, clock gating is used for specific modules which be clocked, only
when it is required. Data memory and Register set are the modules where clock gating
is used. All loading to the registers is takes place at falling edge of clock and all control

signals are generated during rising edge of clock.

STACKPC PCS
SYSTEM DATABUS
PCU
IS
^ IM DM ^H-f
PCR PC IMAKJiffiUS
^%' BC
mDATABUS DM ADDRBUS
IS,.

4-- IR lEX LFU TaiER

Interrupt
m
^
CoatiolUflit k- Module n
Tsfate Isstrocti(»i .TMPO
Power fiqipm :iFo ri- 1NTC»N
Counter Decoder LIL
,TXF
I^KXF RBUFF
y- *4^i- Serial
Module
tXCNif
Accumulator
TBUFF

^ P O
Flag r ^ ^
RO
Register <r^ 4^^
*-v^ VQ
Module
Rl ^ 8 ^Pl
^^1^ ^ ^
"•V^ R2

'^^^ R3 ^-^

^l-l^ R4 *-4^
^ 1 ^ ^ R5 ^«-V^

M •—/

1^ *-/- R7 •^7^

Figure 3.1 8-bit RISC processor architecture

 TFl TXl
TFl TXl
TFl TXl
TFl TXl

Data transfer. Arithmetic & logical,

and Machine control & I/O instructions

TFl TXl
TFl TXl TX2
1 . TFl TXl

Iiranchiu;; instructions

Figure 3.2 pipelining architecture

3.2 Description of Functional Modules

In this work, the RISC processor consists of blocks namely, Program Counter Unit
(PCU), Instruction Memory, Data Memory, Control Unit, Register set, Arithmetic &
Logical Unit (ALU), I/O module. Interrupt module and Serial Module.

3.2.1 Program Counter Unit (PCU)

Program Counter unit consists of Program Counter (PC), Program Counter Save (PCS),
Program Counter Register (PCR) and STACKPC. In the proposed processor. Program
Counter (PC) is 18-bit wide register that contains the address (location) of the
instruction being executed at the current time. As each instruction is fetched,
the program counter increases its stored value by one. In fetch cycle, an 18-bit address
bus labelled as IM_ADDRBUS gets Program Counter content, when the corresponding
control signal is enabled. When LPCS control signal is enabled, Program Counter Save
(PCS) stores (18-bit) Program Counter content incremented by two value. PCR is used
to store address (in TXl cycle) of the next instruction to be executed, while a^branching
instruction is being executed. STACKPC is used to store the current PC value during
the execution of interrupt service routine. All loadings to the register occur at falling
edge of the clock.
 OSTACKPC

mcpc
Program Counter
OPC
(PC)
LPC •I
Vl8 To IMADDRBUS
LPCS >18 J8 \"
OPCS 18 FromlMDATABUS
s^
STACKPC PCR PCS • ^ &IR
RESET

4
CLK

Figure 3.3 Block diagram of PCU

SIGNALS FUNCTIONS
CLK System Clock
OPC To Output PC data on IMADDRBUS
LPC To Load PC with PCR content
INCPC To Increment PC value by one
OPCS To Load PC with PCS content
LPCS To Load PCS with PC content
RESET To Reset PC
OSTACKPC To Load PC with STACKPC content
3.2.2 Instruction Memory (IM)
Instruction Memory is 16-bit wide and having 262,144 address locations, so that any
practical real time programs can be fitted into it. In fetch cycle, when the corresponding
control signals are enabled, a 16-bit data bus labelled as IMDATABUS gets
Instruction Memory (IM) content corresponding to the valid address location provided
bytheIM_ADDRBUS.
 Xl8 FromlM ADDRBUS
Instrnction Mernoiy
RDIM ^ (IM)
' ? 256KX16 \16 To IM_DATABUS
,,.„,^,, „„.,. n s ^ p s s s ^

Figure 3.4 Block diagram of IM

SIGNAL FUNCTION
RDIM To output IM content to IMDATABUS
corresponding to the address provided by the
IM_ADDRBUS

3.2.3 Control Unit

The control unit contains Instruction Register (IR), Instruction RegisterX (IRX), Tstate
counter, Low Power Unit (LPU) and instruction decoder. The Instruction Register gets
the instruction for decoding during fetch cycle. While executing one instruction next
instruction is being fetched, therefore IR content should be stored in another register for
execution of the instruction. For this purpose, Instruction Register (IR) content is moved
to Instruction RegisterX (IRX) during every rising edge of clock of execution cycle.
Tstate counter generates fetch and execution cycles required for the proper working of
processor. The tstates TFl (fetch cycle), TXl (execution cycle), TX2 (execution cycle2,
only for branching instruction) are generated at rising edge of clock. The pipelining
feature is applied in the Tstate counter module. Interrupt priority and exceptions in
instructions, like jump, are also taken in account in Tstate counter module. Instruction
decoder will generate controls signals required for the modules whenever IRX is loaded
with a valid instruction. As IRX is loaded at every rising edge of execution cycle, the
control signals are generated at the same instance of time, because control signals are
generated according to the changes in the IRX content. Clock gating for Data Memory
and general purpose register set are done in Low Power Unit (LPU) of Control Unit.
Control Unit receives inputs from flag register. Serial Module and Interrupt Module.
The Control Unit takes input clock from source clock of FPGA and generates 59 control
signals and 4 clock signals for the proper working of all modules. The four clock signals
include gated clock signals for register set and Data Memory modules, baud rate clock
for Serial Module and 25 MHz output clock signal for all other modules.

The Control Unit receives inputs from Interrupt Module about the states of its three
interrupts through IFO, IFl and TMFO flags, which are taken into account in Tstate
counter module. Control Unit also receives inputs from Flag register regarding the states
of its four flags, which are used for control signal generation related to branching
instructions. The Control Unit receives inputs from Serial Module regarding
transmission or reception of data through TXF and RXFflags,which are set whenever a
transmission or reception is completed.

The Low Power Unit mainly uses clock-gating technique to reduce power dissipation.
The Data Memory and Register set are the main memory elements, which consume
power, so gated clock is provided to these modules. Whenever loading to a
memory/general-purpose register corresponding module will be activated. Thus, power
consumption in the proposed processor has been reduced by the use of clock-gating
technique.

TXF
IR —• IRX • LPU
4- Output elks

\59 Control signals

RXF i fc
12 .To
IFO DM_ADDRBUS
1
• ^

''
IFl Tstate Instruction 16 From
counter Decoder IM DATABUS
TMFO
8 Jo
ZCBP v« ^ SYSTEM DATABUS
^

^ '»'<• f IF

CLK LIR OIRSYS OIRDM

Figure 3.5 Block diagram of Control unit

All loading to memory/register takes place at falling edge of clock when the
corresponding control signals are high.
SIGNALS FUNCTIONS
LIR To output IM_DATABUS content to IR and PC is
incremented by one
OIRSYS To output IR content to SYSTEMDATABUS
OIRDM To output IR content to DMADDRBUS
3.2.4 Data Memory (DM)
Data Memory is 8-bit wide and has 4096 address locations. Data Memory gets the
required address location by 12-bit address bus, DMADDRBUS, from control unit.
Data memory provides read and write control and can be accessed by 8-bit data bus
SYSTEMDATABUS. Clock signal required for this module is provided by control
unit, which is active only during loading operations for power reduction. All loading to
the memory occurs at falling edge of clock, when corresponding control signals are
high.

RDDM

DATA MEMORY »8 To SYSTEM_DATABUS

WRDM
(DM)
"w 4Kx8
12 From DM ADDRBUS
^

DM C L K

Figure 3.6 Block diagram of DM

SIGNALS FUNCTIONS
DMCLK Data Memory Clock
RDDM To output DM content to SYSTEM_DATABUS
corresponding to the address provided by the
DM_ADDRBUS
WRDM To input SYSTEM_DATABUS content to DM
corresponding to the address provided by the
DM ADDRBUS
3.2.5 Accumulator (A)
Accumulator is an 8-bit wide register is shown in Figure 3.7. Accumulator is connected
to SYSTEMDATABUS by a bidirectional data bus, which is used for data transfer
instructions. Accumulator is also connected to ALUDATABUSA and
ALU_RESULT data buses, which are used for arithmetic and logical instructions.
Accumulator is connected to two 8-bit data buses for communicating with 1/0 module.
The increment, decrement, rotate right, rotate left and compliment operations are
performed on accumulator data. Accumulator is cormected to TBUFF register in Serial
Module for sending the data required for transmission through serial-out port 'txout'
and is connected to RBUFF register in Serial Module for storing the data received
through serial-in port 'rxin'.

INCA DECACMA RL RR

8 ^oALU_DATABUS_A

,8 ^To/fiom SYSTEM DATABUS

LALU
«-4-*
OALU ^ ,8 ^To Output port PI

LA .^V8 From Input port PO

mmmmf Accumulator (A)
OA t8 i>^To Serial Module
-»^—^'
RESET 8 From Serial Module
w—*\--

4 «™4
8 From ALU RESULT

I
CLK LIN OOUT LSIN OSOUT

Figure 3.7 Block diagram of Accumulator

SIGNALS FUNCTIONS
CLK System clock
RESET To Reset Accumulator
LA To Load Accumulator from SYSTEMDATABUS
OA To Output Accumulator to SYSTEM_DATABUS
INCA To Increment Accumulator
DECA To Decrement Accumulator
CMA To Complement all the bits of Accumulator
LALU To Load Accumulator from ALURESULT
OALU To Output Accumulator to ALUDATABUSA
RR To Rotate the bits of Accumulator in right direction
RL To Rotate the bits of Accumulator in left direction
LIN To Load Accumulator from 8-bit input port PO
OOUT To Send Accumulator content to 8-bit output port
PI
LSIN To Load Accumulator from 8-bit register RBUFF
in Serial Module
OSOUT To Send Accumulator content to 8-bit register
TBUFF in Serial Module
3.2.6 Register Set
Register set contains eight 8-bit registers RO, Rl, R2, R3, R4, R5, R6 and R7, which can
be used for storing data that arefrequentlyused. Register set is connected to ALU unit
by ALU_DATABUS_R, which is a unidirectional data bus for performing arithmetic
and logic operations. It is also connected to SYSTEMDATABUS by a bidirectional
data bus for loading and storing data. All loading to the register occur at falling edge of
clock, when corresponding control signals are high. The clock input to Register set is
gated-clock, which is active only during loading to any one of the registers. In the
Figure 3.8, in the confrol signals LRX, OERX and OERALX, X is 0 - 7 implying RO,
Rl, R2, R3, R4, R5, R6 and R7 register respectively.
 SYSTEM DATABUS ALU_DATABUS_R

\»
RO

Rl

R2 4-
R3

^ R4
R5

Re -^
- ^ R7 -^

^
V, sS v»

R CLK RESET LRX OERX OERALX

Figure 3.8 Block diagram of Register set

SIGNALS FUNCTIONS
R_CLK Register set clock
LRX To Load RX from SYSTEMDATABUS where X=
0,1,2, 3,4, 5, 6 or 7.
OERX To Output RX to SYSTEM_DATABUS
OERALX To Output RX to ALUDATABUSR
RESET To Reset all eight registers
3.2.8 ALU unit
ALU is connected to Accumulator, and general-purpose registers by its 8-bit buses
ALU_DATABUS_A and ALU_DATABUS_R. ALU unit consists of AND, OR, XOR,
ADD, SUB operations. RX shown in figure 3.9 can be any of the register RO, Rl, R2,
R3, R4, R5, R6 or R7. The result of operation is stored in Accumulator by the bus
labelled as ALU_RESULT. The zero flag (Z), Carry flag(C), Borrow flag (B) and parity
flag (P) are updated according to the ALU operation, which are stored in 4-bit Flag
Register. Parity flag is set only when resultant of ALU operation contains odd number
of ones.
 EAND
AND
EOR
ADD
EXOR ^

EADD OR
™ ^ -
ESUB
SUB

XOR
CLK
Oi
ALU DATABUS A ALU DATABUS R

ALU RESULT

RX

"I
SYSTEM DATABUS
4
Figure 3.9 Block Diagram of ALU unit

SYSTEM DATABUS

If 0ALU=1 and 0ERALX=1, data from

accumulator register and RX register are
^-^ transferred to ALU data buses and if
EAND=1 then AND operation will take
AND J
place in AND ALU block.
RX Parity flag (P) and Zero flag (Z) are
-^
updated. When LALU=1, the result is
transferred to accumulator during falling

EAJJD
T
CLK
edge of clock.
WhereX = 0,1,2, 3,4, 5, 6or7.

Figure 3.10 Block diagram of AND block

 SYSTEM DATABUS
If 0ALU=1 and 0ERALX=1, data from
accumulator register and RX register are
A transferred to ALU data buses and if
—»r
'? E0R=1 then OR operation will take
>.« place in OR ALU block.
' OR J
'§ Parity flag (P) and Zero flag (Z) are
RX updated. When LALU=1, the result is
transferred to accumulator during falling

T
EOR CXK
edge of clock.
WhereX = 0,1,2,3,4, 5 , 6 o r 7 .

Figure 3.11 Block diagram of OR block

SYSTEM_DATABUS
If 0ALU=1 and 0ERALX=1, data from
accumulator register and RX register are
*—4* A transferred to ALU data buses and if
' ! EX0R=1 then XOR operation will take
s XOR J place in XOR ALU block.
" Parity flag (P) and Zero flag (Z) are
1 *\} I
4 1^ » RX updated. When LALU=1, the result is
A transferred to accumulator during falling

EXOR
i\

1
CLK
edge of clock.
WhereX = 0, 1,2, 3,4, 5 , 6 o r 7 .

Figure 3.12 Block diagram of XOR block

If 0ALU=1 and 0ERALX=1, data from

accumulator register and RX register are
transferred to ALU data buses and if
EADD=1 then addition operation will
take place in ADD ALU block.
Carry flag (C), Parity flag (P) and Zero
flag (Z) are updated. When LALU=1, the
result is transferred to accumulator
during falling edge of clock.
WhereX = 0, 1,2, 3,4, 5, 6 o r 7 .

Figure 3.13 Block diagram of ADD block

 If 0ALU=1 and 0ERALX=1, data from
accumulator register and RX register are
transferred to ALU data buses and if
ESUB-1 then subtraction operation will
take place in SUB ALU block.
Borrow flag (B), Parity flag (P) and Zero
flag (Z) are updated. When LALU=1, the
result is transferred to accumulator
during falling edge of clock.
WhereX = 0, 1,2,3,4, 5 , 6 o r 7 .

Figure 3.14 Block diagram of SUB block

3.2.8 Flag Register

Flag register is a 4-bit special purpose register, which is used to store the status of the
result of any ALU operation. Flag register consists of Zero flag (Z), Carry flag (C),
Borrow flag (B) and Parity flag (P). Updating of the flags will occur corresponding to
the ALU operations only. For example, when an addition operation is performed Zero,
Carry and Parity flags will be updated, but Borrow flag will remain the same. All
process occurs at falling edge of clock when the corresponding control signals are high.
Figure 3.15 shows the block diagram of Flag register and Figure 3.16 shows the order in
which flags are arranged in Flag register.

EAND EOR EXOR EADD ESUB

\f ]f ^ ;'_ £
- ^ 1^ ^4 From SYSTEM_DATABUS
c
' • • • MJL,,^

B Flag Roister
. .1 , ^ J S ^ ^ "
P
' 7
4
CLK SETCLRF

Figure 3.15 Block diagram of Flag register

 z C B P
bits bit 2 bitl bitO

Figure 3.16 4-bit Flag register

SIGNALS FUNCTIONS
CLK System clock
SETCLRF To Set/Clear flags bits by SYSTEMDATABUS
content
BAND A and RX, Parity (P) and Zero (C) flags are updated
EOR A or RX, Parity (P) and Zero (C) flags are updated
EXOR A xor RX, Parity (P) and Zero (C) flags are updated
EADD A + RX, Carry (C), Parity (P) and Zero (C) flags are
updated
ESUB A - RX, Borrow (B), Parity (P) and Zero (C) flags are
updated
3.2.9 I/O Module
The I/O module has one 8-bit input port and one 8-bit output port for communicating
with external environment, which can be a sensor, actuator or even another
microprocessor. The input port PO and output port PI are directly connected to
Accumulator, which will control the data flow through the ports when corresponding
control signals are enabled.

PO \S To Accumulator

I/O Module , \ 8 From Accumulator

* \
PI

Figure 3.17 Block diagram of I/O Module

3.2.10 Interrupt Module

The interrupt module contains two external hardware interrupts 10 and II and one timer
interrupt. The interrupts are priority based, the 10 interrupt is having highest priority,
followed by II interrupt and timer interrupt is having lowest priority. The II interrupt is
maskable and 10 is not maskable. The external hardware interrupts are level triggered
and must be high for two clock cycles for proper working of the proposed processor.
The interrupt module is having a 3-bit register INTCON to control the operations in
interrupt module. Its bit 2 is used for enabling and disabling timer interrupt, bit 1 is used
for enabling and disabling external interrupts and bit 0 is used for masking II.
Whenever bit 1 of INTCON is high and 10 is high, IFO flag will be set. However, IFl
flag will be set only if the bit 1 of INTCON is high, the bit 0 of INTCON is low and II
is high. The Interrupt module has lO-bit register known as TIMER for counting to a
predefined number, in this case it is 1023 (maximum value). When the TIMER register
reaches the maximum value, timer flag TMFO gets set. Thus in the interrupt service
routine we need to clear the TMFO flag by the instruction CLRTMRF. Whenever timer
interrupt is turned on, timer flag will be raised at predefined intervals, which depends on
the predefined number.

TMR ENB MASK

bit 2 bitl bitO
Figure 3.18 INTCON register

10 INTCON

II INTERRUPT MODULE
-#

TIMER 3 From SYSTEM DATABUS

i « ^

CLK LDITCON CLRTMRF

Figure 3.19 Block diagram of Interrupt Module

SIGNALS FUNCTIONS
CLK System clock
LINTCON To enable/disable interrupts and mask II
interrupt by SYSTEMDATABUS content.
CLRTMRF Clear timerflagTMFO
3.2.11 Serial Module
The Serial Module contains rxin as serial-in port and txout as serial-out port. The serial
communication is based on UART protocol shown in Figure 3.20. The baud rate used
for this Serial Module is 115200 per second. The data transmission starts with a start bit
of 0, followed by the individual data bits of the word with the Least Significant Bit
(LSB) being sent first and then stop bit 1. The Serial Module consists of two 8-bit
registers TBUFF and RBUFF for storing data while transmission and reception. The
data stored in TBUFF register is shifted out during serial data transmission and process
is reversed for RBUFF register. The baud rate (clock) required for serial communication
is provided by the control unit. Serial Module will provide TXF and RXFflagsto
Control Unit regarding transmission or reception of data, which will be set whenever a
transmission or reception respectively is completed.

Data bits

1 L Idle state
Idle state LSB MSB

Start bit Stop bit

Figure 3.20 UART serial communication protocol

TXF^ To Control Unit

TBUFF
RXF To Conti-ol Unit
SEIUAL MODIJLE
v 8 ^ To Accumulator
RBUFF ^ \8 From Accumulator
A

BAUDCLK

Figure 3.21 Block diagram of Serial Module

3.3 List of control signals, I/O bus and Flags

The Control Unit will generate 59 control signals and 4 output clocks for the proper
working of all modules.

Program Counter Unit:

Control signals: OPC, LPC, INCPC, OPCS, LPCS, OSTACKPC and LPCR
Input bus: IM_DATABUS [15:0], IRX [9:8]
Output bus: IM_ADDRBUS [17:0]

Instruction Memory:
Control signals: RDM
Input bus: IM_ADDRBUS [17:0]
Output bus: IMDATABUS [15:0]

Control Unit:
Control signals: OIRSYS, LIR and OIRDM
Input bus: IMDATABUS [15:0]
Output bus: DM_ADDRBUS [15:0], SYSTEM_DATABUS [7:0]
Flag inputs: Z, C, B, P, RXF, TXF, IFO, IFl and TMFO

Data Memory:
Control signals: RDDM and WRDM
Input bus: DM_ADDRBUS [15:0]
Output bus: SYSTEM_DATABUS [7:0]

Accumulator:
Control signals: LA, OA, LALU, OALU, INCA, DECA, CMA, RR, RL, LIN, OOUT,
LSIN, OSOUT and RESET
Input bus: PO [7:0], ALURESULT [7:0]
Output bus: PI [7:0], ALU_DATABUS_A [7:0]
Input/Output bus: SYSTEM_DATABUS [7:0]

Register set:
Control signals: LRO, LRl, LR2, LR3, LR4, LR5, LR6, LR7, OERO, OERl, 0ER2,
0ER3, 0ER4, 0ER5, 0ER6 and 0ER7
Input/Output bus: SYSTEMDATABUS [7:0]
Output bus: ALU_DATABUS_R [7:0]
ALU Unit:
Control signals: OERALO, OERALl, 0ERAL2, 0ERAL3, 0ERAL4, 0ERAL5,
0ERAL6, 0ERAL7, EAND, EXOR, EOR, EADD and ESUB
Input bus: ALU_DATABUS_A [7:0], ALU_DATABUS_R [7:0]
Output bus: ALURESULT [7:0]

Flag Register:
Control signals: SETCLRF
Flag output: Z, C, B and P

Interrupt Module:
Control signals: LINTCON and CLRTMRF
Flag output: IFO, IF 1, TMFO

Serial Module:
Flag output: TXF and RXF

3.4 Instruction Set Architecture

The Instruction set architecture contains four type of instructions, data transfer
instruction, arithmetic and logical instruction, branching instruction and machine
control and I/O instruction. The instruction set architecture contains only 34 basic
instructions and total number of opcodes is 83. The opcode contains 16 bits from 0 to
15, of which 15'^ and 14* bits decides type of instruction being performed. If the 15*
and 14* bit are 00, 01, 10 or 11, type of instruction will be data transfer instruction,
arithmetic and logic instruction, branching instruction or machine control and I/O
instruction respectively.

The main advantage of this instruction set architecture is the use of SAV PC instruction
that saves PC incremented by two value in PCS. SAV PC can be used before jump
instruction so that after jumping to another location, using RES PC (loads PCS content
to PC) we can come back to next instruction after jump instruction. The combined use
of SAV PC and jump instruction, will act like a CALL instruction thus reducing the
number of instruction required without sacrificing functionality. We can also use jump
instruction alone to jump to specific location. Another special instruction is RETI that is
used to restore the PC value after the execution of interrupt service routine. SETCLRF
is a special instruction, which can be used to clear or set every flag in flag register.
EDINTER is another special one, which can be used to enable/disable interrupts and
mask the II interrupt when needed.

Serial data transmission is possible by the use of SOUT TBUFF and WAIT TXF.
Initially use SOUT TBUFF to send accumulator content to TBUFF. Then use WAIT
TXF for waiting until data is completely transmitted serially from TBUFF register. For
serial data reception, initially use WAIT RXF for waiting until data is completely
received by RBUFF register and then use SIN RBUFF to store the serial data received
in RBUFF register to accumulator. IN PO is used to take 8-bit parallel input data from
Port PO that is connected to external hardware. OUT PI is used to send 8-bit parallel
data to Port PI, which is connected to external hardware. Thus by using rxin, txout. Port
PO and Port PI, the proposed processor can communicate with different types of
external hardware.

Table 3.1 shows instruction set of proposed RISC processor. In the Table 3.1
Opcode column, rrr is register select code from 000 to 111, x is don't care, a is address
and d is data. In the Table 3.1 Mnemonic column, RX is register representing any one of
RO, Rl, R2, R3, R4, R5, R6 and R7, A is accumulator, M is Data Memory address and
add 18 is Instruction Memory address. In Operation column, update flags means update
the flags corresponding to that operation.

Table 3.1 Instruction set

Opcode Mnemonic Operation

Data Transfer Instructions
OOOOOrrrxxxxxxxx MOV A, RX RX =>A
0001 Orrrxxxxxxxx MOV RX, A A=>RX
001Oaaaaaaaaaaaa MOV A, M M=>A
OOUaaaaaaaaaaaa MOV M ,A A=>M
OOOOlxxxdddddddd MOVI A, 8-bit data 8-bit data => A
Arithmetic and Logical Instructions
OlOOOOOrrrxxxxxx ANDA,RX A <= A and RX update flags
OlOOOOlrrrxxxxxx XOR A, RX A <= A xor RX update flags
OlOOOlOrrrxxxxxx OR A, RX A <= A or RX update flags
010001 Irrrxxxxxx ADDA,RX A <= A + RX update flags
OlOOlOOrrrxxxxxx SUBA,RX A <= A - RX update flags
OlOlOOOxxxxxxxx CMA A<=~A
OlOlOOlxxxxxxxx INC A A <= A + 1
OlOlOlOxxxxxxxx DEC A A <= A - 1
010101Ixxxxxxxx RRA rotate accumulator right by 1 bit
OlOllOOxxxxxxxx RLA rotate accumulator left by 1 bit
OllOOOxxxxxxdddd SETCLRF 4-bitdata clear/set flags
011001xxxxxxxxxx CLRTMRF clear timer flag
To control interrupt's operations; enable,
Olllxxxxxxxxxddd EDINTER 3-bitdata disable and mask
Branching Instructions
lOOOOaaxxxxxxxxx aaaaaaaaaaaaaaaa JUMPaddlS Jump to 18-bit address add 18
lOOOlaaxxxxxxxxx aaaaaaaaaaaaaaaa JZaddlS Jump to 18-bit address add 18 if Z=l
lOOlOaaxxxxxxxxx aaaaaaaaaaaaaaaa JCaddlg Jump to 18-bit address add 18 if C= 1
lOOOlaaxxxxxxxxx aaaaaaaaaaaaaaaa JBaddlS Jump to 18-bit address add 18 if B=l
lOOOlaaxxxxxxxxx aaaaaaaaaaaaaaaa JP addl8 Jump to 18-bit address add 18 if P=l
Machine Control and I/O Instructions
1lOOOOxxxxxxxxxx HALT To stop operations
110001xxxxxxxxxx RESET To reset Accumulator, Register set and PC
1lOOlOxxxxxxxxxx SAVPC Save PC+2 value in PCS register
110011xxxxxxxxxx RES PC Restore PC with PCS content
1lOlOOxxxxxxxxxx RETI Returnfi-ominterrupt service routine
110101xxxxxxxxxx WAITTXF Wait until TXF flag gets set
11011Oxxxxxxxxxx WAITRXF Wait until RXF flag gets set
11lOOxxxxxxxxxxx INPO Accumulator gets Port PO content
11101xxxxxxxxxxx OUT PI Accumulator sends it content to Port PI
111lOxxxxxxxxxxx SEsTRBUFF Accumulator gets RBUFF register content
Accumulator sends its content to TBUl
11111xxxxxxxxxxx SOUT TBUFF
register

The more information regarding instruction set architecture is provided in appendix A

and micro operations of each instruction are covered in appendix B.

3.5 Source Code

The programming language used for the design of this 8-bit RISC processor is Verilog.
The source code for the proposed processor is given below.

/ * Control Unit, Program Counter unit and Instruction Memory */

module ins_decoder(
input inclk,
input [7-.01 PORTO,
output [7:0] PORTl,
input 10,11,
output reg clk=l'bO,
incut IF0,IF1,TMF0,
inout [3:0] ZCBP,
output LR0,LRl,LR2,LR3,LR4,LR5,LR6,LR7,OER0,OERl,OER2,OER3,OER4,OER5,OER6,OER7,
output OERALO,OERAL1,OERAL2,OERAL3,OERAL4,OERAL5,OERAL6,OERAL7,
output RESET,
output OIRDM,RDDM,WRDM,
output LA,OA,LALU,OALU,INCA,DECA,CMA,RR,RL,
output EAND,EXOR,EOR,EADD,ESUB,
output SETCLRF,CLRTMRF,
output LINTCON,
output LIN,OOUT,
output R_CLK,DM_CLK,
output reg baudclk=l'bO,
output reg c=l'bO,
input rxin,
output LSIN,OSOUT,
output txout,
inout RXF,TXF,
inout [15:0] IM_DATABUS,
inout [17:0] PCS_DATABUS,
inout [7:0] SYSTEM_DATABUS,
output [11:0] DM_ADDRBUS,
output [17:0] IM_ADDRBUS,
output [7:0] ace);
reg [15:0] IRX;
reg [17:0] PCR;
reg [17:0] PC=18'bO;
reg [17:0] PCS;
reg [17:0] STACKPC;
reg [15:0] IM [0:262143];
reg [15:0] IR;
always@(posedge incll<)
begin
cik=~clk;
end
reg [7:0] cb =8'b0;
always@(posedge inclk)
begin
if(cb==217)
begin
baudclk=~baudclk; //baudclock generation for serial module
cb=0;
c=l'bl;
end
else
begin
cb=cb+l;
c=l'bO;
end
end
wireOPC,LPC,INCPC,OPCS,LPCS,OSTACKPC,OIRSYS,RDIM,LPCR,LIR;
wire DT,ALU,BR,MIO;

//identifying type of instruction

assign DT=(IRX[15:14]==2'bO)?l'bl:l'bO;
assign ALU=(IRX[15:14]==2'b01)?l'bl:l'bO;
assign BR=(IRX[15:14]==2'blO)?l'bl:l'bO;
assign MIO=(IRX[15:14]==2'bll)?l'bl:l'bO;
/ / tstate counter instantiation
tstate_counter
ts(.cll<(clk),.IF0(IF0),.IFl(IFl),.TMF0(TMF0),.TXF(TXF),.RXF(RXF),.IR8(IR[15:10]),.TFl(TFl),.TXl(TXl),.TX2(T
X2));

assign RESET = {TXl&&MIO)&&(~IRX[13])&&((IRX[12:101==3'b001)?l'bl:l'bO);

//assign STOP = (MIO)&&(~IRX[13])&&((IRX[12:10]==3'bO)?l'bl:l'bO);

/ / control signals of register set

assign LRO = (DT&&TXl)&&((IRX[13:ll]==3'b010)?l'bl:l'bO)&&((IRX[10:8]==3'bO)?l'bl:l'bO);
assign LRl = (DT&&TXl)&&((IRX[13:ll]==3'b010)?l'bl:l'bO)&&((IRX[10:8]==3'b001)?l'bl:l'bO);
assign LR2 = (DT&&TXl)&&{(IRX[13:ll]==3"b010)?l'bl:l"bO)&&((IRXllO:8]==3'b010)?l'bl:l'bO);
assign LR3 = (DT&&TXl)&&((IRX[13:ll]==3'b010)?l'bl:l'bO)&&((IRX[10:8]==3'b011)?l'bl:l'bO);
assign LR4 = (DT&&TXl)&&((IRX[13:llI==3'b010)?l'bl:l'b0)&&((IRX[10:8]==3'bl00)?l'bl:l'b0);
assign LR5 = (DT&&TXl)&&((IRX[13:lll==3'b010)?l'bl:l'bO)&&((IRX[10:8]==3'bl01)?l'bl:l'bO);
assign LR6 = (DT&&TXl)&&((IRX[13:lll==3'b010)?l'bl:l'bO)&&((IRX[10:8]==3'bllO)?l'bl:l'bO);
assign LR7 = (DT&&TXl)&&({IRX[13:lll==3'b010)?l'bl:l'bO)&&((IRX[10:8]==3'blll)?l'bl:l'bO);

assign OERO = (DT&&TXl)&&((iRX[13:ll]==3'bO)?l'bl:l'bO)&&((IRX[10:8]==3'bO)?l'bl:l'bO);

assign OERl = (DT&&TXl)&&((IRX[13:ll]==3'bO)?l'bl:l'bO)&&((IRX[10:8]==3'b001)?l'bl:l'bO);
assign 0ER2 = (DT&&TXl)&&((IRX[13:ll]==3'bO)?l'bl:l'bO)&&((IRX[10:8]==3'b010)?l'bl:l'bO);
assign 0ER3 = (DT&&TXl)&&{(IRX[13:ll]==3'bO)?l'bl:l'bO)&&((IRX[10:81==3'b011)?l'bl:l'bO);
assign 0ER4 = (DT&&TXl)&&((IRX[13:ll]==3'b0)?l'bl:l'b0)&&((IRX[10:81==3'bl00)?l'bl:l'b0);
assign 0ER5 = (DT&&TXl)&&((IRX[13:ll]==3'bO)?l'bl:l'bO)&&((IRX[10:81==3'bl01)?l'bl:l'bO);
assign 0ER6 = (DT&&TXl)&&((IRX[13:ll]==3'bO)?l'bl:l'bO)&&((IRX[10:8]==3'bllO)?l'bl:l'bO);
assign 0ER7 = (DT&&TXl)&&((IRX[13:ll]==3'bO)?l'bl:l'bO)&&((IRX[10:8l==3'blll)?l'bl:l'bO);

assign OERALO = (ALU&&TXl)&&((IRX[13:121==2'b0)?l"bl:l'b0)&&((IRX[8:6]==3'b0)?l'bl:l'b0);

assign OERALl = (ALU&&TXl)&&((IRX[13:12]==2'b0)?l'bl:l'b0)&&((IRX[8:6]==3'b001)?l'bl:l'b0)
assign 0ERAL2 = (ALU&&TXl)&&((IRX[13:12l==2'b0)?l'bl:l'b0)&&((IRX[8:6]==3'b010)?l'bl:l'b0)
assign 0ERAL3 = (ALU&&TXl)&&((lRX[l3:12]~2'b0)?l'bl:l'b0)&&{(IRX[8:6]==3'b011)?rbl:l'b0)
assign 0ERAL4 = {ALU&&TXl)&&((IRX[13:121==2'b0)?l'bl:l'b0)&&((IRX[8:6]==3'bl00)?l'bl:l'b0)
assign 0ERAL5 = (ALU&&TXl)&&((IRX[13:12]==2'b0)?l'bl:l'b0)&&((IRX[8:6]==3'bl01)?l'bl:l'b0)
assign 0ERAL6 = (ALU&&TXl)&&((IRX[13:12]==2'b0)?l'bl:l'b0)&&((IRX[8:6]==3'bll0)?l'bl:l'b0)
assign 0ERAL7 = (ALU&&TXl)&&((IRX[13:12]==2'b0)?l'bl:l'b0)&&((IRX[8:6]==3'blll)?l'bl:l'b0)
assign R_CLK = (LRO| LRl | LR21LR31LR41LR51LR61LR7) && elk; //gated clock for register set

//Control signals of Program Counter Unit

assign OPC = TFl 11 (TX1&&BR);
assign LPC = (TX2 && BR)&&(((IRX[13:lll==3'bO)?l'bl:l'bO)| |(((IRX[13:ll]==3'b001)?l'bl:l'bO)&&
ZCBP[3]) 11 (((IRX[13:ll]==3'b010)?l'bl:l'bO)&& ZCBP[2]) 11 (((IRX[13:ll]==3'b011)?l'bl:l'bO)&&
ZCBP[1])| |(({IRX[13:lll==3'blOO)?l'bl:l'bO)&& ZCBP[0]));
assign INCPC = (TX2&&BR)&&(~LPC);
assign LPCS = (TXl&&MIO)&&(~IRX[13])&&((IRX[12:10l==3'b010)?l'bl:l'bO);
assign OPCS = (TXl&&IVIIO)&&(~IRX[13])&&((IRX[12:10]==3'b011)?l'bl:l'bO);
assign OSTACKPC = (TXl&&MIO)&&(~IRX[l31)&&((IRX[12:10]==3'blOO)?l'bl:l'bO);

/ / Control signals of control unit

assign LIR = TF1;
assign OIRDM = (TX1&&DT)&&(IRX[13]);
assign LPCR = TX1&&BR;
//assign OIRPC = TX1&&BR;
assign OIRSYS
((TXl&&DT)&&((IRX[13:ll]==3'b001)?l'bl:l'bO)) 11((TXl&&ALU)&&(((IRX[13:12]==2'blO)?l'bl:l'bO)11((
IRX[13:12]==2'bll)?l'bl:l'bO)));

/ / Control signals of Instruction Memory

assign RDIM =TF1 11 (TX1&&BR);

/ / Control signals of Data Memory

assign RDDM = (TXl&&DT)&&((IRX[13:12]==2'blO)?l'bl:l'bO);
assign WRDM = (TXl&&DT)&&((IRX[13:12]==2'bll)?l'bl:l'bO);
assign DM_CLK = WRDM && elk;

/ / Control signals of Accumulator

assign LA = (TX1&&DT)&&(~IRX[12]);
assign OA = (TX1&&DT)&&(IRX[12]);
assign OALU = (TXl&&ALU)&&((IRX[13:12]==2'bO)?l'bl:l'bO);
assign LALU = OALU;
assign CMA = (TXl&&ALU)&&((IRX[13:12]==2'b01)?l'bl:l"bO)&&((IRX[ll:9]==3'bO)?l'bl:l'bO);
assign INCA = (TXl&&ALU)&&((IRX[13:12]==2'b01)?l'bl:l'bO)&&((IRX[ll:9l==3'b001)?l'bl:l'bO);
assign DECA = (TXl&&ALU)&&((IRX(13:12]==2'b01)?l'bl:l'bO)&&((IRX[ll:91==3'b010)?rbl:l'bO);
assign RR = (TXl&&ALU)&&((IRX[13:12]==2'b01)?l'bl:l'bO)&&((IRX[ll:9)==3'b011)?l'bl:l'bO);
assign RL = (TXl&&ALU)&&((IRX[13:12]==2'b01)?l'bl:l'bO)&&((IRX[ll:9]==3'blOO)?l'bl:l'bO);
wire a = (LA I LALU | LIN | CMA | INCA | DECA | RR | RL);

/ / Control signals of ALU Unit

assign EAND = (TXl&&ALU)&&((IRX[13:12]==2'bO)?l'bl:l'bO)&&((IRX(ll:9]==3'bO)?l'bl:l'bO);
assign EXOR = (TXl&&ALU)&&((IRX[13:12]==2'bO)?l'bl:l'bO)&&((IRX[ll:9]==3'b001)?l'bl:l'bO);
assign EOR = (TXl&&ALU)&&((IRX[13:12]==2'bO)?l'bl:l'bO)&&((IRX[ll:9]==3'b010)?l'bl:l'bO);
assign EADD = (TXl&&ALU)&&((IRX[13:12]==2'bO)?l"bl:l'bO)&&((IRX[ll:9]==3'b011)?l'bl:l'bO);
assign ESUB = (TXl&&ALU)&&((IRX[13:12]==2'bO)?l'bl:l'bO)&&((IRX[ll:9]==3'blOO)?l'bl:l'bO);

/ / Control signals of Interrupt Module

assign LINTCON = (TXl&&ALU)&&((IRX[13:12]==2'bll)?l'bl:l'bO);
assign CLRTMRF = (TXl&&ALU)&&((IRX[13:12]==2'blO)?l'bl:l'bO)&&((IRX[ll:10]==2'b01)?l'bl:l'bO);

/ / Control signals of Flag Register

assign SETCLRF = (TXl&&ALU)&&((IRX[13:12]==2'blO)?l'bl:l'bO)&&((IRX[ll:10]==2'bO)?l'bl:l'bO);

/ / Control signals related I/O Module

assign LIN = (TXl&&MIO)&&{(IRX[13:ll]==3'blOO)?l'bl:l'bO);
assign OOUT = (TXl&&MIO)&&({IRX[13:ll]==3'bl01)?l'bl:l'bO);

/ / Control signals related to Serial Module

assign LSIN = (TXl&&MIO)&&((IRX[13:ll]==3'bllO)?l'bl:l'bO);
assign OSOUT = (TXl&&MIO)&&((IRX[13:ll]==3'blll)?l'bl:l'bO);

/ / I/O buses
assign SYSTEM_DATABUS = OIRSYS?IRX[7:0]:'bz;
assign DM_ADDRBUS = OIRDM?IRX[ll:0]:'b2;
assign PCS_DATABUS = (LPCS|OPCS)?((LPCS?PC:18'bO)|(OPCS?PCS:18'bO)):'bz;
assign IM_ADDRBUS = OPC?PC:'bz;
assign IM_DATABUS = RDIM?IM[IM_ADDRBUS]:'bz;

//Program Counter Unit operations

always@(negedge elk)
begin
if(LPC)
PC[17:0]=PCR;
else if(LPCR)
begin
PCR[15:0] = IM_DATABUS;
 PCR[17:16] = IRX[9:8];
end
else if(INCPC)
PC=PC+1;
else if(LIR&&LPCS)
begin
PCS=PCS_DATABUS+2;
IR=IM_DATABUS;
PC=PC+1;
end
else if(LIR)
begin
IR=IM_DATABUS;
PC=PC+1;
end
else if(LPCS)
PCS=PCS_DATABUS+2;
else if(OPCS)
PC=PCS_DATABUS;
else if(OSTACKPC)
PC=STACKPC;
else if( RESET)
PC=18'bO;
else if(IFO)
begin
STACKPC=PC-1;
PC=18'dl5;
end
else if(IFl)
begin
STACKPC=PC-1;
PC=18'dl7;
end
else if(TMFO)
begin
STACKPC=PC-1;
PC=18'dl5;
end
end
always@{posedge elk)
begin
IRX=IR;
end

/ / data memory instantiation

data_memory
a2(.clk(DM_CLK),.RDDM(RDDM),.WRDM(WRDM),.DM_ADDRBUS(DM_ADDRBUS),.SYSTEM_DATABUS(SY
STEM_DATABUS));

//alu unit instantiation

alu_unit
alusys(.clk(clk),.R_CLK(R_CLK),.EAND(EAND),.EXOR(EXOR),.EOR(EOR),.EADD(EADD),.ESUB(ESUB),.SYSTE
M_DATABUS(SYSTEM_DATABUS),.acc(acc),.OALU(OALU),.LALU(LALU),.OA(OA),.LA(LA),.INCA(INCA),.DEC
A(DECA),.CMA(CMA),.RR(RR),.RL(RL),PORTO(PORTO),.PORT1(PORT1),.RESET(RESET),.LIN(LIN),.OOUT(00
UT),.SETCLRF(SETCLRF),.OER0(OER0),.OERl(OERl),.OER2(OER2),.OER3(OER3),.OER4(OER4),.OER5(OER5)
,.OER6{OER6),.OER7(OER7),.LR0(LR0),.LRl(LRl),.LR2(LR2),.LR3(LR3),.LR4(LR4),.LR5(LR5),.LR6(LR6),.LR7(L
R7),.OERAL0(OERAL0),.OERALl(OERALl),.OERAL2(OERAL2),.OERAL3(OERAL3),.OERAL4(OERAL4),.OERAL
5(OERAL5),.OERAL6{OERAL6),.OERAL7(OERAL7),.flagreg(ZCBP),.baudclk(baudclk),.c(c),.rxin(rxin),.txout(t
xout),.LSIN(LSIN),.OSOUT(OSOUT),.RXF(RXF),.TXF(TXF));

//interrupt module instantiation

interrupt_module
inter(.clk(clk),.iO(IO),.il(ll),.LINTCON(LINTCON),.IFO{IFO),.(Fl(IFl),.TMFO(TiVIFO),.aRTMRF(CLRTMRF),.SYS
TEM_DATABUS(SYSTEM_DATABUS));

endmodule

/ * Tstate counter * /

module tstate_counter(
input clk,IFO,IFl,TMFaTXF,RXF, //input clock 25MHz
input [7:2] IRS,
output reg TF1=0,TX1=0,TX2=0);
reg [3:0]counter=5'b00;
reg[7:0]c = 8'b0;
always@(posedge dk)
begin
case(counter)
5'b0:begin
TFl=l'bl;
TXl=l'bO;
TX2=l'bO;
counter=5'b00001;
end
5'b00001:begin
if(IFO) //check for interrupt flag IFO
begin
TFl=l'bO;
TXl=l'bO;
counter=5'b00011;
end
else if(IFl) //check for interrupt flag IFl
begin
TFl=l'bO;
TXl=l'bO;
counter=5'b00011;
end
elseif(TMFO), //check for timer interrupt flag TMFO
begin
TFl=l'bO;
TXl=l'bO;
counter=5'b00011;
end
elseif(IR8[7:2]==6'bll0101) //check for wait TXF instruction
begin
TFl=l'bO;
TXl=l'bO;
counter=5'b01000;
end
else if(IR8[7:2]==6'bll0110) / / check for wait RXF instruction
begin
 TFl=l'bO;
TXl=l'bO;
counter=5'b01001;
end
else if(IR8[7:6]==2'blO) //check for branching instruction
begin
TFl=l'bO;
TXl=l'bl;
counter=5'b00010;
end
elseif(IR8[7:2]==6'bll0011) //check for RESTORE PC instruction
begin
TFl=l'bO;
TXl=l'bl;
counter=5'b0;
end
elseif(IR8[7:21==6'bll0100) //check for return interrupt instruction RET!
begin
TFl=l'bO;
TXl=l'bl;
counter=5'bO;
end
else if(IR8[7:2]==6'bll0000) / / check for halt instruction
begin
TFl=l'bO;
TXl=l'bO;
end
else
begin
TFl=l'bl;
TXl=l'bl;
counter=5'b00001;
end
end
5'b00010:begin
TFl=l'bO;
TXl=l'bO;
TX2=l'bl;
counter=5'bO;
end
5'b00011:begin
TFl=rbl;
TXl=l'bO;
TX2=l'bO;
counter=5'b00100;
end
5'b00100:begln
if(IR8[7:6]==2'blO)
begin
TFl=l'bO;
TXl=rbl;
counter=5'b00010;
end
elseif(IR8[7:2]==6'bll0011)
begin
TF1=0;
TXl=l'bl;
 counter=5'bO;
end
else if(IR8[7:2]==6'bll0100)
begin
TFl=l'bO;
TXl=l'bl;
counter=5'b0;
end
else
begin
TFl=l'bl;
TXl=l'bl;
counter=5'b00101;
end
end
5'b00101:begin
if(IR8[7:6]==2'blO)
begin
TFl=l'bO;
TXl=l'bl;
counter=5'b00010;
end
else if(IR8[7:2]==6'bll0011)
begin
TFl=l'bO;
TXl=l'bl;
counter=5'b0;
end
else if(IR8[7:21==6'bll0100)
begin
TFl=l'bO;
TXl=l'bl;
counter=5'bO;
end
else
begin
TFl=l'bl;
TXl=l'bl;
counter=5'b00110;
end
end
5'b00110:begin
if(IR8[7:6]==2'blO)
begin
TFl=l'bO;
TXl=l'bl;
counter=5'b00010;
end
else if(IR8[7:2]==6'bll0011)
begin
TFl=l'bO;
TXl=l'bl;
counter=5'b0;
end
else if(IR8[7:2]==6'bll0100)
begin
TFl=l'bO;
 TXl=rbl;
counter=5'b0;
end
else
begin
TFl=l'bl;
TXl=l'bl;
counter=5'b00111;
end
end
5'b00111:begin
if{IR8[7:6]==2'blO)
begin
TFl=l'bO;
TXl=l'bl;
counter=5'b00010;
end
else if(IR8[7:21==6'bll0011)
begin
TFl=l'bO;
TXl=l'bl;
counter=5'bO;
end
else lf(IR8[7:2]==6'bll0100)
begin
TFl=l'bO;
TXl=l'bl;
counter=5'b0;
end
else
begin
TFl=l'bl;
TXl=rbl;
counter=5'bO;
end
end
5'b01000:begin
if(IFO)
begin
TFl=l'bO;
TXl=l'bO;
counter=5'b00011;
end
else if(IFl)
begin
TFl=rbO;
TXl=l'bO;
counter=5'b00011;
end
else if(TMFO)
begin
TFl=l'bO;
TXl=l'faO;
counter=5'b00011;
end
else if(TXF && c==217)
begin
 TFl=l'bO;
TXl=l'bO;
counter=5'b0;
end
else
begin
TFl=l'bO;
TXl=l'bO;
counter=5'b01000;
end
end

5'b01001:begin
if(IFO)
begin
TFl=l'bO;
TXl=l'bO;
counter=5'b00011;
end
else if(IFl)
begin
TFl=l'bO;
TXl=l'bO;
counter=5'b00011;
end
elseif(TMFO)
begin
TFl=l'bO;
TXl=l'bO;
counter=5'b00011;
end
else if(RXF && c==217)
begin
TFl=l'bO;
TXl=l'bO;
counter=5'b0;
end
else
begin
TFl=l'bO;
TXl=l'bO;
counter=5'b01001;
end
end
endcase
end
always(S)(posedge elk)
begin
if(c==217)
c=0;
else
c=c+l;
end

endmodule
 / * Data Memory * /
module data_memory(
input elk, //gated clock for data memory
Input RDDM,WRDM,
input [11:0] DM_ADDRBUS,
inout [7:0] SYSTEM_DATABUS);
reg [7:0] DM [0:4095];
assign SYSTEM_DATABUS = RDDM?DM[DM_ADDRBUS]:'bz;
always@{negedge elk)
if(WRDM)
DM[DM_ADDRBUS]=SYSTEM_DATABUS;
endmodule

/ * ALU Unit and Flag register * /

module alu_unit(
input elk, //input clock 25MHz
input R_CLK, //gated-clock for register set
input [7:0] PORTO,
output [7:0] PORTl,
input RESET,LIN,OOUT,
input LR0,LRl,LR2,LR3,LR4,LR5,LR6,LR7,OE;R0,OERl,OER2,OER3,OER4,OER5,OER6,OER7,
input OERAL0,OERALl,OERAL2,OERAL3,OERAL4,OERAL5,OERAL6,OERAL7,
input OALU,LALU,OA,UV,INC:A,DECA,CMA,RR,RL,
input EAND,EX0R,E0R,EADD,ESUB,SETCLRF,

inout [7:0] SYSTEM_DATABUS,

output [7:0] A L U _ D A T A B U S _ A ,
output [7:0] A L U _ D A T A B U S _ B ,
output [7:0] ace,
inout [8:0] result,
output reg [3:0] flagreg=4'b0,
input baudelk,
input c,
input rxin,
input LSIN,OSOUT,
output txout,
output RXF,TXF);//ZCBFP
wireZ,C,B,P;

//accumulator instantiation
accumulator
acal(.clk{clk)..OA(OA),.LA(l^),.OALU(OALU),.LALU(l-ALU),.SYSTEM_DATABUS(SYSTEM_DATABUS),.ALU_D
ATABUS_A(ALU_DATABUS_A),.result(result),.Acc(aec),.INCA(INCA),.DECA(DECA),.CMA(CMA),.RR(RR),.RL(
RL),.RESET(RESET),.LIN(LIN),.OOUT{OOUT),.PORT0(PORT0),.PORTl(PORTl),.baudclk(baudclk),.c(c),.rxin{r
xin),.txout(txout),.LSIN(LSIN),.OSOUT(OSOUT),.RXF(RXF),.TXF(TXF));

//register set instantiation

register_set
rxal(.clk(R_CLK),.LR0(LR0),.LRl(LRl),.LR2(LR2),.LR3(LR3),.LR4(LR4),.LR5(LR5),.LR6(LR6),.LR7(LR7),.RESET(R
ESET),.OER0(OER0),.OERl(OERl),.OER2(O£R2),.OER3(OER3),.OER4(OER4),.OER5(OER5),.OER6(OER6),.OE
R7(OER7),.OERAL0(OERAL0),.OERALl(OERALl),.OERAL2(OERAL2),.OERAL3(OERAL3),.OERAL4(OERAL4),.
OERAL5(OERAL5),.OERAL6(OERAL6),.OERAL7(OERAL7),.SYSTEM_DATABUS(SYSTEM_DATABUS),.ALU_DA
TABUS_B(ALU_DATABUS_B));

/ / Flag register update

assign result = (EAND|EXOR|EOR|EADD|ESUB)?((EAND?ALU_DATABUS_A &
ALU_DATABUS_B:9'bO)|(EXOR?ALU_DATABUS_A'^ALU_DATABUS_B:9'bO)|(EOR?ALU_DATABUS_A|ALU
_DATABUS_B:9'bO) | (EADD?ALU_DATABUS_A+ALU_DATABUS_B:9'bO) | (ESUB?ALU_DATABUS_A-
ALU_DATABUS_B:9'bO)):'bz;
assign C = EADD?result[8]:'bz;
assign B = ESUB?result[8]:'bz;
assign Z = ((result==9'b0)! !(result==9'bl00000000))?l'bl:l'b0;
assign P = result[7]+result[6]+result[5]+result[4)+result[3]+result[2]+result[l]+result[0];

//ALU operations
always@(negedge cll<)
begin
if(EAND)
begin
flagreg[3]=Z;
flagreg[0]=P;
end
else if(EXOR)
begin
flagreg[3]=Z;
flagreg[0]=P;
end
else if(EOR)
begin
flagreg[31=Z;
flagreg[01=P;
end
else if(EADD)
begin
fiagreg[3]=Z:
flagreg[2]=Q
fiagreg[01=P
end \
else if(ESUB)
begin
flagreg[3]=Z;
flagreg[l]=B;
flagreg[0]=P;
end
else if(SETCLRF)
begin
flagreg=SYSTE M_DATABUS[3:01;
end
end
endmodule

/ * Accumulator, I/O Module and Serial Module*/

module accumulator!
input elk, //input clock 25MHz
input RESET,
input [7:0] PORTO,
output reg [7:0] PORTl,
input LIN,OOUT,
input LA,OA,OALU,LALU,INCA,DECA,CMA,RR,RL,
inout [7:0] SYSTEM_DATABUS,
inout [8:0] result,
output [7:0] ALU_DATABUS_A,
input baudclk, //baud clock 115200 per second
input c,
input rxin,
input LSIN,OSOUT,
output reg txout=l'bl,
output reg RXF=l'bO,TXF=l'bO,
output reg [7:0] Acc=8'b0);
reg [7:0] data;
reg [7:0] RBUFF;
reg [7:0] TBUFF;
reg [3:0] countrx=4'bl001;
reg\3:0l counttx=4'bl001;
reg t x b = l ' b l ;

//accumulator operations
assign SYSTEM_DATABUS = OA?Acc:'bz;
assign ALU_DATABUS_A = OALU?Acc:'bz;
wire temp;
assign temp = (RR|RL)?((RR?Acc[0]:l'bO)|(RL?Acc[7]:l'bO)):'bz;

always@(negedge elk)
begin
if(LA)
Acc=SYSTEM_DATABUS;
else if{LALU)
Ace = result[7:0];
else if(INCA)
Ace = Acc+1;
else if(DECA)
Ace = Acc-1;
else if(CMA)
Ace = ~Acc;
else if(RR)
begin
Ace = A c c » l ;
Acc[7] = temp;
end
else if{RL)
begin
Ace = A c e « l ;
Acc[0] = temp;
end
else if(RESET)
Acc=8'b0;
else if(LIN)
Acc=PORT0; //input port PORTO
else if(OOUT)
PORTl=Acc; //output port PORTl
else if(LSIN)
Acc=RBVif?;
else if(OSOUT)
begin
TBUFF=Acc; //TBUFF register in serial module
txb=l'bO;
 end
else if(TXF & c)
txb=l'bl;
end

//serial module receiver

alwavs@(posedge baudclk)
begin
if(rxin==0 & countrx==9)
begin
if(countrx)
begin
RXF=l'bO;
RBUFF=8'bO;
RBUFF=RBUFF»1;
RBUFF[7]=rxin;
countrx=countrx-l;
end
end
else if(countrx<=8 & countrx>0)
begin
RBUFF=RBUFF»1;
RBUFF[71=rxin;
countrx=countrx-l;
end
else if{countrx==0)
begin
RXF=l'bl;
countrx=4'bl001;
end
else
begin
RXF=l'bO;
countrx=4'bl001;
end
end

//serial module transmitter

always@(posedge baudclk)
begin
if ((counttx<=8)&&(counttx>=l))
begin
txout=data[Ol;
data[7:01=data[7:0]»l;
counttx=counttx-l;
TXF=l'bO;
end
else if(counttx==0)
begin
txout=l'bl;
counttx=4'bl001;
TXF=l'bl;
end
else if(txb==0)
begin
txout=l'bO;
data=TBUFF;
 counttx=counttx-l;
TXF=l'bO;
end
else
begin
txout=l'bl;
counttx=4'bl001;
TXF=l'bO;
end
end
endmodule

/ * Register set * /
module register_set(
input cll<, //gated clock for register set
input RESET,
input LR0,LR1,LR2,LR3,LR4,LR5,LR6,LR7,
input OER0,OERl,OER2,OER3,OER4,OER5,OER6,OER7,
input OERAL0,OERALl,OERAL2,OERAL3,OERAL4,OERAL5,OERAL6,OERAL7,
inout [7:0] SYSTEM_DATABUS,
output [7:0] ALU_DATABUS_B);
reg [7:0] R0,R1,R2,R3,R4,R5,R6,R7;

assign SYSTEM_DATABUS
{OER0|OERl|OER2|OER3|OER4|OER5|OER6|OER7)?((OER0?R0:8'b0)|(OERl?Rl:8'b0)|(OER2?R2:8'b0)
I (OER3?R3:8'bO) | (OER4?R4:8'b0) | (OER5?R5:8'bO) | (OER6?R6:8'bO) | (OER7?R7:8'bO)):'bz;
assign ALU_DATABUS_B
(OERALOI OERALl 10ERAL210ERAL310ERAL410ERAL510ERAL61 OERAL7)?((OERAL0?R0:8'b0) | (OERALIPR
l:8'b0) I (OERAL2?R2:8'bO) | (OERAL3?R3:8'b0) | (OERAL4?R4:8'b0) | (OERAL5?R5:8'b0) | (OERAL6?R6:8'b0) |
(OERAL7?R7:8'bO)):'bz;

always@{negedge elk)
begin
if(LRO)
RO=SYSTEM_DATABUS;
else if(LRl)
R1=SYSTEM_DATABUS;
else if(LR2)
R2=SYSTEM_DATABUS;
else if(LR3)
R3=SYSTEM_DATABUS;
else if(LR4)
R4=SYSTEM_DATABUS;
else if(LR5)
R5=SYSTEM_DATABUS;
else if(LR6)
R6=SYSTEM_DATABUS;
else if(LR7)
R7=SYSTEM_DATABUS;
else if(RESET)
begin
RO=8'bO;
Rl=8'b0;
R2=8'b0;
R3=8'bO;
R4=8'b0;
 R5=8'b0
R6=8'b0
R7=8'b0
end
end
endmodule

/ * Interrupt Module * /
module interrupt_module(
input elk, //input clock 25MHz
input 10,11,
output reg IFO.IFl,
output reg TMFO=l'bO,
inout 17:0] SYSTEM_DATABUS,
input LINTCON,CLRTMRF);
reg [2:01INTCON=3'bO;
reg 19:0] timer=10'bO;

//external interrupts handling

always@(negedge elk)
begin
if(LINTCON)
INTCON = SYSTEM_DATABUS[2:0];
elseif(INTCON[ll)
begin
if(INTCON[0]==l'bO)
begin
if(IO)
begin
lFO=l'bl;
IFl=l'bO;
end
elseif(ll)
begin
IFO=l'bO;
lFl=l'bl;
end
else
begin
IFO=l'bO;
IFl=l'bO;
end
end
else
begin
if(IO)
begin
IFO=l'bl;
IFl=l'bO;
end
elseif(ll)
begin
IFO=l'bO;
IFl=:l'bO;
end
else
 begin
IFO=l'bO;
IFl=l'bO;
end
end
end
else
begin
IFO=l'bO;
IFl=l'bO;
end
end

//timer interrupt handling

always(a)(negedge elk)
begin
if(CLRTMRF&&INTC0N[2])
begin
TMFO=l'bO;
timer=timer+l;
end
else if(CLRTMRF)
begin
TMFO=l'bO;
end
elseif(INTC0N[2])
begin
if(timer==1023)
begin
TMFO=l'bl;
timer=timer+l;
end
else
begin
timer=timer+l;
end
end
end
endmodule
 Chapter 4
RESULTS AND DISCUSSIONS
The simulation has been performed using ISim. Simulation has been performed for each
module and for the whole processor. Initially simulation is performed on each module
for verifying functionality of control signals corresponding to the respective module.
Figure 4.1 represents simulation of Program Counter Unit. It shows that, when OPC is
high, IMADDRBUS gets PC content. When LIR is high and at falling edge of clock,
PC content is incremented. In figure 4.1, when LPCS control signal is enabled, PCS
stores the value 4, which is Program Counter (2) content incremented by two value.
When OPCS control signal is high and at falling edge of clock, PC gets the value 4,
which is PCS content. When OSTACK control signal is high and at falling edge of
clock, PC is loaded by the value 7, which is STACKPC content.

Figure 4.1 Simulation of Program Counter Unit

Figure 4.2 represents the simulation of Instruction Memory. When RDIM is high,
IMDATABUS gets the Instruction Memory content corresponding to the address
provided by IM_ADDRBUS. For example, when RDIM is high, IM_ADDRBUS
content is 00 0000 0000 0000 0001, IM_DATABUS gets 0000 1000 0000 0110, which
is corresponding to address location 00 0000 0000 0000 0001 of Instruction Memory.

Figure 4.3 represents the simulation of Data Memory. It shows that whenever RDIM is
high, SYSTEM_DATABUS gets the Data Memory content corresponding to the
address provided by DMADDRBUS. When WRDM is high. Data Memory gets
SYSTEM_DATABUS content, corresponding to address provided by DMADDRBUS.
For example, when WRDM is high and SYSTEMDATABUS content is 10101010,
DM_ADDRBUS content is 0000 0000 0001, at falling edge of clock Data Memory with
address location 0000 0000 0001 will be loaded by 10101010.

Figure 4.2 Simulation of Instruction Memory

1,000 ns 1,050 ns

n_o ..c JIL

•_ zi_a_n_ni_o
n_
; M c w o o n x o i X S a ooooooioo ^oooooo xiiinXooooooooo ci])(DOO0oooooioi;
10101010 ) ( ~ ( i i o o o i i i ( oioiiooo~~)( l a i o i f l i ^ xxxxxxxx
IfflXXXXXXX.lT; POQOOOOtt O P 00000(,10101Q10,X XXXXXXJQOOOOa

JMOifXXX

XXJOOOOi

XXX>000(

Figure 4.3 Simulation of Data Memory

Figure 4.4 represents simulation of Accumulator. In Figure 4.4, Accumulator is initially

at zero, when INCA is high and at falling edge of clock, accumulator is incremented by
one, hence becomes 00000001. When OOUT is high, output port PORTl becomes
00000001, which is the current accumulator content. When RL is high, at falling edge
of clock, accumulator becomes 00000010, which is accumulator shifted left by one bit.
When LA control signal is enabled and at falling edge of clock, accumulator is loaded
by 00110011, which is SYSTEM_DATABUS content. When DECA is high and at
falling edge of clock, accumulator is decremented by one, hence becomes 00110010.
When OALU is high, ALU_DATABUS_A becomes 00110010, which is the current
accumulator value. When OA is high, SYSTEMDATABUS gets accumulator content.
 When RR is high and at falling edge of clock, accumulator becomes 00011001, which is
accumulator shifted right by one bit. When CMA is high and falling edge of clock,
accumulator becomes 11100110, which is complemented value of accumulator. When
LIN is high and at falling edge of clock, accumulator becomes 00110011, which is input
port PORTO content. When LALU is high and at falling edge of clock, accumulator
becomes 00000011, which is resuh content (ALURESULT). When RESET is high and
at falling edge of clock, accumulator becomes 00000000, which is the default reset.

INMM llwue 1 1,000 IB 1,05)|« 1,100 m 1,1501» i.roore Lja-B 1.30On! l,350n5 l,-«Ons l.'^SOns 1

rr~i r~-] __j ^ rTsi f^^n — -'-j ^ T1

mwKIKMm-^
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n ifTTT
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n szz X 00110011 : : zzzzzzz
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^••HiPftMa xxxxxxxx 0000000

~x
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m »^J?>3

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,
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r T

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t 1

inrnn
00000001! X 222222222
• iiijtzrz • ~ .•- ' tniiooio X 7fimn
• ^ ^ 9 n...
H ^ ^ ^ ^ ^ l QOOC urn X I 3000001 ' 00000010 X 1 moou X 00110010 X 000] 1001 _ x _ IIOOIID X 001: 3011 X OCOOOOi X ooooooo

Figure 4.4 Simulation of accumulator

Figure 4.5 represents simulation of Register set. In Figure 4.5, registers RO - R7 is

initiated to values 0 - 7 respectively. When LRX is high (where X is 0 - 7) and at falling
edge of clock, corresponding register is loaded by SYSTEM_DATABUS content. For
example. When LRl is high and at falling edge of clock, register Rl becomes
10101010, which is SYSTEMDATABUS content. When OERX is high (where X is 0
- 7), SYSTEM_DATABUS gets corresponding register content. When 0ER4 is high,
SYSTEMDATABUS becomes 00000011, which is register R3 content. When
OERALX is high (where X is 0 - 7), ALU_DATABUS_B gets corresponding register
content. When 0ERAL7 is high, ALUDATABUSB becomes 00000111, which is
register R7 content.
 •95Gns 1,000 n s 1^50 ns 1, icons 1, ISO re 1,200 n s 1 2 5 0 ns 1,300 TS

LA "1
ooococoo
' ' 1, ' : 5101010
)
' •

00000001 }
OOOGCOIO
\
ooaoon X 1111009 >

00000100

OOCOOIQI 1
00000110
)
)?
ijoo^xiu
xxx)Oooa 00000000 X rrrnn x wic l O U X OOOOOOi
: X 22ZZZ2Z2 ;• 00000100 luoooo X oo^xoC'Oi >
KXMOOa
lamn x ( joooioi X 77777777 X oooooin ;• c'.lazin }

1" '^•.'^ f " -1

F • -J

'. .. \
r^
r ~ ~ " ~1
— - L_
•|
r
' ^ r
Figure 4.5 Simulation of Register set

Figure 4.6 represents simulation of ALU unit. When EXOR is high, ALU will perform
AND operation on 8-bit inputs ALU_DATABUS_A and ALUDATABUSB, result is
obtained on ALURESULT. Flag register is labelled as flagreg (4-bit), will update its
content according to the ALU operation. For example, when EXOR is high,
ALU_DATABUS_A is 01011001 and ALU_DATABUS_B is 01010001, hence
ALU_RESULT becomes 001111100. In this case, zero flag (Z) and parity flag (P) will
be updated, but carry flag (C) and borrow flag (B) will remain unchanged.

1,000 ns WSOns 1,100 ns 1,150 ns 1,200 ns WSOns 1,300 n

1 1 r-n
—1 r -1 i i
"^
. •
n n__r™i
• ; x _ t ;• ..™_
1
p-J ""' .1
• 1
r—' - 1
r"
xxxx XXX X 1 DOOOIIO X 0000 XJll
r
X 0000100*
-T X oeioiioi ) • 10110000 X iiiiiio X u i ln i l
xxxx XXX X lOlOOOO X OOOC KTOl X OOOOIOC' X 0101000! ) • 00010101 X <\ 0000100 X oooa )000
XXXWOOOOC : ZZZZ2ZZZZ X _ 0 .1010110 X 0000 0100 X i i i m i : 1 X 001111100 ) ' 000010000 X 1 njoocoio X 00001 0000
0000 X oc 11 X 0010 X 0011 X oui 1110

_j:-r_L_, .,.^^^
____j
r
rr~~~ r~"
Figure 4.6 Simulation of ALU unit
Figure 4.7 represents simulation of Interrupt module part 1. When LINTCON is high
and at falling edge of clock, INTCON register becomes 110, which is
SYSTEMDATABUS content. When INTCON register's MSB bit is 1 (bit 2), timer
interrupt will be enabled. When bit 1 of INTCON register is 1, both external interrupts
is will be enabled. When LSB bit (bit 0) of INTCON register is 0, interrupt 11 is not
masked, thus all three interrupt are enabled. In Figure 4.7, when 10 interrupt is high, IFO
flag is set. When II interrupt is high, IFl flag is set. When both 10 and II are high, only
IFO flag is set because it is having highest priority. It shows that timer flag TMFO is low
and timer register is incrementing in each clock cycle as timer interrupt is enabled.

lj20Qn

x::!L m _Eia_-

y, 00000110 X

y, oooMooo r y OOOOOOOOKT; : oooaxBoirXoi 30000i(irX"Mooc a l o r x ooooooei FYocoooooiii;: oooQOiiiooo )Ca o

Figure 4.7 Simulation of interrupt module part 1

Figure 4.8 represents simulation of Interrupt module part 2. In Figure 4.8, when timer
register reaches its maximum value 1023, timer flag TMFO is set. When CLRTMRF is
high and at falling edge of clock, TMFO is cleared.

J_

Figure 4.8 Simulation of interrupt module part 2

Figure 4.9 represents simulation of Serial Module. In Figure 4.9, rxin is input serial port
and txout is output serial port. Both ports are 1 at idle state. In Figure 4.9, elk is the
system clock at 25MHz and baudclk is baud rate required for serial communication,
which is 115200 per second. When rxin becomes 0, by UART protocol start bit has
arrived which is followed by 8-bit data. RXF flag is set when reception is completed,
which will be high for one baudclk. The 8-bit received data is stored in RBUFF register.
 When LSIN is high and at falling edge of clock, accumulator becomes 11011100, which
is RBUFF content. When OSOUT is high and at falling edge of clock, TBUFF becomes
11011100, which is accumulator content. From next rising edge of baudclk, txout will
transmit the 8-bit data on TBUFF (11011100) serially by UART protocol. After
completion of transmission TXF flag is set, which will be high for one baudclk.

^ ^ ^ ^ ^ J ^ ^ ^ ^
2C'ts
1111t • r i 1 1 1 1 ] 1 1 ] 1 1 «« (Dis
1.1J
, sous , lOOus 12) us
J 1 1 1 1 1 I 1 1 1 1 1 1 1 1 11 1 1 1 1 1 I 1 1II11
l«us IB.JS ISOus aou! :JK5 ,

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i ^ 9 ^ H i _ p _ n -E_FL aJiLE 1 m m^ ^ ™
n n n n r n D n n f:3_n_qLJILIW^
^ ^ H ^ ^ H M«li;f? ^ifH LJKil&Jm. ,:»iiJ. 1 -,-1.' , - , . .
, ^ ,, ^ L ^ „^ ,„^^
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r~~i
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UAU^^H 0001 DOOO
X uoiiia

^ ^ ^ H H M R mjoooa X eoooooo; XacQi !»...X1U0_XM1 ...X11I11...X 110 1100

oooooou K lamoo

Figure 4.9 Simulation of serial module

Figure 4.10 represents the simulation of control unit. In figure 4.10, Instruction Memory
IM is having data on 9 address locations (0-8). By referring to appendix A, the Opcode
corresponding to each address location can be find out. Instructions are MOVI A,
00000110 (IM [0]), MOV R6, A (IM [1]), MOVI A, 00000101 (IM [2]), ADD A, R6
(IM [3]), JUMP 00 0000000000000111 (IM [4] and IM [5]), DEC A (IM [6]), INC A
(IM [7]), HALT (IM [8]). By referring to appendix B, control signals corresponding to
each instruction and in which tstate it is occurred, can be find out. In Figure 4.10, TFl
represents fetch cycle, TXl represents execution cycle 1 and TX2 represents execution
cycle 2. Instruction in IM [0] is having OPC, RDIM and LIR in TFl and OIRSYS and
LA in TXl cycle. Instruction in IM [1] is having OPC, RDIM and LIR in TFl and LR6
and OA in TXl cycle. As control signals in fetch cycle is common for all-,fi^omnext
instruction onwards control signals in execution cycle (TXl and TX2) will be
considered. Instruction in IM [2] is having OALU, 0ERAL6, EADD and LALU in TXl
cycle. Instruction in IM [4] and IM [5] (JUMP) is having OPC, RDIM, OIRPC and
LPCR in TXl cycle and LPC and OPCR in TX2 cycle. Instruction in IM [6] is having
DECA in TXl cycle and instruction in IM [7] is having INCA in TXl cycle. IM [8] is
 1,000 ns 1,050 (IS 1,100 ns I,l50n6 1,2X1 ns 1,250 ns 1,300 ns 1,350 ns

QOOO X 0001 ^
1

T
r ••' - • ^' -1
r~
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l-.-zi: ""
F . ....^,.^ I ,.,.^'
^
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trr
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77777777 "X" X 0000010

ZX DC xx DC
y ~ i 3000101 ~X~
ooooQoooa...")(ooi oiooooorXooo^i Moor)(ooooioooo CrXoioooiiiior; [ IflOOi MOOOOOOOOO yploit x:
3100 i~XiioeoooQo5~
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IDC
ioSL~)(ooooMooo Cyoooiouooo: :ooooiooooQ.."X5ii ooitiiory" lOOOOOOOOOO 0000 xzx 0101001000. .00000000000000
OOOOIOOOOOOOOIIC OOOIOIIOOOOOOOOO OOOOlOOOOOOOOiei OlOOOmiOOOOOOO lOOOOOOOOOOOOOOO 0000000000000111 O1010100000( 0000 OIOIOOIOOOOOO. o
ooooicnoc)oooiio
OOOIOIIOC MOOOOO
OOOOMOOC XJOOlOl
010001111X100000
tOOOOOOOG 1000000
OOOOOOOOOOOOlll
OIOIOIOOC lOOOOOO
010100 IOC n o o o o o
UOOOOOOC3000000

Figure 4.10 Simulation of Control unit

HALT state, it stops fetching next instructions, an interrupt is required to exit from halt
state. The control unit will start fetch and execute from IM [0] until it reaches halt state.
For example consider the instruction ADD A, R6, which is at IM [3]. In fetch cycle
(TFl) PC content is 3, as OPC is high IMADDRBUS gets PC content (3). RDIM is
also high, thus IM_DATABUS gets the 16-bit Opcode 0100011110000000 (ADD A,
R6) corresponding to address provided by IMADDRBUS. LIR is high on fetch cycle,
hence at falling edge of clock. Instruction Register (IR) is loaded by 16-bit Opcode and
PC is incremented by one. Thus by the end of TFl cycle PC becomes 4 and ready for
fetching of next instruction during the execution of current instruction. At rising edge of
next clock cycle, IR content is loaded to IRX register, which is used for decoding the
instruction and generating control signals corresponding to the Opcode provided. As IR
content is changed at every falling edge of clock and we need Opcode to be stable for
one full clock cycle for proper execution of instruction by pipelining architecture, IR
content is transferred to IRX. During execution cycle (TXl) OALU, 0ERAL6, EADD
and LALU are high. As OALU is high, ALU_DATABUS_A gets accumulator content
(00000101) and as 0ERAL6 is high, ALUDATABUSB gets register R6 content. As
EADD is high, result of addition is on ALU_RESULT (00001101). When LALU is
high and at falling edge of clock, accumulator (ace) becomes 00001101, which is
ALURESULT content. In flag register ZCBP, zero flag (Z), carry flag (C) and parity
flag (P) are updated. In Figure 4.10, TXl and TFl are high during same time for most
part of execution, which shows the pipelining architecture and TX2 is high only during
the execution of JUMP instruction (branching instruction), which is an exception to the
pipelining architecture. In Figure 4.10, DT, ALU, BR and MIO represents type of
instruction, which are data transfer, arithmetic and logical, branching and machine
control and I/O instructions respectively.

The Table 4.1 presents a simple twenty-line assembly language program for simulation.
In Table 4.1, IM addr represents instruction memory address and ISR is Interrupt
Service Routine. The Table 4.2 shows the device utilization of the Spartan-3E Starter
kit FPGA board. The Figure 4.11, 4.12 and 4.13 shows the simulation results of the
proposed 8-bit RISC processor with pipeline architecture for the program in Table 4.2.

Simulation results in Figure 4.11 shows the control signals and clock signals
corresponds to Register set and Data Memory. RCLK and DMCLK are the gated-
clock inputs corresponding to Register set and Data Memory, which are activated only
when instruction corresponding to loading a memory/general-purpose register is
fetched.

In Figure 4.12, Accumulator is represented as ace with initial value 01010010 and flag
register is represented as ZCBP. It also shows interrupt flags and relevant buses used by
the processor for executing the given program. It shows that the STACKPC stores
current PC value whenever an interrupt flag is raised, PCS stores address of next
instruction after jump instruction (11) and PCR store address of the next instruction to
be executed (19), while a branching instruction is being executed.
In Figure 4.13, DT, ALU, BR and MIO represents type of instruction, which are data
transfer, arithmetic and logical, branching and machine control and I/O instructions
respectively. The tstates TFl, TXl and TX2 are also shown, which behaves in different
manner, while a branching instruction is being executed or an interrupt flag is raised.

Control Unit will generate 59 control signals and 4 clock signals while simulating the
program in Table 4.1, but for convenience, by Figure 4.11, 4.12 and 4.13, major part of
total simulation is shown.

Table 4.1 Twenty-instruction program for simulation

IM addr Opcode Mnemonic Description

0 0111000000000010 EDINTEROIO Enable interrupts 10 & 11
1 0000100000000110 MOVIA,00000110 00000110 => A
2 0001011000000000 MOV R6, A A=>R6
3 0000100000000101 MOVI A, 00000101 00000101-> A
4 0001010100000000 MOV R5, A A->R5
5 0000100000000011 MOVI A, 00000011 00000011 => A
6 0001001100000000 MOV R3, A A => R3
7 0100011110000000 ADD A, R6 A+R6 - > A
8 1100100000000000 SAVE PC PC => PCS
9 1000000000000000 JUMP 00 Jump to address 19
10 0000000000010011 0000000000010011
11 0100100011000000 SUB A, R3 A-R3 => A
12 0101100000000000 RL Rotate A left by 1 bit
13 0011000000000001 MOV 000000000001, A A=>DM[000000000001]
14 1100000000000000 HALT Stop operations
15 0000100000000111 MOVI A, 00000111 00000111 => A
16 1101000000000000 RETI Return from ISR
17 0000100000000010 MOVI A, 00000010 00000010 => A
18 1101000000000000 RETI Return from ISR
19 0100011101000000 ADD A, R5 A+R5 => A .
20 1100110000000000 RES PC PCS => PC
 Table 4.2 Device utilization of the Spartan-3E Starter kit FPGA board
Logic Utilization Used Available Utilization
Number of Slice Flip-Flops 291 9312 3%
Number of 4 input LUTs 3374 9312 36%
Number of occupied Slices 1821 4656 39%
Number of bonded lOBs 166 232 71%

UXOra 1.300 m 1,^00 rt 1,500 (« 1,600ns IjTOCns l,«X!ns i.m)ii! 1 2.000m ijmni^

r —1
r—J
fSSl

ra n rJ
n
L_ElL_Cn_ ca..n I i_a_n_ o n e 3 a n n n n D n
z X 1 X z
r-~i
r~n
o r rT tr-i t —1 Fjn
Ffe^ 1—1 r n p-»Ti

Figure 4.11 Simulation results of proposed processor part I

L .. . (
J = l

] c r T 3 CZl zia_ =3_ ji^^n

EZL zia_ ZIL_CI3

STOoc:x5rirxnrogyrxMo-xooi7)0(;g::xr>n
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omooio "X 00000110 y oooooiai X~«ooooii X~ ^ oo<3ubo Xooo.-X oooiooio"
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tQUlOOCOOOOOOCia^eOCOlOOQQgOQt m,OQQ101iaOQOOOQOO.QO<»100000C )O10l,0OOlOlO10OO0OOCC,0OOOIO0CO WOO11.0OO1QO1SQQO0O t00,0100OH 10000000. HOC IQCOOOOOOOOO.IQOOO) OOOOOOQOOOffllOOWOOOOQlSO

«Mxxxx»--XooO(iiQioooQor^kcoooooo«xxxxxiX5i|rXiiiBiiq»rx^ X^^QC"

Figure 4.12 Simulation results of proposed processor part II

Figure 4.13 Simulation results of proposed processor part III
 Chapter 5
CONCLUSION
FPGA based 8-bit RISC processor with pipelining and clock-gating technique is
designed. ISim is used for performing simulation. The design is implemented on Xilinx
Spartan-3E Starter kit FPGA board at 25MHz, on which all 34 instructions are verified.
Pipelining technique yields better performance as the processor executes one instruction
on every clock cycle. Clock gating applied to specific modules helps in reduction of
power to a certain extent. Serial communication using UART protocol is successfully
carried out at a baud rate of 115200. The enhanced feature of Xilinx Spartan-3E
voluntarily reduces the cost per logic cell designed. RISC processor's range of
application includes signal processing, convolution application, commercial data
processing, used in supercomputers such as the K computer, smart phones, tablets and
real-time embedded systems.
 REFERENCES
[I] Sivarama P.Dandamudi, "A Guide To RISC Processor For Programmers And
Engineers", Springer.

[2] Sivarama P.Dandamudi, "Introduction to Assembly Language Programming For

Pentium and RISC Processors", Springer.

[3] J. Hennessy and D. Patterson, Computer Architecture: A Quantitative Approach, 4th

ed., 2007.

[4] J. Ball, "Designing Soft-Core Processors for FPGAs Processor Design", in

Processor Design: System-on-Chip Computing for ASICs and FPGAs, J. Nurmi, 1st Ed:
Springer Netherlands, 2007, pp. 229-256.

[5] Jagrit Kathuria, M.Ayoub khan, Arti noor, "A review of clock gating techniques",
International Journal of Electronics and Communication Engineering, Vol. 1, No. 2
pp.l06-114,Aug2011.

[6] Dr.M.Kamaraju, G.Chinavenkateswararao, "Low Power Reduced Instruction Set

Architecture Using Clock Gating Technique", International Journal of VLSI design &
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 APPENDIX A
INSTRUCTION SET ARCHITECTURE
DATA TRANSFER INSTRUCTIONS

l.MOVA,RX RX => A where X = 0, 1, 2, 3, 4, 5, 6, 7 or 8

Group Mem/ Im
S/D Register code Don't care
code Reg data
0 0 0 0 0 0/1 0/1 0/1 x x x x x x x x

2. MOV RX, A ;A=>RX

Group Mem/ Im
S/D Register code Don't care
code Reg data
0 0 0 1 0 0/1 0/1 0/1 x x x x x x x x

3. MOV A, M ;M=>A
Group Mem/ Data Memory address
S/D
code Reg
0 0 1 0 @ @ @ @ @ @ @ \ @ @ @ @ @

4. MOV IVI,A ;A=>M

Group Mem/ S/D Data Memory address
code Reg
0 0• 1 1 @ @ @ @ @ @ @ @ @ @ @ @

5. MO VI A, Immediate data ; Immediate data => A

Group Mem/ S/D Im Don't care Immediate data
code Reg data
0 0 0 0 1 X X X # # # # # # # #

A = Accumulator
M == Data Memory address
RX = Register, can be any one of RO, Rl, R2, R3, R4, R5, R6 or R7
Group code = 00 represents data transfer operation
Mem = Memory => presence denoted as 1
Reg = Register ==> presence denoted as 0
S - Source => presence denoted as 0
D = Destination => presence denoted as 1
Im data=Immediate data =>presence denoted as 1
Register code = startsfrom000 to 111
X = don't care bits
@ = address bits
# = data bits
 ARITHMETIC AND LOGICAL INSTRUCTIONS

1. AND A, RX ; A <= A and RX update flags

Group ALU/ACC/CLR/ ALU code Reg code Don't care
code INTER op
0 1 0 0 0 0 0 0/1 0/1 0/1 X X X X X X

2. XOR A, RX ; A <= A xor RX update flags

Group ALU/ACC/CLR/ ALU code Reg code Don't care
code INTER op
0 1 0 0 0 0 1 0/1 0/1 0/1 X X X X X X

3. OR A, RX ; A <= A or RX update flags

Group ALU/ACC/CLR/ ALU code Reg code Don't care
code INTER op
0 1 0 0 0 1 0 0/1 0/1 0/1 X X X X X X

4. ADD A, RX ; A <= A + RX update flags

Group ALU/ACC/CLR/ ALU code Reg code Don't care
code INTER op
0 1 0 0 0 1 1 0/1 0/1 0/1 X X X X X X

5. SUB A, RX ;A<=A-RX update flags

Group ALU/ACC/CLR/ ALU code Reg code Don't care
code INTER op
0 1 0 0 1 0 0 0/1 0/1 0/1 X X X X X X

6.CMA ; A <= ~A
Group ALU/ACC/CLR/ Ace code Don't care
code INTER op
0 1 0 1 0 0 0 X X X X X X X X X

7. INC A ; A <= A+1

Group ALU/ACC/CLR/ Ace code Don't care
code INTER op
0 1 0 1 0 0 1 X X X X X X X X X

ALU/ACC/CLR/INTER op
ALU = ALU operation => denoted as 00
ACC = Accumulator operation => denoted as 01
CLR = Clear operation => denoted as 10
INTER = Interrupt operation => denoted as 11
Group code = 01 represents Arithmetic and logic operation
8. DEC A ; A <= A-1
Group ALU/ACC/CLR/ Ace code Don't care
code INTER op
0 1 0 1 0 1 0 X X X X X X X X X

9.RRA . ; rotate Accumulator right by 1 bit

Group ALU/ACC/CLR/ Ace code Don't care
code INTER op
0 1 0 1 0 1 1 X X X X X X X X X

lO.RL^^L ; rotate Accumulator left by 1 bit

Group ALU/ACC/CLR/ Ace code Don't care
code INTER op
0 1 0 1 1 0 0 X X X X X X X X X

11. SET<CLRF 4-bit data ; clear/set flag bits

Group ALU/ACC/CLR/ clear Don't care 4-bit data
code INTER op flag/timer
0 1 1 0 0 0 X X X X X X # # # #

12. CLRTMRF ; clear TIMER flag

Group ALU/ACC/CLR/ clear Don't care
code INTER op flag/timer
0 1 1 0 0 1 X X X X X X X X X X

13. EDINTER 3-bit data ; To control interrupt's operations

Group ALU/ACC/CLR/ Don't care 3-bit data
code INTER op
0 1 1 1 X X X X X X X X X # # #

BRANCHING INSTRUCTIONS

1. JUMP addl8 ; Jump (0 18-bit address addl8

Group Instruction MSB Don't care
code code bits
1 0 0 0 0 @ @ X X X X x ] x X X X

Instruction memory address

@ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @

2. JZ addl8 ; Jump f0 18-bit address addl8 if zero flag is 1

Group Instruction MSB Don't care
code code bits
1 0 0 0 1 @ @ X X X X X X X X X

Instruction memory address

@ @ @ @ @ @ @ @ @ @ @ @ @ @ @ | @
3. JC add18 ; Jump to 18-bit address addl8 if carry flag is 1
Group Instruction MSB Don't care
code code bits
1 0 0 1 0 @ @ x x x x x x x x X

Instruction memory address

@ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @

4. JB add18 ; Jump to 18-bit address addl8 if borrow flag is 1

Group Instruction MSB Don't care
code code bits
1 0 0 1 1 @ @ X X X X X X X X X

Instruction memory address

@ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @

5. JP addl8 ; Jump to 18-bit address addl8 if parity flag is 1

Group Instruction MSB Don't care
code code bits
1 0 1 0 0 @ @ X X X X X X X X X

Instruction memory address

@ @i @ @ @ @ @ @ @ @ @ @ @ @ @ @

MSB Bits = 2-bit MSBs of Instruction memory address

Parity flag is set when resultant of ALU operation contains odd number of ones.

MACHINE CONTROL AND JO INSTRUCTIONS

1. HALT ; To stop operations

Group MC/ Instruction Don't care
code 10 code
1 1 0 0 0 0 X X X X X X X ?C X X

2. RESET ; Reset Ace, PC, RX

Group MC/ Instruction Don't care
code 10 code
1 1 0 0 0 1 X X X X X X X 5C X X

3. SAV PC ; Save PC+2 value in PCS Register

Group MC/ Instruction Don't care
code 10 code
1 1 0 0 1 0
it
 "1
4. RES P( ; Restore PC with PCS content
Group MC/ Instruction Don't care
code 10 code
1 1 0 0 1 1 x x x x x x x x X X

5.RETI ; Restore PC with STACKPC content

Group MC/ Instruction Don't care
code 10 code
1 1 0 1 0 0 x x x x x x x x x x

6. WAIT TXF ; Wait until TXF flag gets set

Group MC/ Instruction Don't care
code 10 code
1 1 0 1 0 1 x x x x x x x x x x

7. WAIT RXF ; Wait until RXF flag gets set

Group MC/ Instruction Don't care
code 10 code
1 1 0 1 1 0 x x x x x x x x X X

8. IN PO ; Accumulator gets Port PO content

Group MC/ Instruction Don't care
code 10 code
1 1 1 0 0 X X X X X X X X X X X

9. OUT PI ; Accumulator sends its content to Port PI

Group MC/ Instruction Don't care
code 10 code
1 1 1 0 1 X X X X X X X X X X X

10. SIN RBUFF ; Accumulator gets RBUFF content

Group MC/ Instruction Don't care
code 10 code
1 1 1 1 0 X X X X X X X X X ) C X

11. SOU!r TBUFF ; Accumulator sends its content to TBUFF

Group MC/ Instruction Don't care
code 10 code
1 1 1 1 1 X X X X X X X X X X X

MC/IO
MC = Machine control instruction => presence denoted as 0
10 = Input/output instruction => presence denoted as 1
 APPENDIX B
MICRO OPERATIONS
DATA TRANSFER INSTRUCTIONS

1. MOV A, RX
TFl TXl

PC -> IM

IMdata -> IR
RX -> A
PC+1 -> PC

OPC
OERX
RDIM
LA
LIR

2. MOV RX, A
TFl TXl

PC -> IM

IMdata -> IR A->RX

PC+1 -> PC

OPC
LRX
RDIM
OA
LIR

3. MOV A, M
TFl TXl

PC->IM
IRX[11:0] -> DM
IMdata -> IR
DMdata->A
PC+1-> PC

OPC RDDM

RDIM OIRDM

LIR LA
4. MOV M, A
TFl TXl

PC->IM
IRX[11:0]->DM
IMdata -> IR
A->DMdata
PC+1 -> PC

OPC WRDM

RDIM OIRDM

LIR OA

5. MOVI A, Immediate data

TFl TXl

PC -> IM

IMdata->IR IRX[7:0]->A

PC+1-> PC

OPC
OIRSYS
RDIM
LA
LIR

At the positive edge of every TXl cycle of all instructions, IR content is moved to IRX
for execution of instruction

ARITHMETIC AND LOGICAL INSTRUCTIONS

I. AND A, RX
TFl TXl

PC->IM

IMdata -> IR A<-Aand RX

PC+1-> PC

OALU

OERALX
OPC
BAND
RDIM
LALU
LIR
update flags
2. XOR A, RX
TFl TXl

PC -> IM

IMdata -> IR A <- A xor RX

PC+1 -> PC

OALU

OPC OERALX

RDIM EXOR

LIR LALU

update flags

3. OR A, RX
TFl TXl

PC->IM

IMdata->1R A <- A or RX

PC+1 -> PC

OALU

OPC OERALX

RDIM EOR

LIR LALU

update flags
4. ADD A, RX
TFl TXl

PC->IM

IMdata -> IR A <- A + RX

PC+1 -> PC

OALU

OERALX
OPC
EADD
RDIM
LALU
LIR
update flags

5. SUB A, RX
TFl TXl

PC -> IM

IMdata -> IR A <- A - RX

PC+1 -> PC

OALU

OERALX
OPC
ESUB
RDIM
LALU
LIR
update flags

6.CMA
TFl TXl

PC -> IM

IMdata -> IR A<-~A

PC+1 -> PC

OPC

RDIM CMA

LIR
7. INC A
TFl TXl

PC -> IM

IMdata -> IR A <- A + 1

PC+1 -> PC

OPC

RDIM INCA

LIR

8. DEC A
TFl TXl

PC->IM

IMdata -> IR A <- A-1

PC+1 -> PC

OPC

RDIM DECA

LIR

9.RRA
TFl TXl

PC -> IM

IMdata->IR A[7]<-A[0]

PC+1 -> PC A[n] <- A[n+1] ; n=0,l,2,3A5,6

OPC

RDIM RR

LIR
lO.RLA
TFl TXl

PC -> IM

IMdata -> IR A[0]<-A[7].

PC+1 -> PC A[n+1] <- A[n] ; n=0,l,2,3,4,5,6

OPC

RDIM RL

LIR

11. SETCLRF 4-bit data

TFl TXl

PC->IM

IMdata->IR IRX[3:0] -> FLAG REGISTER

PC+1 -> PC

OPC
OIRSYS
RDIM
SETCLRF
LIR

12. CLRTMRF
TFl TXl

PC -> IM

IMdata->IR TMFO=>0

PC+1 -> PC

OPC

RDIM CLRTMRF

LIR
13. EDINTER 3-bit data
TFl TXl

PC -> IM

IMdata->IR IRX[2:0] -> INTCON REGISTER

PC+1 -> PC

OPC
OIRSYS
RDIM
LINTCON
LIR

BRANCHING INSTRUCTIONS

1. JUMP addl8
TFl TXl TX2

PC->IM PC->IM

IMdata -> IR IMdata -> PCR[15:0] PCR->PC

PC+1 -> PC IRX[10:9] -> PCR[17:16]

OPC
OPC
RDIM LPC
RDIM
OIRPC OPCR
LIR
LPCR

2. JZ addl8
TFl TXl TX2

PC->IM PC->IM

IMdata->IR IMdata->PCR[15:0]
PCR -> PC
PC+1 -> PC IRX[10:9] -> PCR[17:16]

OPC OPCR
OPC
RDIM check zero flag
RDIM
OIRPC if Z=l LPC is set
LIR
LPCR elseifZ=OINCPCisset
3. JC addl8
TFl TXl TX2

PC -> IM PC->IM

IMdata->IR IMdata -> PCR[15:0] PCR -> PC

PC+1 -> PC IRX[10:9] -> PCR[17:16]

OPC OPCR
OPC
RDIM check carry flag
RDIM
OIRPC If C=l LPC is set
LIR
LPCR elseifC=OINCPCIsset

4. JB addl8
TFl TXl TX2

PC->IM PC -> IM

IMdata -> IR IMdata -> PCR[15:0] PCR -> PC

PC+1 -> PC IRX[10:9] -> PCR[17:16]

OPC OPCR
OPC
RDIM check borrow flag
RDIM
OIRPC If BF=1 LPC is set
LIR
LPCR elseifBF=OINCPCisset

5. JP addl8
TFl TXl TX2

PC -> IM PC->IM

IMdata -> IR IMdata -> PCR[15:0] PCR -> PC

PC+1 -> PC IRX[10:9] -> PCR[17:16]

OPC OPCR
OPC
RDIM check parity flag
RDIM
OIRPC if P=l LPC is set
LIR
LPCR elseif P=OiNCPCisset
 MACHINE CONTROL AND lO INSTRUCTIONS

I.HLT
TFl TXl

PC->IM
Stops operations. An interrupt is
IMdata -> IR
necessary to exit from the halt state.
PC+1 -> PC

OPC

RDIM -

LIR

2. RESET
TFl TXl

PC->IM

IMdata->IR RESET PC, A, RX

PC+1 -> PC

OPC

RDIM RESET

LIR

3. SAV PC
TFl TXl

PC -> IM

IMdata -> IR PC+2 -> PCS

PC+1 -> PC

OPC

RDIM LPCS

LIR
4. RES PC
TFl TXl

PC->IM

IMdata -> IR PCS-> PC

PC+1 -> PC

OPC

RDIM OPCS

LIR

5. RETI
TFl TXl

PC->IM

IMdata -> IR STACKPC -> PC

PC+1 -> PC

OPC

RDIM OSTACKPC

LIR

6. WAIT TXF
TFl TXl

PC->IM

IMdata -> IR . Waits until TXF flag gets set

PC+1 -> PC

OPC

RDIM -

LIR
7. WAIT RXF
TFl TXl

PC -> IM

IMdata -> IR Waits until RXF flag gets set

PC+1 -> PC

OPC

RDIM -

LIR

8. IN PO
TFl TXl

PC -> IM

IMdata -> IR PO->A

PC+1 -> PC

OPC

RDIM LIN

LIR

9. OUT PI
TFl TXl

PC->IM

IMdata->IR A->P1

PC+1 -> PC

OPC

RDIM OOUT

LIR
10. SIN RBUFF
TFl TXl

PC->IM

IMdata->IR RBUFF-> A

PC+1 -> PC

OPC

RDIM LSIN

LIR

ll.SOUTTBUFF
TFl TXl

PC -> IM

IMdata -> IR A->TBUFF

PC+1 -> PC

OPC

RDIM LSIN

LIR

V5/^^__j^.