Digital Integrated Circuits

(83-313)

Lecture 4:
Technology Scaling
Semester B, 2016-17
Lecturer: Dr. Adam Teman
TAs: Itamar Levi,
Robert Giterman

2 April 2017
Disclaimer: This course was prepared, in its entirety, by Adam Teman. Many materials were copied from sources freely available on the internet. When possible, these sources have been cited;
however, some references may have been cited incorrectly or overlooked. If you feel that a picture, graph, or code example has been copied from you and either needs to be cited or removed,
please feel free to email [email protected] and I will address this as soon as possible.
 Motivation
• If transistors were people… Courtesy: Intel 2011

• Now imagine that those 1.3B people could fit onstage in the original music hall.
• That’s the scale of Moore’s Law.

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 Lecture Content

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 3
1 2
Current and Future
Moore’s Law Scaling Models
Trends

Moore’s Law

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 Moore’s Law
• In 1965, Gordon Moore noted that the number of
components on a chip doubled every 18 to 24 months.
• He made a prediction that semiconductor technology
will double its effectiveness every 18 months

Electronics, April 19, 1965.

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 Computersciencezone.org

Moore’s Law

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 Reports of my death were greatly exaggerated

"In my 34 years in the semiconductor industry, I have

witnessed the advertised death of Moore’s Law no less
than four times. As we progress from 14 nanometer
technology to 10 nanometer and plan for 7 nanometer
and 5 nanometer and even beyond, our plans are proof
that Moore’s Law is alive and well“
7 Bryan Krzanich, CEO Intel, April 2016
 Technology supporting Moore’s Law

Courtesy: Intel

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 Moore’s Law Today (2016)
Intel Xeon E5-2600 V4 IBM 7nm Test Chip

• 14nm “Broadwell”
• 22 Cores
• 2.2 GHz • 7nm
• 55MB Cache • EUV Photolithography
• 416 mm2 • SiGe channels
• 7.2 Billion Transistors • Introduced July 2015
• 456 mm2 Die size
• Introduced March 31, 2016

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 Evolution in Memory Complexity

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 Die Size Growth
100
Die size (mm)

P6
486 Pentium ® proc
10 386
286
8080 8086
8085 ~7% growth per year
8008
4004 ~2X growth in 10 years

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1970 1980 1990 2000 2010 Apparently, that doesn’t
Year apply anymore…

Die size grows by 14% to satisfy Moore’s Law

Courtesy, Intel
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 Moore was not always accurate

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 Teman’s Law

~25 cm

~8 cm

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 Cost per Transistor

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 Scaling…

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 Goals of Technology Scaling
• Make things cheaper:
• Want to sell more functions (transistors) per chip for the same money
• Build same products cheaper, sell the same part for less money
• Price of a transistor has to be reduced
• But also want to be faster, smaller, lower power
Rabaey’s Law of Playstations

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 Technology Scaling – Dennard’s Law
• Benefits of scaling the dimensions by 30% (Dennard):
• Double transistor density
• Reduce gate delay by 30%
(increase operating frequency by 43%)
• Reduce energy per transition by 65%
(50% power savings @ 43% increase in frequency

• Die size used to increase by 14% per generation

• Technology generation spans 2-3 years

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 3
1 2
Current and Future
Moore’s Law Scaling Models
Trends

Scaling Models

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 Dennard Scaling
• In 1974, Robert Dennard of IBM described the MOS scaling
principles that have accompanied us for forty years.
• As long as we scale all dimensions of a MOSFET by the same
amount (S), we will arrive at better devices and lower cost:
• L – 1/S
• W – 1/S
• tox – 1/S
• Na – S
• Vdd – 1/S
• VT – 1/S

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 Reminder – our simple timing/power models
• In our previous course, we developed the unified model for MOS
transistor conduction: I  K V V
DS GT  0.5V 2  1  V
DSeff DSeff DS 
K  nCoxW L
VDSeff  min VGT , VDS , VDSAT 
Cox 
 ox
tox
I on  K V 2
n GT

VDD
Ron 
I on
tpd  Ron Cg
Pdyn  f  C VDD
2

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 Dennard (Full) Scaling for Long Transistors
L  S 1 Property Sym Equation Calculation Scaling Good?

W  S 1 Oxide Capacitance Cox  ox tox 1 S 1 S

tox  S 1 Device Area W L 1 1 1 S2
A S S
VDD  S 1 Gate Capacitance Cg Cox W  L S  S 1  S 1 1S
VT  S 1 Transconductance Kn nCoxW L S  S 1 S 1 S
NA  S Saturation Current K nVDSatKV
n GTGT DSat  S SSS1 S
Ion V 2
V 2 1 1S
On Resistance VDD I on S 1 S 1 1
VDSat  crit L
Ron
Intrinsic Delay tpd RonCg 1 S 1 1S
Power Pav f  C VDD
2
S  S 1  S 2 1 S2
Power Density PD Pav A S 2 S 2 1
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 Dennard Scaling
• This previous slide showed the principal that has led to scaling for
the last 50 years.
• Assume that we scale our process by 30%
every generation.
1  0.7 
 S 2
S
• Therefore, if the area scales by 1/S2=1/2,
our die size goes down by 2X every generation!
Sorry… I couldn’t resist!
• In addition, our speed goes up by 30%!
• And our power also gets cut in half, without any increase in power density.
• We have hit one of those rare win-win free lunch situations!
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 But what if we want more speed?
• We saw that
t pd  Cg VDD I on

• We can aggressively increase the speed by keeping the voltage constant.

1
I on  K V 2
n GT  S  t pd  S 1 S  1 S 2

• This led to the Fixed Voltage Scaling Model,

which was used until the 1990s (VDD=5V)

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 Moore’s Law in Frequency

24 Nature
 Fixed Voltage Scaling
VDD  1 Property Sym Equation Calculation Scaling Good?

1 Oxide Capacitance  ox tox 1 S 1

LS Cox S

1
Device Area A W L 1
S S 1 1 S2
W S Gate Capacitance Cg Cox W  L S  S 1  S 1 1S
1
tox  S Transconductance nCoxW L
Kn S  S 1 S 1 S
1
VT  S Saturation Current Ion
2
K nVGT S 1 S
NA  S On Resistance Ron VDD I on 1S 1S
Intrinsic Delay tpd RonCg S 1  S 1 1S
2

Power Pav f  C VDD

2
S 2  S 1 1 S
Power Density PD Pav A S S 2 S3
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 Fixed Voltage Scaling – Short Channel
• What happens with velocity saturated devices?

I on  K nVDSat VGT  VDSat   S  S 1 1  1

• So the on current doesn’t increase leading to less effective speed increase.

1
t pd  RonCg  1 S 1 S

• The power density still increases quadratically!

1 2
PD  fCV 2
DD A  S  S 1 S S 2

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 Power density (2004 expectation)

The Power
Density Crisis
Patrick Gelsinger, Intel
ISSCC 2001

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 What happens as a result of power density…?

Let’s remove the CPU fan…

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 What actually happened?

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 Technology Scaling Models
• Fixed Voltage Scaling
• Supply voltages have to be similar for all devices (one battery)
• Only device dimensions are scaled.
• 1970s-1990s
• Full “Dennard” Scaling (Constant Electrical Field)
• Scale both device dimensions and voltage by the same factor, S.
• Electrical fields stay constant, eliminates breakdown and many secondary
effects.
• 1990s-2005
• General Scaling –
• Scale device dimensions by S and voltage by U.
• Now!
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 How about Leakage Power?
• Later in the semester, we will see that the off current is exponentially dependent
on the threshold voltage. VT
nT
I off  e
• In the case of Full Scaling, the leakage current
increases exponentially as VT is decreased!

• Since the 90nm node, static power is one of

the major problems in ICs.

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 3
1 2
Current and Future
Moore’s Law Scaling Models
Trends

Current and Future Trends

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 ITRS
• International Technology Roadmap for Semiconductors

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 Technology Strategy Roadmap
“More
Moore”

“More than
Moore”

“Beyond
Moore”
Quantum
Computing

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 When will Moore’s Law End?

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 Current Strategies

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 Further Reading
• J. Rabaey, “Digital Integrated Circuits” 2003, Chapter 1.3

• E. Alon, Berkeley EE-141, Lecture 2 (Fall 2009)

http://bwrc.eecs.berkeley.edu/classes/icdesign/ee141_f09/

• …a number of years of experience!

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