UNIVERSITY OF BUEA

FACULTY OF ENGINEERING AND TECHNOLOGY

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

Feedback system lab report

Sub-Group 3

Option: Telecommunication Engineering

NAME MATRICULE
KUUM CLIFORT MUGHE FE20A178
KOUTI DIVINE FE20A176
KILANGA FELIX KEVIN FE20A172
KIMBENG FAITH ANTIA FE20A173

DATE: 2022/2023

PRACTICAL WORK
 INTRODUCTION:

Phase Locked Loop (PLL) is a feedback control system that locks the

phase of an output signal to the phase of an input signal. It is commonly

used in communication and control systems. One of the most common

applications of PLL is in generating a stable frequency output signal from

an unstable or noisy input signal. In this lab report, we will discuss the
implementation of PLL using IC 4046 on an electronic board and test it

with an input FM signal.

MATERIALS:

 IC 4046

 Resistors
 Capacitors

 Potentiometer
 FM signal generator

 Oscilloscope
 Power supply

 Breadboard
 Jumper wires
DIAGRAM:
PROCEDURE:

The IC 4046 was used to implement the PLL on the electronic board.

The FM signal was applied to the input of the PLL, and the output of the
PLL was connected to an oscilloscope for observation. The circuit was

powered using a power supply unit, with the voltage set to 5V.
The IC 4046 consists of a phase detector, a loop filter, and a VCO. The

phase detector compares the phase of the input signal with the output

of the VCO. The loop filter removes the high-frequency components of

the phase error signal and produces a DC voltage that is applied to the

VCO. The VCO adjusts its frequency to reduce the phase error,

completing the feedback loop.

RESULTS:

After building the PLL circuit and connecting the FM signal generator to
the input, we were able to observe the output signal on the oscilloscope.

Initially, the output signal was not locked to the input signal, and there
was a phase difference between the input and output signals. We

adjusted the potentiometer to set the VCO frequency close to the input
signal frequency, and we observed that the output signal started to lock

to the input signal. The phase difference between the input and output
signals reduced as the VCO frequency approached the input signal

frequency.
We repeated the experiment by changing the input signal frequency,

and we observed that the output signal followed the input signal
frequency. The PLL circuit was able to track the input signal frequency

and generate a stable output signal frequency.

CONCLUSION:

In this lab report, we discussed the implementation of PLL using IC 4046

on an electronic board and tested it with an input FM signal. We

observed that the PLL circuit was able to lock the phase of the output
signal to the phase of the input signal and generate a stable output
signal frequency. The PLL circuit is widely used in communication and
control systems to generate a stable frequency output signal from an

unstable or noisy input signal

SIMULATION OF PLL FOR THREE PHASE GRID CONNECTION

Abstract: This report discusses the design of a phase lock loop (PLL) for

synchronizing an inverter to a three phase grid using Simulink. PLLs are

important in grid-tied inverters to synchronize the inverter output

voltage with the grid voltage in terms of frequency, phase and

amplitude.

Introduction: Phase lock loops are employed in grid-tied inverters to

synchronize the inverter output with the utility grid. The main function of

a PLL is to detect the phase angle and frequency of the grid voltage and

generate a reference signal that is synchronized to the grid voltage. This

synchronization is important for correcting power factor, injecting

reactive power into the grid and maintaining stability of the inverter

current.
Simulink Model Design: We used Simulink to simulate a PLL for three

phase grid connection. The simulation model consisted of three PLLs,

one for each phase of the grid. The PLLs were designed using a

Proportional Integral (PI) controller.

Simulation Results: The Simulink model was simulated for balanced

three phase grid voltage at nominal frequency and various disturbances

like unbalanced voltage, voltage sag, harmonics, etc. The PLL was able to

effectively synchronize the inverter output current with the grid voltage

under all conditions.

 Phase to phase input voltages are:

 The alpha beta transformation voltages, the dq voltage is zero:

 The alpha beta waveforms are 90 degrees in phase as expected as

shown below:
  The alpha waveform and active components are also in phase with

each other as shown below:

Conclusion: A phase lock loop design for three phase grid connection
was presented which can effectively synchronize an inverter to the grid.

The Simulink model allows testing the performance of different PLL

controllers and parameters under various grid disturbances.
 SOFTWARE TOOL (MATLAB)

STABILITY ANALYSIS FOR SYSTEMS UNDER DIFFERENT PERFORMANCE

CONDITIONS

LAB 1

Aim: To analyze stability of systems represented by their transfer functions

Abstract: This report discusses how Simulink can be used to analyze the
stability of systems represented by their transfer functions using time

response simulations. By observing the time response of the system to

inputs, conclusions about stability can be drawn.

Introduction: Transfer functions provide a mathematical representation

of dynamic systems in the Laplace or 's' domain. They can be converted

into state space models and simulated in Simulink to obtain the time

response. By observing the time response for different inputs, the

stability of the system can be assessed.

• For stable systems, the output response should settle to a finite value.
Unstable systems will have output responses that grow unbounded.
• The response to disturbances can also provide clues about stability.

Stable systems will reject disturbances, while unstable systems will

exhibit growth in response.

• The magnitude of system poles also determines stability. Poles with

positive real parts cause output responses to grow without bound.

Conclusion: Simulating the time response of systems represented by

transfer functions in Simulink is an effective way to analyze stability,

especially for complex higher order systems. Both the time domain

plots and observations about input-output behavior provide important

clues about stability. Combining time response analysis with frequency

domain techniques gives a comprehensive picture of system behavior.

S +1
G = ( S+2)( S+3)( S+ 4)

S (S +7)
H = S (S−5)( S−7)

1
W = ( S−4)(S+ 3)( S+1)
 S+ 6
G1 = ( S−2)(S−1)(S−3)

S( S−3)
G2= ( S+2)( S+3)( S+ 4)
Conclusion: Simulating the time response of systems represented by

transfer functions in Simulink is an effective way to analyze stability,

especially for complex higher order systems. Both the time domain

plots and observations about input-output behavior provide important

clues about stability. Combining time response analysis with frequency

domain techniques gives a comprehensive picture of system behavior.

LAB 2

Aim: To Sketch the root locus system analytically and compare the results with
MATLAB PLOT.

Introduction: Root locus is a graphical method used to study the

change in the system poles with changing gain. It provides insight into
the system stability, transient response and sensitivity to parameter

variations. The root locus can be sketched manually by applying root

locus rules or plotted using MATLAB. Comparing the results helps
validate the analytical method.

G= ; H(S) = 1

Analytical Procedure:
• Determine the characteristic equation of the open loop transfer

function.
• Find the system poles and zeroes from the transfer function.
• Determine the break points by solving for the values of gain where

poles and zeros coincide.

• Plot the break points and label them on the s-plane.

• Draw the loci of the poles from zero gain to infinity using root locus
rules.

• Check for stability at various gain values from the root loci.
• Note any improvements in transient response at critical gain values.

For the transfer function with gain as 1;

1
G= S (S +1)(S +2)( S+ 4) , the poles location are;

Modifying the gain to 2;

2
G1= S (S +1)(S +2)( S+ 4)
 Further modifying the gain to 3;
3
G1= S (S +1)(S +2)( S+ 4)

DICUSSION AND CONCLUSION:

In a unity feedback transfer function, the location of the poles change as

the gain (K) is varied. As K increases:

1. The system poles move along the root loci trajectories. The root loci are

the curved paths that the poles follow as K is varied.

2. When a pole meets a zero at a certain gain value, it forms a break point.

The pole then 'breaks' into the root loci and starts moving along that
trajectory.

3. As K increases further, the poles continue moving along the root loci
away from the real axis.

4. When a pole crosses the imaginary axis, the system becomes unstable.
This indicates the maximum gain margin of the system.

5. Eventually, as K becomes very large, the poles move far into the left half
plane for stable systems, or into the right half plane for unstable systems.
 LAB 3
With damping ratio of 0.2,

With damping ratio of 0.3,

With damping ratio of 0.5;

With damping ratio of 0.7,

 No. Damping 𝒘𝒏 K Maximum Rise Settling
ratio overshoot time time
1 0.2 1 16.7107 0 2.5s 25.1s
2 0.3 1 9.2195 62.5 1. 4 33.4s
3 0.5 1 6.0402 4.92 3.67 1.28
4 0.7 1 6.2701 5.28 1.26 3.66

DISCUSSION AND CONCLUSION

The damping ratio of a transfer function affects the gain, settling

time, rise time, and maximum overshoot of the system in the following

ways:

1. Gain: The damping ratio affects the gain of the system by reducing
the peak magnitude of the frequency response. A higher damping ratio

reduces the gain at resonance, which is the frequency at which the

system oscillates the most. This means that a higher damping ratio

reduces the magnitude of the output of the system when excited at

resonance.

2. Settling Time: The damping ratio affects the settling time of the system
by determining how quickly the system will reach its steady-state value.

A higher damping ratio reduces the settling time of the system by

causing the oscillations to decay more quickly. This means that a higher

damping ratio will result in a faster settling time.

3. Rise Time: The damping ratio affects the rise time of the system by

determining how quickly the system responds to a step input. A higher

damping ratio increases the rise time of the system by causing the

system to be more sluggish in its response. This means that a higher

damping ratio will result in a slower rise time.

4. Maximum Overshoot: The damping ratio affects the maximum overshoot

of the system by determining how much the system will overshoot its

steady-state value before settling. A higher damping ratio reduces the

maximum overshoot of the system by damping out the oscillations more

quickly. This means that a higher damping ratio will result in a smaller
maximum overshoot.