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03.sequential Logic

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29 views26 pages

03.sequential Logic

Uploaded by

Daniel Borregaard
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Embedded Systems Design, Spring 2023

Lecture 3

Sequential Logic: Latches and flip-flops

1 2023 AD
Review from last time

§ ?

2 2023 AD
Bistability

3 2023 AD
Flip flops (latches)

§ 1918 – Eccles - Jordan triggered circuit

§ Latches can change their state at any time


§ Flip-flops can change their state only when a clocking signal is
changing

4 2023 AD
Clock types

§ Clock types

5 2023 AD
S-R latch

§ S-R latch:

6 2023 AD
Typical operation

§ Metastable region: when the output is unpredictable

7 2023 AD
§ Propagation delay: time need for an input signal change to generate an output
signal change
§ Recovery time: giving the minimum separation between S and R as to be not
simultaneous

8 2023 AD
S-R latches

§ S’ and R’ are active low, therefore opposite operation

9 2023 AD
S-R latch with enable

§ Why? To control when the inputs are active

10 2023 AD
Typical operation

11 2023 AD
D-latches

12 2023 AD
Timing parameters

13 2023 AD
Edge triggered D Flip Flop

§ Clk: dynamic input indicator – edge triggered behavior

14 2023 AD
15 2023 AD
16 2023 AD
Shift registers

§ They produce a discrete delay for a specific digital signal. The


delay is given by “n” stages.
§ Conveyor belt similarity

17 2023 AD
Shift registers

18 2023 AD
Serial – in, parallel - out

19 2023 AD
20 2023 AD
Parallel - in, serial - out

21 2023 AD
Parallel - in, serial - out

22 2023 AD
Parallel – in, parallel - out

23 2023 AD
24 2023 AD
Example: 74x194, 4 bit shift register

Example:
S1:0
S0:1

25 2023 AD
§ Example

26 2023 AD

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