CC317 Digital System Design

Spring 2022
Lecture 10

http://www.free-powerpoint-templates-design.com
Sequential Statements
 Sequential Statements
• Sequential statements are statements which are analyzed serially one after the other.

• The final output depends on the order of the statements.

✓ unlike concurrent statements where the order is inconsequential.

• Sequential statements are allowed only inside process and subprograms (function and
procedure)

• Only sequential statements can use variables.

• The Process statement is the primary concurrent VHDL statement used to describe
sequential behaviour.
 Process statement
• The process statement is a concurrent statement , which delineates a part of an
architecture where sequential statements are executed.
• Syntax
[label:] process [(sensitivity list )]
[declarations]
begin
sequential statements
end process;
 Process statement
• Process is a concurrent statement in which sequential statements are allowed.
• An architecture can contain multiple processes. Each process is executed concurrently
• The order of execution of statements is the order in which the statements appear in the
process
• The simulator runs a process when any one of the signals in the sensitivity list changes.
For a wait statement, the simulator executes the process after the wait is over.
✓ process(clk , reset) ...
✓ is executed when either ‘clk’ or ‘reset’ changes
• Each Process is activated at least once at the beginning of the process, independent of
the sensitivity list.
• All signal assignments occur at the END PROCESS statement in terms of simulation.
 Process Statement
The use of wait statements

Proc1: process (a,b,c)

begin Equivalent
x <= a and b and c;
end process;

Proc2: process
begin
x <= a and b and c;
wait on a, b, c;
end process;
 Sequential Statements

Four types of sequential statements

used in behavioral descriptions

if-the-else case-when for-loop while-loop

 The if statement
• Syntax
if condition1 then
statements Priority

[elsif condition2 then

statements]
[else
statements]
end if;
• An if statement selects one or none of a sequence of events to execute . The choice
depends on one or more conditions.
 The if statement contd.
if (sel = “00”) then
if sel = ‘1’ then o <= a;
c <= a; elsif sel = “01” then
else o <= b;
c <= b; elsif (sel=“10”) then
end if; o <= c;
else
o <= d;
end if;

• If statements can be nested.

• If statement generates a priority structure
• If corresponds to when else concurrent statement.
 D flip flop using VHDL
10

ENTITY D_flipflop IS ENTITY D_flipflop IS

PORT(D, Clock : IN STD_LOGIC; PORT(D, Clock : IN STD_LOGIC;
Q : OUT STD_LOGIC); Q : OUT STD_LOGIC);
END D_flipflop; END D_flipflop;
ARCHITECTURE Behavior OF D_flipflop IS ARCHITECTURE Behavior OF D_flipflop IS
BEGIN BEGIN
PROCESS(Clock) PROCESS(Clock)

BEGIN BEGIN

IF rising_edge(Clock) THEN -- +ve edge clock IF falling_edge(Clock) THEN -- -ve edge clock
Q <= D;
Q <= D;
END IF;
END IF;
END PROCESS;
END PROCESS;
END Behavior;
END Behavior;
 The case statement - syntax
case expression is • The case statement selects, for execution one
when choice 1 =>
of a number of alternative sequences of
statements
when choice 3 to 5 => statements .
statements • Corresponds to with select in concurrent
when choice 8 downto 6 =>
statements .
statements
when choice 9 | 13 | 17 => • Case statement does not result in prioritized
statements logic structure unlike the if statement.
when others =>
statements
end case;
 The case statement contd.
process(sel, a, b, c, d)
process (count) begin
begin case sel is
case count is when “00” =>
when 0 => dout <= a;
dout <= “00”; when “01” =>
when 1 to 15 => dout <= b;
dout <= “01”; when “10” =>
when 255 downto 16 => dout <= c;
dout <= “10”; when “11” =>
when others => dout <= d;
dout <= “11”; when others =>
end case; null;
end process; end case;
end process;
 Multiplexer Example
-- Sequential Assignment -- Concurrent Assignment

process ( control )
begin with control select
control
case control is Out_1 <= in1 when “00”
when “00” => out_1 <= in1; in2 when “01”
when “01” => out_1 <= in2; in1 in3 when “10”
in2 Out_1 in4 when “11”;
when “10” => out_1 <= in3; in3
when “11” => out_1 <= in4; in4
end behavior ;
end case;
end process;
 for-loop
[label:] FOR identifier IN range LOOP process (reset)
(sequential statements) begin
END LOOP [label]; if reset = '1' then
for i in 4 downto 0 loop
if i /= 2 then
Note
x<=x*i;
For the for loop the loop index is
incremented end if;
end loop;
end if;
end process;
FSM in VHDL
 Moore FSM Coding
17

ENTITY FSM_Parity IS
PORT ( i1, CLK: IN std_logic;
o1: OUT std_logic);
END FSM_Parity; 0 1 1

ARCHITECTURE FSM_Parity_arch OF FSM_Parity

S1/0 S2/1
IS
TYPE FSMStates IS (s1, s2);
SIGNAL PrState, NextState : FSMStates;
0
BEGIN

PROCESS (CLK) BEGIN

IF rising_edge(clk) THEN
PrState <= NextState;
END IF;
END PROCESS;
 Moore FSM Coding
18
PROCESS (PrState, i1) BEGIN
CASE PrState IS
WHEN s1 =>
if i1=‘1’ then
NextState <= s2; 0
else 1 1
NextState <= s1;
end if;
S1/0 S2/1
o1 <= ‘0’;
WHEN s2 =>
if i1=‘0’ then
NextState <= s1; 0
else
NextState <= s2;
end if;
o1 <= ‘1’;
WHEN OTHERS =>
o1 <= ‘1’;
NextState <= s1;
END CASE;
END PROCESS;
 Hardware generated by VHDL for state diagram
19

0 1 1

S1/0 S2/1

18
 Mealy FSM Coding
20

entity seqdetb is
1/1
port (clk: in STD_LOGIC;
0/0
din: in STD_LOGIC; 1/0
dout: out STD_LOGIC);
end seqdetb; 0/0 s0 s1 s2 s3
1/0 1/0 0/0

architecture seqdetb of seqdetb is 0/0

type state_type is (s0, s1, s2, s3);
signal present_state, next_state: state_type;
begin

sreg: process(clk)
begin
if rising_edge(clk)then
present_state <= next_state;
end if;
end process;
 Mealy FSM Coding
21 C1: process(present_state, din)
begin
case present_state is
1/1
when s0 =>
0/0
if din = '1' then 1/0

next_state <= s1; dout <= '0';

0/0 s0 s1 s2 s3
1/0 1/0 0/0
else
next_state <= s0; dout <= '0'; 0/0

end if;
when s1 =>
if din = '1' then
next_state <= s2; dout <= '0';
else
next_state <= s0; dout <= '0';
end if;
 Mealy FSM Coding
21

when s2 =>
if din = '0' then
next_state <= s3;
dout <= '0';
1/1
else
0/0 next_state <= s2;
1/0
dout <= '0';
end if;
0/0 s0 s1
1/0
s2
0/0
s3 when s3 =>
1/0
if din = '1' then
0/0
next_state <= s1;
dout <= '1' ;
else
next_state <= s0;
dout <= '0';
end if;
when others =>
null;
end case;
end process;
 FSM in VHDL
21

Next-State Logic

process ( Present_state, <in1>, <in2>, <in3> … )

Begin
case ( Present_State ) is
when <state1> =>
if ( <condition (<in1>, <in2>...)> ) then
Next_State <= <state2>;
elsif ( <condition (<in1>, <in2>...)> ) then
Next_State <= <state3>;
...
end process;
 FSM in VHDL
21

Present-State

Process (clock)
Begin
if rising_edge (clock) then
Present_State <= Next_State;
end if;
End process;
THANK YOU