CC317 Digital System Design

Spring 2022
Lecture 11

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 PLD
• Problems by Using Basic Gates

• Many components on PCB:

• As the number of components increases, the complexity of interconnection nodes
exponentially increases.

• Growth in interconnection would lead to increased interference, PCB size, cost of

PCB design and time of manufacture.
 PLD
• PLD device has the function of allowing the user to implement complex digital design

in a single device.

• PLD is an integrated circuit with internal logic gates and/or connections which can be

modified by the programming process in some way.

• It can be electrically erased and reprogrammed with a new design, making them very

well suitable for both academic and prototyping.

 Types of PLD

• SPLDs (Simple Programmable Logic Devices)

• ROM (Read-Only Memory)

• PLA (Programmable Logic Array)

• PAL (Programmable Array Logic)

• GAL (Generic Array Logic)

• CPLD (Complex Programmable Logic Device)

• FPGA (Field-Programmable Gate Array)

 SPLD
• The first three types are quite similar :
• All of them have an input connection matrix, which links the device inputs to an array of AND-gates.

• All of them have an output connection matrix, which connect the AND-gates outputs to the OR-gates inputs
which drive the device outputs.

Multi-input OR There is a connection

gate There is no connection

conventional symbol array logic symbol

Most PLD technologies have gates with very high fan-in

OR/AND - PLD Notation
 PLDs
All use AND-OR structure- differ in which is programmable
Fixed
Programmable Programmable
Inputs AND array Outputs
connections OR array
(decoder)

Programmable read-only memory (PROM)

Programmable Programmable Fixed

Inputs Outputs
connections AND array OR array

Programmable array logic (PAL) device

Programmable Programmable Programmable Programmable

Inputs Outputs
connections AND array connections OR array

Programmable logic array (PLA)

 Memory
• Memory: A collection of cells able to store binary information (1s or 0s).
• Computer memories are organized into words. Generally, a word is
commonly defined as a group of bits which computer handles as one entity. 12
3
From this definition, a word equals to the size of the internal 4
5
register(usually 16, 32, or 64 bits). 6
7
8
• a word is accessed by providing its row number (address number).
• A memory is identified by the number of words it can store times the size
of word .
• E.g. a 8 x 8 memory can store 8 words of bits each word of 8 bits
 Content of a memory
 Each word in memory has an identification
number called an address which starts from 0 up
to 2k-1, where k is the number of address lines.

 Ex: 1024 x 16 ROM has 1024 address, each

address consists of 10 bits. ROM consists of
1024 words, each word has 16 bits( 2 bytes).

 The number of words in a memory with one of the

letters:

 K=210, M=220, or G=230.

 64K = 216 2M = 221 4G = 232

 Memory
 There are two memories types used in digital systems:
 random-access memory (RAM) can do both Write and Read operations.

 read-only memory (ROM) can only do the Read operation.

• ROM DOES NOT have a write

• n data lines (input/output) operation
• k address lines ✓ ROM DOES NOT have data
• 2k words (data unit) inputs
• Read/Write Control • Word: group of bits stored in one
• Memory size = 2k x n location
 The Read Operation
Floyd

Address register Data register

0 1 1 1 1 0 0 0 0 0 1

Address decoder Byte organized memory array

0 1 0 1 0 1 1 1 1
1 1 0 0 1 0 1 0 0 1
2 1 0 0 0 0 0 0 1 3

Address bus 3 1 1 0 0 0 0 0 1
4 0 0 0 0 0 1 1 0 Data bus
5 1 0 0 0 1 1 0 1
6 1 1 1 1 1 1 1 1
7 0 0 0 0 1 1 1 1
2

Read
1- Address number 011 is placed on the address bus(lines) so address 3 is chosen.
2- Read command is applied.
3- The word located at address 3 is placed on the data bus and shifted into data register.
Note that The contents od word that located at address 3 is not erased by the read operation.
 ROM Internal Logic
• ROM = Decoder + OR gates
• Each decoder output represents one memory address 0
I0 1
• ROM has 32 Words of 8 bits each I1
2
3
.
• ROM has 5 input lines (address) I2 5-to-32 .
decoder .
I3 28
• Each OR gate has a 32 input I4
29
30
31
• A 2k x n ROM will internally consist of an k x 2k decoder and
n OR gates

• A contact can be made using fuse/anti-fuse

A7 A6 A5 A4 A3 A2 A1 A0
• It is easy to implement a combinational circuit.
• Store the truth table by programming the ROM Internal Logic of a 32x8 ROM
• It is only required to provide the truth table
 Programming a ROM
Inputs Outputs
I I I I I A A A A A A A A 0 x x x x x
I0 1 x x x x
4 3 2 1 0 7 6 5 4 3 2 1 0 I1
2 x
x
x
x x
x
x
x
3
0 0 0 0 0 1 0 1 1 0 1 1 0 I2 5-to-32 .
decoder .
0 0 0 0 1 0 0 0 1 1 1 0 1 I3 .
28 x x
x x x x
0 0 0 1 0 1 1 0 0 0 1 0 1
I4
x x x
29
30
31 x x x x
0 0 0 1 1 1 0 1 1 0 0 1 0
. .
. .
A7 A6 A5 A4 A3 A2 A1 A0
. .
1 1 1 0 0 0 0 0 0 1 0 0 1 • Every ONE in truth table identifies a closed circuit
1 1 1 0 1 1 1 1 0 0 0 1 0 • Every ZERO in truth table identifies an OPEN circuit
1 1 1 1 0 0 1 0 0 1 0 1 0 • Example: At address 00011 → The word 10110010 is
1 1 1 1 1 0 0 1 1 0 0 1 1 stored
 Read-Only Memory (ROM)
 8 x 4 ROM 3x8
Decoder
Address Data 0
0 0 0 0000 1
0 0 1 1101 A2 2
I2 3
0 1 0 0011 A1 I1
1000 4
0 1 1 A0 I0 5
1 0 0 1111
6
1 0 1 1001 1 E 7
1 1 0 0111
1 1 1 0000
• Every ONE in truth table specifies a closed circuit D3 D2 D1 D0
• Every ZERO in truth table specifies an OPEN circuit
• Example: At address 00011 → The word 10110010 is stored
 Example 1

 Example: Design a combinational circuit using ROM. The circuit accepts a 3-bit
number and generates an output binary number equal to the square of the number.
 Solution: Derive truth table:
Inputs Outputs
A2 A1 A0 B5 B4 B3 B2 B1 B0 SQ
0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 1 1
0 1 0 0 0 0 1 0 0 4
0 1 1 0 0 1 0 0 1 9
1 0 0 0 1 0 0 0 0 16
1 0 1 0 1 1 0 0 1 25
1 1 0 1 0 0 1 0 0 36
1 1 1 1 1 0 0 0 1 49
 Example 1 (cont.)
Inputs Outputs
A2 A1 A0 B5 B4 B3 B2 B1 B0 SQ
0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 1 1
0 1 0 0 0 0 1 0 0 4
0 1 1 0 0 1 0 0 1 9
1 0 0 0 1 0 0 0 0 16
1 0 1 0 1 1 0 0 1 25
1 1 0 1 0 0 1 0 0 36
1 1 1 1 1 0 0 0 1 49 B0

ROM truth table – specifies the required connections

0 B1
A0 8 X 4 ROM B2

 B1 is ALWAYS 0 ➔ no need to generate it using the ROM A1

B3
B4
 B0 equals to A0 ➔ no need to generate it using the ROM
A2 B5
 Thus: The minimum size of required ROM is 23 x 4 or 8 x 4
 Example 2

 Problem: Tabulate the truth table for an 8 X 4 ROM that implements the following four Boolean
functions:

 A(X,Y,Z) = ∑(3,6,7); B(X,Y,Z) = ∑(0,1,4,5,6)

 C(X,Y,Z) = ∑(2,3,4); D(X,Y,Z) = ∑(2,3,4,7)

 Solution: Inputs Outputs

X Y Z A B C D
A
0 0 0 0 1 0 0 X
0 0 1 0 1 0 0 8 X 4 ROM B
Y
0 1 0 0 0 1 1 C
0 1 1 1 0 1 1 Z
D
1 0 0 0 1 1 1
1 0 1 0 1 0 0
1 1 0 1 1 0 0
1 1 1 1 0 0 1
 Example 3 (Size of a ROM)
• Problem: Specify the size of a ROM (number of words and number of bits per word) for the
following combinational circuit: An 8-bit adder/subtractor with Cin and Cout.

• Solution:
• Inputs to the ROM (address lines) = 8 (first number) + (8 second number) + 1 (Cin) ➔ 17 lines
• Hence number of words in ROM is = 128 K
• Size of each word = number of possible functions/outputs
• = 8 (addition/subtraction) + 1 (Cout)
• =9
• Hence ROM size = 128K X 9
 Advantages of using PLDs
• Advantages of reducing the no. of ICs using PLD:

• less board space

• fewer PCBs
• lower power requirements (i.e., smaller power supplies)
• faster and less costly assembly processes
• higher reliability (fewer ICs and circuit connections => easier troubleshooting)
• availability of design software
THANK YOU