I N V E N TI V E CONFIDENTIAL

Introduction to Xcelium®
Simulator (XLM)
Gate Level Simulation
 Agenda

• Gate Level Simulation

– SDF Annotation
– SDF Annotation Flow
– Gate-Level Sim. Debug
– Summary

2 May 16, 2017 Cadence Confidential

 Gate Level Simulation

SDF Annotation
SDF Annotation Flow
Gate-Level Sim. Debug
Summary

3 May 16, 2017 Cadence Confidential

 Describing Timing Annotation

• A silicon vendor simulation library contains estimated intrinsic

timing.
• For accurate timing simulation you need additional data:
– Drive strength
– Interconnect parasitics
– Total load
– Environmental factors
• process
• temperature
• voltage

• You need to simulate fast clock with slow data, slow clock with fast
data.
• Most event simulators cannot directly do this.
4 May 16, 2017 Cadence Confidential
 Timing Data Flow
Design Floorplan Delay Delay
Capture Refinement Calculation Calculation

Functional Clock Insertion, In Place

Simulation Reoptimization Optimization SPF Data

Global Routing, ECO Routing SDF

Floorplanning
Reoptimization Annotation
Design Rule
Scan Checking Gate-level
Final Routing
Insertion Simulation
&
Back-End Flow
Parasitic Timing
Synthesis Analysis
Extraction

Placement SPF Data

5 May 16, 2017 Cadence Confidential
 Delay Calculators

• Two major categories of delay calculators exist:

– Delay calculators embedded in the tools
• Synthesis tools
• Static timing analysis tools
– Custom delay calculators
• User-defined
• Vendor-supplied

• Delay calculators can generate SDF data, or directly annotate

timing data using the Application Programming Interface (API).

6 May 16, 2017 Cadence Confidential

 Standard Delay Format
What is SDF?

• A Standard Delay Format developed to facilitate timing information

between the ASIC vendor and ASIC designers:
– Successfully used in Verilog-based ASIC designs.
– Supports all Verilog timing modelling methodologies through the
– representation of either timing constraints (forward-annotation) and
delays (backward-annotation).

• The SDF provides a tool-independent, uniform way to specify timing

data.

7 May 16, 2017 Cadence Confidential

 Standard Delay Format
What is SDF?
(DELAYFILE
(SDFVERSION "4.0")
(DESIGN "system")
(DATE "Sun Feb 22 14:10:03 EST 2009")
(VENDOR "Cadence")
(PROGRAM "delay_calc")
(VERSION "08.20-p001")
(DIVIDER /) /*hierarchical divider */
(VOLTAGE 4.5:5.0:5.5)
(PROCESS "worst")
(TIMESCALE 1ns) /* delay time units */
(CELL (CELLTYPE "system") (INSTANCE block_1) /* top-level blocks */
(DELAY (ABSOLUTE
(INTERCONNECT D1/z P3/i (.155::.155) (.130::.130)))))
(CELL (CELLTYPE "INV") (INSTANCE *) /* all instances of "INV" */
(DELAY (INCREMENT
(IOPATH i z (.345::.348) (.325::.329)))))
(CELL (CELLTYPE "OR2") (INSTANCE B1/C1) /* this instance of "OR2" */
(DELAY (ABSOLUTE
(IOPATH i1 z (.300::.300) (.325::.325))
(IOPATH i2 z (.300::.300) (.325::.325)))))
)

8 May 16, 2017 Cadence Confidential

 Standard Delay Format
What about its evolutions?

• It is an IEEE standard.
– Originally developed by Cadence Design Systems as SDF 1.0.
– Updated and Maintained by Open Verilog International (OVI) with SDF
2.0, SDF 2.1 and SDF 3.0.
– Standardized as IEEE 1497-2001 DASC Standard Delay Format (SDF)
as SDF 4.0.

• Important
– IEEE 1076.4-1995 is based on SDF 2.1 while
IEEE 1076.4-2000 is based on a draft version
of the SDF 4.0 (IEEE P1497 Draft Standard
Delay Format).

9 May 16, 2017 Cadence Confidential

 Verilog SDF Annotation

• You can annotate the Verilog portions of your design with the
$sdf_annotate built-in system task.
– Task arguments correspond to command file entries.
– Only the SDF file name argument is required:
$sdf_annotate (“sdf_file”
{, module_instance}
{, “config_file”}
{, “log_file”}
{, “mtm_spec”}
{, “scale_factors”}
{, “scale_type”});

– The three parameters used regularly are the SDF filename, the module
instance and the log file.
– The SDF Config file contains commands that can alter SDF information
on its way into the simulation

10 May 16, 2017 Cadence Confidential

 Verilog SDF Annotation

• The xmelab elaborator by default executes any $sdf_annotate

system tasks unambiguously scheduled to execute at simulation
time 0. That means:
– You cannot place the $sdf_annotate system task in an always block
– You cannot precede the $sdf_annotate system task with a timing
control
– You cannot place the $sdf_annotate system task in a case, for,
repeat. Or while statement
– You cannot place the $sdf_annotate system task in an if statement if
the conditional expression is not statically computable
– Otherwise use -sdf_simtime to postpone annotation until you run
xmsim.

11 May 16, 2017 Cadence Confidential

 Verilog SDF Annotation
Static

• SDF-Annotation is then achieved at elaboration time in a 2-stages

process
1. (Optional) Compile the SDF file with the xmsdfc utility
xmsdfc [-options] filename.sdf[.gz]
If you do not this compilation is spawned during elaboration
One requirement is for $sdf_annotate to always use the invocation directory to look
for and store the compiled SDF file.
2. Invoke xmelab
% xmelab –sdf_verbose [options] [Lib.]Cell[:View]

– Important
• Use the –noautosdf xmelab’s option if you does not want to apply/use
sdf_annotate system task

12 May 16, 2017 Cadence Confidential

 Verilog SDF Annotation
Dynamic

• The MTM annotation scheme is emulated

– Similar code can be added
– Elaboration options source

vlog/vhdl

-sdf_simtime
COD
-sdf_orig_dir
Or xmelab
-sdfdir <dir>
– Simulation options SSS

+usemindelays
Or xmsim
+usemaxdelays

13 May 16, 2017 Cadence Confidential

 Verilog SDF Annotation
Dynamic

• The MTM annotation scheme is emulated

– Flow has been optimized
• Reuse of .X file (xmsdfc invocation upfront)
• Only one annotation @elab + @sim
• -sdf_simtime support to allow for elaboration in one directory and sim in
another.
• -sdf_orig_dir support to force the $sdf_annotate and the auto update code
to use the original directory were the SDF file is stored for the precompiled
SDF.
• -sdf_dir support to force the $sdf_annotate and the auto update code to
use a specific directory were the SDF file is stored for the precompiled SDF.

14 May 16, 2017 Cadence Confidential

 Mixed-lang or (V)HDL SDF Annotation

• You can annotate the Verilog portions of your design with the
$sdf_annotate built-in system task or any portions using the SDF
command file. GRAPHIC_EDIT

15 May 16, 2017 Cadence Confidential

 Mixed-lang or (V)HDL SDF Annotation

• SDF-Annotation is (also) achieved at elaboration time in a 3-stages

process
1. Compile the SDF file with the xmsdfc utility
xmsdfc [-options] filename.sdf[.gz]
2. Write an ASCII file describing the sdf-annotation(s) to process

3. Invoke xmelab with the -sdf_cmd_file file

% xmelab –sdf_cmd_file [File] –sdf_verbose [options] [Lib.]Cell[:View]

16 May 16, 2017 Cadence Confidential

 Gate Level Simulation

SDF Annotation
SDF Annotation Flow
Gate-Level Sim. Debug
Summary

17 May 16, 2017 Cadence Confidential

 Preparing the Optional SDF Configuration File

• The SDF configuration file filters SDF timing data prior to

annotation.
• It contains keywords controlling use of the data (default in bold):
– TIMING_KEYWORD = IGNORE;
– INTERCONNECT_MIPD = [MINIMUM | AVERAGE | MAXIMUM];
– SCALE_TYPE =
[ FROM_MINIMUM | FROM_TYPICAL |FROM_MAXIMUM | FROM_MTM ];
– SCALE_FACTORS = 1.0:1.0:1.0;
– MTM = [ MINIMUM | TYPICAL | MAXIMUM | TOOL_CONTROL ];
– MODULE definition_name // Verilog ONLY
{
MTM = [ MINIMUM | TYPICAL | MAXIMUM ];
SCALE_FACTORS = min_factor:typ_factor:max_factor;
MAP_INNER = hierarchical_instance_name;
[ (sdf_timing_path) = IGNORE; ]
[ | (sdf_timing_path) = ADD { (hdl_timing_path); ...; } ]
[ | (sdf_timing_path) = OVERRIDE { (hdl_timing_path); ...; } ]
18 May 16, 2017 }
Cadence Confidential
 Preparing the SDF Command File
Only field which is
not a string

• Create an SDF command file to control the annotation process:

Keyword Specifies
COMPILED_SDF_FILE Compiled SDF file name
SCOPE Module instance path name
CONFIG_FILE Configuration file name
LOG_FILE Log file name
MTM_CONTROL MTM control
SCALE_FACTORS Scale factors
SCALE_TYPE Scale type

– The COMPILED_SDF_FILE keyword is required. You can omit all other

command file keywords. The MTM_CONTROL, SCALE_FACTORS, and
SCALE_TYPE keywords in the command file override those in the
configuration file.

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 Preparing the SDF Command File

• Examples

– You can also repeat the option to specify more than one command file.
For example:
% xmelab top -sdf_cmd_file cpu.sdf_cmd -sdf_cmd_file ebox.sdf_cmd
Important
• You can enter the statements in any order.
• Use commas to separate statements
• Use a semicolon after the last statement of the record.
• When multiple definitions for the same statement exist, the last definition
takes over.
20 May 16, 2017 Cadence Confidential
 Preparing the SDF Command File

• Hierarchical Path Name Syntax

– To traverse your design hierarchy or access to buried objects, follow
the rules:

21 May 16, 2017 Cadence Confidential

 Compiling SDF files with xmsdfc

• Compile the SDF file with xmsdfc

– xmsdfc [-options] filename.sdf
– xmsdfc -worstcase_rounding timing.sdf
• Here are some useful xmsdfc options:
Keyword Specifies
-DECOMPILE Decompile the specified SDF files
-OUTPUT <arg> Redirect the compiled SDF output
-UPDATE Recompile only if necessary
-WORSTCASE_ROUNDING Round min delays down, max delays up

22 May 16, 2017 Cadence Confidential

 Annotating SDF Data

• Provide the SDF command file to the xmelab elaborator:

xmelab design_unit [-intermod_path] -sdf_cmd_file filename
– xmelab top -intermod_path -sdf_cmd_file cpu_sdf.cmd
– xmelab top -sdf_cmd_file cpu_sdf.cmd -sdf_cmd_file
alu_sdf.cmd
• These xmelab elaborator annotation-specific options affect
Verilog and VHDL:
Keyword Specifies
-intermod_path Enable multisource interconnect delays
-no_sdfa_header Suppress display of SDF header information
-sdf_cmd_file <arg> Provide an SDF command file
-sdf_no_warnings Suppress display of SDF annotator warnings
-sdf_precision <arg> Specify maximum precision for SDF data

23
-sdf_verbose
May 16, 2017 Cadence Confidential Display detailed SDF annotator activity
 Annotating SDF Data

• These xmelab elaborator annotation-specific options affect only

Verilog:
Keyword Specifies
-anno_simtime Allow runtime API annotation
-caint Allow INTERCONNECT annotation across
continuous assignments
-noautosdf Disable automatic $sdf_annotate SDF
annotation
-sdf_nocheck_celltype Suppress validation of cell type declaration
-sdf_nopulse Ignore SDF path pulse reject and error data
-sdf_simtime Allow runtime $sdf_annotate SDF
annotation
-sdf_specpp Use specify block PATHPULSE parameters
24
-sdf_worstcase_rounding
May 16, 2017 Cadence Confidential
Round min delays down, max delays up
 Annotating SDF Data

• These xmelab elaborator VITAL-specific options affect only

VHDL:
Keyword Specifies
-no_tchk_xgen Disable VITAL accelerated timing check ’X’
generation
-no_vpd_msg Disable VITAL accelerated path delay glitch
messages
-no_vpd_xgen Disable VITAL accelerated path delay ’X’
generation
-noipd Disable VITAL level 1 cell input path delays
-novitalaccl Disable VITAL level 1 cell acceleration
-vipd{max,min} Select the VITAL input path delay to annotate

25 May 16, 2017 Cadence Confidential

 Gate Level Simulation

SDF Annotation
SDF Annotation Flow
Gate-Level Sim. Debug
Summary

26 May 16, 2017 Cadence Confidential

 Setting up GLS
Setting a Delay Mode @ elab time

• Inertial delay mode

Transport
– pulse durations less than delay are “swallowed”

Error limit
Reject limit
• Transport delay mode
– all pulses transported to output Filtered/Inertial X

Simulator default delay modes differ. Simulators may provide command-line options
or simulator-specific compiler directives to manipulate the delay mode.

27 May 16, 2017 Cadence Confidential

 Setting up GLS
Setting a Delay Mode @ elab time

• Xcelium default is to simulate interconnect delays and module path

delays as transport delays
– enable transport delay behaviour with pulse control with some xmelab’s
options or through SDF constructs

Keyword (xmelab) Specifies

-pulse_e <>/-pulse_r <> Set global pulse limits for both module path
delays and interconnect delays.
-pulse_int_e <>/-pulse_int_r <> Set limits for interconnect delays only .

– enable the ability to specify unique delays for each source-load path

Keyword (xmelab) Specifies

-intermod_path Enable the ability to specify unique delays for
source-load paths
– but behaviour is like inertial

28 May 16, 2017 Cadence Confidential

 Setting up GLS
On-Event versus On-Detect Pulse Filtering

• Verilog-1995 used the onevent • For Verilog-2001 you can select the
pulse filtering style. ondetect pulse filtering style.
• pulsestyle_onevent • pulsestyle_ondetect
specify Not available in Verilog-1995 specify
pulsestyle_onevent outp; pulsestyle_ondetect outp;
(inp => outp) = 5 ; (inp => outp) = 5 ;
specparam specparam
PATHPULSE$inp$outp = (2,4); PATHPULSE$inp$outp = (2,4);
endspecify endspecify

inp inp

outp outp

0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8

29 May 16, 2017 Cadence Confidential

 Setting up GLS
On-Event versus On-Detect Pulse Filtering

• Xcelium default behaviour is to use On-Event .

Keyword Specifies
-epulse_onevent Do not filter canceled events (negative pulses) to
the e state
-epulse_ondetect Use On-Detect filtering of error pulses. This
option extends the e state back to the edge of the
event that caused the pulse to occur
-epulse_neg Filter canceled events (negative pulses) to the e
state. This option makes canceled events visible.
-epulse_noneg Do not filter canceled events (negative pulses) to
the e state.

30 May 16, 2017 Cadence Confidential

 Setting up GLS

• When simulating with no timing delays

– GLS can exhibit some zero-delay oscillations that need to be detected
and fixed
Keyword Specifies
-GAteloopwarn Enable potential zero-delay gate loop warning
• Then, use the Tcl drivers -active command to identify the active signals
and trace these signals to the zero-delay loop.
• The Tcl where command is also helpful (but requires –linedebug)
– GLS are prone to race conditions
Keyword Specifies
-SEQ_udp_delay Apply the specified delay value to the input/output
delay_specification paths of all sequential UDPs in the design.

– More generally, just check to see that you don't exceed 1000 warnings!!
• Use -warnmax 0 to print all warnings
31 May 16, 2017 Cadence Confidential
 Setting up SDF Annotation

• Use –sdf_verbose with xrun to see each annotation as it is

performed in the log file
• Verbose log file can grow very large but they are best tool to see the
details
• Creating a testcase SDF file
– When debugging a specific problem, there is no need to use entire SDF
file.
– Create your own SDF file to annotate just the pins in question

32 May 16, 2017 Cadence Confidential

 Setting up SDF Annotation

• These are some general rules that you should be aware of:
– Each SDF version reflects significant changes
• Cadence defined SDF version 1.0
• OVI defined SDF versions 2.0, 2.1, 3.0
• IEEE std. 1497-2001 defines SDF version 4.0
• IEEE std. 1076.4-2000 (VITAL) supports SDF version 4.0
– The annotator must apply SDF data in file order
• Subsequent LABEL, TIMINGCHECK, TIMINGENV replace previous
• Subsequent ABSOLUTE delays replace previous delays
• Subsequent INCREMENT delays add to previous delays
– The annotator must apply cell path data only to existing constructs
• Edge-qualified SDF cell paths do not map to unqualified cell paths
• Conditional SDF cell paths do not map to unconditional cell paths

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 Setting up SDF Annotation

• These are some tool-related issues that you should be aware of:
– The SDF escapes only individual identifier characters
– The SDF allows a port to be an internal node
– Annotators can convert INTERCONNECT delay to PORT delay
• Annotators can ignore INTERCONNECT delay
– Annotators must attempt to apply DEVICE delays to cell timing paths
• If unsuccessful, must apply to all primitives driving output port
– Simulation tools do not use TIMINGENV data
– Not all annotators use negative values
• Shall substitute 0 in ABSOLUTE clauses
• May substitute 0 in INCREMENT clauses
• Simulators typically do not use negative delay

34 May 16, 2017 Cadence Confidential

 Setting up SDF Annotation

• The IEEE std. 1076.4-2000 (VITAL) supports a subset of SDF 4.0:

– No support for LABEL, TIMINGENV, PATHPULSE,
– PATHPULSEPERCENT, NETDELAY
– No support for escape characters
– Not sensitive to character case

35 May 16, 2017 Cadence Confidential

 Modeling Sequential Statements

• These are some simulator-specific issues that you should be aware

of:
– Simulator handling of mixed-language INTERCONNECT path pulse
controls
• Supports pulse controls for interconnect paths that terminate in a Verilog
partition
– Simulator handling of missing INTERCONNECT
• For Verilog — Converts to PORT delays
• For VHDL — Ignores missing INTERCONNECT

36 May 16, 2017 Cadence Confidential

 Modeling Sequential Statements
Example of Specify Block and UDPs

• The following example is of a positive edge-triggered D flip-flop with

an asynchronous reset, complete with timing checks and path
delays. The model instantiates a UDP which has an input for the
value of a notifier reg. primitive UDP_DFFR (q, d, c, r, n);
output q; reg q;
Added to theinput
functionality
d, c, r, n;
`timescale 1 ns / 1 ns table
module dffr_m (q, d, clk, rst); // d c r n : q : qnext
input d, clk, rst; ? ? 0 ? : ? : 0; // reset
output q; ? ? n ? : 0 : -; // rst negedge
reg nt; ? ? p ? : ? : -; // rst posedge
UDP_DFFR u1 (q, d, clk, rst, nt); 0 r ? ? : ? : 0; // clk rise
specify 1 r 1 ? : ? : 1; // clk rise
specparam tS = 2; 0 p ? ? : 0 : -; // clk posedge
(clk => q) = (2:3:4); 1 p 1 ? : 1 : -; // clk posedge
$setup (d, posedge clk, tS, nt); ? n ? ? : ? : -; // clk negedge
endspecify * ? ? ? : ? : -; // data edge
endmodule ? ? ? * : ? : x; // notifier
endtable
endprimitive
Notifier will trigger @ each violation
Will create an X
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 Modeling Sequential Statements
Modeling Timing-Checks

• You use timing checks to verify that signals obey timing constraints
– Stability window checks
• $setup Setup data sufficiently before active clock edge
• $hold Hold data sufficiently after active clock edge
• $setuphold Combined setup and hold check permits a negative time limit
• $recovery Remove asynchronous control sufficiently before active clock edge
• $removal Remove asynchronous control sufficiently after active clock edge
• $recrem Combined recovery and removal check permits a negative time limit
– Event interval checks
• $nochange Second signal does not change while first signal in specified state
• $width Pulse width is sufficiently long
• $period Period is sufficiently long
• $skew Time between two signals is sufficiently short
• $timeskew Time between two signals is sufficiently short (variation)
• $fullskew Time between two signals is sufficiently short (variation)

38 May 16, 2017 Cadence Confidential

 Modeling Sequential Statements
Understanding Timing-Checks’ reports

• Timing checks violations are reported as

Time of the second event (the violation)
Time of the first event
Value of the timing check limit
Warning! Timing violation
$setuphold <setup> (posedge clock: 100 NS, data: 60 NS, 50 : 50 NS, 50 : 50 NS);
File: ./ff.v, line = 13
Scope: board.counter.a
Time: 100 NS + 1
File and Line number

Instance name of the module in which the violation

occurred

Time of the violation

39 May 16, 2017 Cadence Confidential

 Modeling Sequential Statements
Negative Timing Checks

• Observation point in timing simulation is different

than the silicon characterization point.
– Negative hold time is generally seen where a delay is
already added in the data path inside the flop .
– Negative setup time is generally seen where a delay is
already added in the clock path inside the flop .

40 May 16, 2017 Cadence Confidential

 Modeling Sequential Statements
Setup and Hold Checks

• $setuphold (reference_event , data_event , timing_check_limit ,

timing_check_limit [ , [ notify_reg [ , [ stamptime_condition ] [ , [
checktime_condition ] [ , [ delayed_reference ] [ , delayed_data ] ] ] ] ] ) ;
– Combines setup and hold checks
– Permits a negative setup limit or a negative hold limit
– Accepts separate conditionalization arguments
– A setup violation (if both limits positive) is:
(clock-limit) < data <= clock
– A hold violation (if both limits positive) is:
clock <= data < (clock + limit)

clk clk

setuphold setuphold
data data

$setuphold(posedge clk, data, 6, 2); $setuphold(posedge clk, data, 9, -1,,,, data_dly);

41 May 16, 2017 Cadence Confidential

 Modeling Sequential Statements
Recovery and Removal Checks

• $recrem (reference_event , data_event , timing_check_limit ,

timing_check_limit [ , [ notify_reg [ , [ stamptime_condition ] [ , [
checktime_condition ] [ , [ delayed_reference ] [ , delayed_data ] ] ] ] ] ) ;
– Combines recovery and removal checks
– Permits a negative recovery limit or a negative removal limit
– Accepts separate conditionalization arguments
– A recovery violation (if both limits positive) is:
(clock - limit) < control <= clock
– A removal violation (if both limits positive) is:
clock <= control < (clock + limit)

rst_ rst_

recrem recrem
clk clk

$recrem(posedge rst_,posedge clk,3,4); $recrem(posedge rst_,posedge clk,8,-1,,,,rst_dly_);

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 Modeling Sequential Statements
Negative Timing-Checks

• From a modelling standpoint,

– Using negative limits in these timing
checks can affect the evaluation of timing checks.
• For each timing check with a negative limit, the reference and/or data event
may be delayed, thereby delaying the execution of the timing check.
– If there are Negative Setup numbers, then the window is shifted to the right of the
clock edges
– If there are Negative Hold numbers, then the window is shifted to the left of the
clock edges
• When either the reference or data signal of a check is delayed, the limits of
the check are appropriately modified to verify the same constraint using the
delayed signals.

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 Modeling Sequential Statements
Negative Timing-Checks

• From a verification standpoint,

– The simulators will create these delayed clock or data signals in such a
way as to fall within the violation region that the system task declares.
– Problem can arise if multiple $setuphold or $recrem system task with
respect to the same clock and data signals
• Creating a single delayed clock that satisfies (or falls within) all of the
violation regions might prove impossible because the violation regions do
not overlap  non-convergence error.
• Default algorithm is to set one of the negative timing check values to zero
and repeats its attempt to find a time within the overlapping violation
regions.
• This process continues until the simulator finds such an overlap, or until all
negative values have been set to 0.

44 May 16, 2017 Cadence Confidential

 Setting up SDF Annotation
Negative Timing-Checks

• In case one is facing non-convergence issues

Keyword Specifies
-NTC_Verbose Display the limits that have been changed by the
negative timing check (NTC) algorithm in order to
make a circuit converge
-NTC_Warn Print convergence warnings for negative timing
checks for both Verilog and VITAL if delays
cannot be calculated given the current limit
values.
• Then:
-EXTEND_TCHECK_Data_limit Extend the violation regions established by a pair
percent_relaxation of setuphold or recrem timing checks with
- negative values in which the timing checks
EXTEND_TCHECK_Reference_l contain two different constraints for posedge and
imit percent_relaxation negedge of data with respect to the same
reference signal and in which the violation
regions do not overlap.
45 May 16, 2017 Cadence Confidential
 Setting up SDF Annotation
Negative Timing-Checks

• Note that the sum of the two limits must be 0 or greater

– If the sum of the two arguments is less than 0, the negative limit is set
to 0 by default and one is getting a warning
– Such a warning can be filtered and a tolerance window be specified

Keyword Specifies
-NTC_Tolerance 1. Specify the tolerance value for a negative
tolerance_value timing check timing window.
2. Suppress the warning messages that are
generated for $setuphold and $recrem timing
checks in which the negative value is greater than
the positive value, and in which the difference
between the two is less than the value specified
in the tolerance_value argument.

46 May 16, 2017 Cadence Confidential

 Setting up SDF Annotation
Negative Timing-Checks

• Note that the sum of the two limits must be 0 or greater

– If the sum of the two arguments is less than 0, the negative limit is set
to 0 by default and one is getting a warning
– Now, there are also means to adjust the positive and negative limits for
an invalid negative timing check timing window

Keyword Specifies
-NTC_NEglim Adjust the negative limit for an invalid negative
timing check timing window.
-NTC_Poslim Adjust the positive limit for an invalid negative
timing check timing window.

Negative value set to 0 by default

-ntc_neglim

47 May 16, 2017 Cadence Confidential

 Setting up SDF Annotation
Disabling Timing Information

• Xcelium default behaviour is to follow the timing description of the

models but for any reason, one can disable some/all timing
information:
Keyword Specifies
-NOSPecify Disable timing information described in specify
blocks and SDF annotation
-NOTImingchecks Do not execute timing checks.
-NONOtifier Ignore notifiers in timing checks
-NO_TCHK_msg Suppress the display of timing check messages,
while allowing delays to be calculated from the
negative limits
-NTCNOtchks Generate negative timing check (NTC) delays,
but do not execute timing checks (if you want the
delayed signals to be generated but want to turn
off timing checks).

48 May 16, 2017 Cadence Confidential

 Setting up GLS
Disabling specific timing checks @ elab time

• tfile
-TFile timing_file (Verilog only)
– Use the specified timing file. A timing file is a text file that lets you turn
off timing for particular instances or portions of a design.

A timing file consists of a set of lines

• Each line pertain to
– specific instance(s) in the design
– hierarchical portions of the design
• Each line begins with a keyword and must be terminated by a
carriage return.
• Keywords are case-insensitive.

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 Setting up GLS
Disabling specific timing checks @ elab time

• List of keywords
Keyword Specifies
DEFAULT timing_spec Specifies the default timing behavior for all inst.
BASENAME [path] [timing_spec] Specifies the starting point for the path in all
subsequent PATH statements.
PATH path timing_spec Specifies whether timing is on/off for all matches
CELLINST timing_spec Specifies whether timing is on/off for all instances
that are tagged as cells and their subhierarchy.
CELLLIB lib.cell:view timing_spec Specifies whether timing is on/off
INCLUDE timing_file Include the contents of the specified timing file

• Note: If the HDL contains a $setuphold statement and the user has specified in timing file to disable the $setup timing
check in the tfile, then that $setup portion of the $setuphold will be disabled. Any potential timing violation for the setup
portion will not be seen in the simulation run.
– The reverse is not true. If the HDL contains $setup or $hold statement and tfile contains the statement to disable the $setuphold timing check,
none of the individual timing checks of $setup or $hold will be disabled.
– The same rules apply to $recrem with respect to $recovery and $removal.
• For the RETAIN SDF keyword data that is a part of IOPATH constructs, the annotator tool that runs during elaboration will
ignore the RETAIN data ( and thus disable it ) through the use of the -sdf_ignore_retain switch for xrun or the xmelab
tool.
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 Setting up GLS
Disabling specific timing checks @ elab time
// Disable timing checks in top.foo
• Example
// Disable timing checks in all scopes below top.foo

PATH top.foo -tcheck

// Enable timing checks in top.foo.bar
PATH top.foo... -tcheck

PATH top.foo.bar +tcheck // Disable timing checks for all objects in the library
mylib
CELLLIB mylib -tcheck
// No module path delays for all instances in the 2nd l
evels of hierarchy
PATH *.* -iopath

PATH top.foo –tcheck // Disable all timing checks in top.foo

PATH top.foo $setup –tcheck

// Disable $setup timing check in top.foo
PATH top.foo $setup $hold –tcheck
// Disable $setup and $hold timing checks in top.foo
CELLLIB mylib $width -tcheck

// Disable $width timing check for all objects in the

library mylib

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 Setting up GLS
Disabling specific timing checks on the fly

• tcheck
– The tcheck command turns timing check messages and notifier updates
on or off for a specified Verilog instance. The specified Verilog instance
can be an instance of a Verilog module instantiated in VHDL.
– tcheck Command Syntax
• tcheck instance_path -off | -on

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 Debugging GLS
Failed Attempt…

Error Message
xmelab: *W,SDFNEP: Failed Attempt to annotate to non-existent path
xmelab: *W,SDFNET: Failed Attempt to annotate to non-existent timing check

Problem
• The annotator follows strict rules when it matches Verilog timing checks to the
corresponding SDF checks

Always make sure that the annotator correctly interprets

and annotates your timing check data

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 Debugging GLS
Failed Attempt…

Solution
– The SDF timing check translation rules are as follows:
1. 1. If you specify a module path delay or timing check that does not already exist in
the Verilog model, the simulators cannot annotate the timing information.
2. If there is an edge specifier in an IOPATH statement in an SDF file, there must be
an exact match of the same edge specifier in the HDL model.
3. If there is an edge specifier in a TIMINGCHECK statement in an SDF file, there
must be an exact match in the HDL code.
4. If there is no edge specifier in an IOPATH or TIMINGCHECK statement in an SDF
file, then the simulator annotates data to any path (or timing check) in the HDL
code that has the same reference, and data nets specified in the SDF IOPATH or
TIMINGCHECK statement. Therefore, non-edge specified IOPATH and
TIMINGCHECK SDF statements overwrite their corresponding edge-specified
paths and checks in HDL.
5. SETUPHOLD statements in your SDF file do not annotate data to corresponding
but separate $setup and $hold statements in your Verilog code. However, you
can use the +sdf_splitvlog_suh command-line option to cause the SETUPHOLD
checks in an SDF file to be split into their component SETUP and HOLD checks,
provided there are no negative values in those checks.
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 Debugging GLS
An SDF 2 limit …

Error Message
xmelab: *W,SDFNG2: An SDF 2 limit timing check request (SETUPHOLD (negedge D)
(posedge CLK) (0.317) (-0.014)) contains a negative limit and was matched to 2
single limit timing checks. Negative limit will be set to 0.
xmelab: *W,SDFNL1 (dff_ars_seu2_1x.v,57|10):
Attempt to annotate a negative value to a 1 limit timing check in
instance(:STATE_reg_2), setting to 0.

Problem
• A negative timing check delay can only be applied to a two-limit timing check
specify block task. For example, a negative hold time must be matched by a
positive setup time in a single $setuphold timing system task call.
– Even if there exist corresponding individual $setup and $hold tasks, negative numbers
may not be annotated except to a single $setuphold task. These two warning types,
SDFNG2 and SDFNL1, cover the cases where an attempt is made to annotate
negative times to anything other than a two-limit timing check system task.
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 Debugging GLS
The interconnect src …

Error Message
xmelab: *W,SDFINC: The interconnect src top.Q is not connected to the destination
top.A3 in instance <./slow.sdf, line 95>. The interconnect request will be replaced with
a port annotation at the destination.
xmelab: *W,SDFSDM: Annotating delays from a source on net test.Q to a port on
different net test.A3, annotation performed anyway.

Problem
• SDFINC / SDFSDM warnings indicate that the two ports mentioned in an SDF
INTERCONNECT statement are not connected to the same net in a design.
– The SDF annotator assigns the given delay to the destination port anyway.
– Indicates a difference between the data used to create the SDF file and the
information in the Verilog model.
– Different warning codes.
• SDFCAI / SDFCAP if a destination pin is connected to a single driver through a continuous
assignment
• SDFINC / SDFSDM If the source and destination are truly on different nets
• These warnings can be disabled
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 Debugging GLS
Glitch

Error Message
Warning! Glitch suppression
Scheduled event for delayed signal of net "DD" at time 6FS was canceled!

Problem
• A schedule is cancelled when a delay schedules a transition to occur before a
previously scheduled transition. The message can only be generated for
Negative Timing Check delayed signals that have different rise and fall delays
calculated. In this case it is possible for the input events to cause a scheduled
output event to be cancelled. To better see what is going on:
• Add the option -ntc_verbose to the invocation. For the signals of interest compare the
calculated delays.
• Place monitors on the primary inputs for these delayed signals to see what they are doing
and to look at the input events to see how they compare to calculated delays for them
• If you want to see a glitch that happens in n FS, you'll need to do this by observing a
waveform that's dumped with event enabled
Solution
• Use the -nontcglitch switch when you run xmsim (three-step) or the
+ncnontcglitch switch when running xrun.
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 Debugging GLS
Pulse

Error Message
Warning! Pulse flagged as an error, value = StE
File: …/….v, line = 3935, pos = 8
Node: ….Z
Time: 1828852 PS + 0

Problem
• This warning message can be caused by the use of the +pulse_r/0 and
+pulse_e/100 options. They will control when to report the messages. In
this case, using 0% and 100%, any pulse that is smaller than the delay from
the input to the output of any gate is detected, it will report a warning.

Solution
• Use the -epulse_no_msg option of xmsim when you invoke the simulator
to suppress the display of error messages for pulses smaller than
error_percent.
• Change the percentages to allow different amount of glitches to pass
through. However you should consult whoever’s in charge of the library for
the recommended amount of pulse rejection to set.
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 Gate Level Simulation

SDF Annotation
SDF Annotation Flow
Gate-Level Sim. Debug
Summary

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 Xcelium Flow – Gate-Level
xmelab Verilog Options

-ANNO_SIMTIME -- Enables delay annotation at simulation time

-ARR_ACCESS -- Allow tf_nodeinfo access by turning off verilog array layout optimization
-CAIN -- Annotate an SDF PORT or INTERCONNECT delay even if the source & load ports are not hier. connec
-DELAY_MODE <arg> -- Delay mode {Zero, Unit, Path, Distr, None}
-DISABLE_ENHT -- Disable the enhanced timing features
-EPULSE_NEG -- Filter cancelled events (negative pulses) to e (overrides specify block settings)
-EPULSE_NONEG -- Do not filter cancelled events (negative pulses) to e (overrides specify block settings)
-EPULSE_ONDETECT -- On-detect filtering of error pulses
-EPULSE_ONEVENT -- On-event filtering of error pulses
-EXTEND_TCHECK_DATA_LIMIT <arg> -- Relaxes tcheck data limit
-EXTEND_TCHECK_REFERENCE_LIMIT <arg> -- Relaxes tcheck reference limit
-GATELOOPWARN -- Enable potential zero-delay gate loop warning
-NOAUTOSDF -- Automatic SDF Annotation is suppressed
-NOESP -- Disable edge sensitive iopath delays
-NONEG_TCHK -- Disallow negative values in SETUPHOLD & RECREM timing checks
-NONOTIFIER -- Notifiers are ignored in timing checks.
-NORTIS -- Disable retain input sense
-NOSPECIFY -- Don't execute timing checks, ignore path delays and skip SDF annotations.
-NTC_LEVEL <arg> -- Pick the behavior of the NTC algorithm 1-2. Default is 2.
-NTC_NEGLIM -- Adjust the negative limit for invalid ntc timing window
-NTC_POSLIM -- Adjust the positive limit for invalid ntc timing window
-NTC_TOLERANCE <arg> -- Specify tolerance value for ntc timing window
-NTC_VERBOSE -- Show limits changed by the NTC algorithm in order to make a circuit converge
-NTC_WARN -- Whether to produce convergence warnings for negative timing checks
-NTCNOTCHKS -- Generate NTC delays while removing timing checks

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 Xcelium Flow – Gate-Level
xmelab Verilog Options (Cont…)

-OVERRIDE_PRECISION -- Override the timescale precision in Verilog modules with the timescale precision value
provided in -timescale commandline arg
-OVERRIDE_TIMESCALE -- Override the timescale directives in Verilog modules with the timescale value provided in -
timescale commandline arg
-PATHPULSE -- Set pulse limits according to PATHPULSE$
-PATHTRAN -- Kill pathdelays that are touching to many tran gates
-PRINT_HDL_PRECISION <arg> -- Prints VHDL timescale.
-PULSE_E <arg> -- Sets percentage of delay for pulse error limit for both specify paths and interconnect
-PULSE_INT_E <arg> -- Sets percentage of delay for pulse error limit only for interconnect
-PULSE_INT_R <arg> -- Sets percentage of delay for pulse reject limit only for interconnect
-PULSE_R <arg> -- Sets percentage of delay for pulse reject limit for both specify paths and interconnect
-SDF_FILE <arg> -- Specifies the SDF file to use
-SDF_NOCHECK_CELLTYPE -- Don't check accuracy of CELLTYPE field
-SDF_NOPULSE -- Ignore SDF pulse information
-SDF_SIMTIME -- Allow SDF annotation to happen during simulation
-SDF_SPECPP -- Use PATHPULSE parameters in specify block for pathpulse calculation
-SDF_WORSTCASE_ROUNDING -- For SDF annotation, truncate min delays, round max delays up
-SEQ_UDP_DELAY <arg> -- Specify a constant delay for sequential UDPs
-TFILE <arg> -- Timing file.
-TIMESCALE <arg> -- Set default timescale on Verilog modules
-XLIFNONE -- Emulate XL's ifnone SDF annotation implementation.

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 Xcelium Flow – Gate-Level
xmelab VHDL Options

-NOIPD -- Ignore interconnect delays

-NO_TCHK_XGEN -- Turn off X-generation in VITAL timing checks
-NO_VPD_MSG -- Turn off VITAL pathdelay warnings
-NO_VPD_XGEN -- Turn off X-generation in VITAL pathdelays
-NOVITALACCL -- Turn off VITAL acceleration
-NOXILINXACCL -- Turn off Xilinx acceleration
-PRINT_HDL_PRECISION <arg> -- Prints VHDL timescale.
-VHDL_TIME_PRECISION <arg> -- Set default time precision for VHDL.
-VIPDMAX -- Select the Max. delay value for VitalInterconnectDelays
-VIPDMIN -- Select the Min. delay value for VitalInterconnectDelays

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 Xcelium Flow – Gate-Level
xmsim Options

-EPULSE_NO_MSG -- Suppress e-pulse error message

-NO_SDFA_HEADER -- Do not print the SDF annotation header
-NONTCGLITCH -- Suppress delayed net glitch suppression messages
-NTC_VERBOSE -- Show limits changed by the NTC algorithm in order to make a circuit converge
-SDF_NO_WARNINGS -- Do not report SDF warnings

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