East West University

POST LAB-5
Course Number & Name:
EEE102-Electronic Circuits 1
Semester & Year:
Spring-2023
Experiment No:05
Parameters and I-V characteristics measurement of an N-
channel MOSFET
Group Number: 02 Name of Lab Instructor:
Name of Student:

Md. Moshiur Rahman Jisan- Dr. M. Ryyan Khan

2022-1-80-023 Assistant Professor
Other’s group member: Department of EEE
Umme Hani Eshita
2022-1-80-015

Date of performance: 01.05.2023

Experiment No:05
Parameters and I-V characteristics measurement of an N-
channel MOSFET

Objective of the experiment

The objective of this experiment is to measure the parameters, namely
the threshold voltage, Vt and the process transconductance kn(W/L),
and the output characteristics (ID vs. VDS) of an N-channel enhancement
MOSFET.
Circuit Diagrams

Fig. 01: Measurement of Vt and kn(W/L) of an NMOS

Fig. 02: Circuit to measure I-V characteristics of an N-channel MOSFET

REQUIRED PARTS AND EQUIPMENTS
1. CD4007C
2. Resistors (1KΩ, 3MΩ)
3. Multimeter

Experimental Data
The value of resistance (3MΩ) =3.106 MΩ

VGS= 1.28 V, Vt= 1.28 V

The value of resistance (1KΩ) =0.985 KΩ

The voltage drop across the resistor= 5.173 V

ID = 5.2518 mA

VGS= 4.992 V

Kn(W/L) = 0.7623 mA/V^2

VGG = Vt + 2V = 3.28 V

VDD (VOLT) VDS (VOLT) VRD (VOLT) ID (mA)

0 0 0 0

0.2 0.03 0.08 0.081

0.4 0.098 0.24 0.125

0.8 0.21 0.48 0.487

1.2 0.36 0.786 0.797

1.6 0.519 1.04 1.055

2 0.725 1.3 1.319

2.4 0.913 1.46 1.482

3 1.31 1.6 1.624

3.8 2.1 1.638 1.663

 5 3.39 1.655 1.68

6 4.34 1.667 1.692

7 5.318 1.672 1.697

8 6.428 1.679 1.705

8.5 7.05 1.683 1.71

VGG = Vt + 3V = 4.28 V

VDD (VOLT) VDS (VOLT) VRD (VOLT) ID (mA)

0 0 0 0

0.4 0.08 0.267 0.271

0.8 0.178 0.56 0.569

1.2 0.274 0.84 0.853

1.6 0.38 1.14 1.157

2 0.5 1.45 1.472

3 0.821 2.16 2.193

4 1.18 2.76 2.802

5 1.78 3.23 3.279

6 2.65 3.3 3.35

7 3.65 3.37 3.421

8 4.62 3.4 3.452

9 5.59 3.42 3.472

10 6.6 3.43 3.482

10.5 7.05 3.435 3.487

Answers to lab-report questions:

Answer to question no 1
In the Fig.02, the drain and gate are shorted. When the drain and gate are
shorted, the N-Mosfet operates in Saturation. Therefore, we use the current
expression in Saturation. Gate voltage VG= Drain voltage VD and VGS=VDS.

Answer to question no 2

Vt= 1.28 V

Kn(W/L) = 0.7623 mA/V^2

We have 2 current expressions for two modes.

Linear for VDS < Vt and saturation for VDS > Vt

VGG = Vt + 2V = 3.28 V; VGS= 3.28 V

VDS (VOLT) ID (mA) [Calculated] ID (mA) [Experimental]

0 [linear]
0 0
0.045 [linear]
0.03 0.081
0.145 [linear]
0.098 0.125
0.298 [linear]
0.21 0.487
0.484 [linear]
0.36 0.797
0.656 [linear]
0.519 1.055
0.843 [linear]
0.725 1.319
0.975 [linear]
0.913 1.482
 1.525 [saturation]
1.31 1.624
1.525 [saturation]
2.1 1.663
1.525 [saturation]
3.39 1.68
1.525 [saturation]
4.34 1.692
1.525 [saturation]
5.318 1.697
1.525 [saturation]
6.428 1.705
1.525 [saturation]
7.05 1.71

ID Vs VDS Graph for VGG= 3.28 V

ID Vs VDS Graph
1.8
1.6
1.4
1.2
ID (mA)

1
0.8
0.6
0.4
0.2
0
0 1 2 3 4 5 6 7 8
VDS (VOLT)

ID (mA) [Calculated] ID (mA) [Experimental]

Now, VGG = Vt + 3V = 4.28 V; VGS= 4.28 V

VDS (VOLT) ID (mA) [Calculated] ID (mA) [Experimental]

0 [linear]
0 0
0.18 [linear]
0.08 0.271
0.391 [linear]
0.178 0.569
 0.589 [linear]
0.274 0.853
0.797 [linear]
0.38 1.157
1.02 [linear]
0.5 1.472
1.541 [linear]
0.821 2.193
2.0 [linear]
1.18 2.802
3.43 [saturation]
1.78 3.279
3.43 [saturation]
2.65 3.35
3.43 [saturation]
3.65 3.421
3.43 [saturation]
4.62 3.452
3.43 [saturation]
5.59 3.472
3.43 [saturation]
6.6 3.482
3.43 [saturation]
7.05 3.487

ID Vs VDS Graph for VGG= 4.28 V

ID Vs VDS Graph
4
3.5
3
2.5
ID (mA)

2
1.5
1
0.5
0
0 1 2 3 4 5 6 7 8
VDS (VOLT)

ID (mA) [Calculated] ID (mA) [Experimental]

 Answer to question no 3

There is a good difference between the calculated and experimental graph,

especially in the Saturation region. The main reason is behind that we used VDS,
when we calculated ID. But the in the experiment, we simply used ohm’s law.
That’s why we couldn’t get more accurate data. Both of the graphs the calculated
values line looks more accurate and rounded in the triode-to-saturation
converting phase. There are some measurement errors.

Answer to question no 4
For VGG= Vt+3 V = 4.28 V
ID1= 3.35 mA
ID2= 3.482 mA
VDS1= 2.65 V
VDS2= 6.6 V
Slope = (ID2-ID1)/(VDS2-VDS1) = (3.482-3.35) / (6.6-2.65) = 0.0334 mA/V

Output resistance, ro= 1 / Slope = 1 / 0.0334 = 29.94 kΩ

Early Voltage, VA = ID / ro = 3.416 / 29.94 = 0.114 V
[Here ID= 3.416 is on average]

Answer to question no 5
Circuit simulation:
 Fig. circuit diagram

Fig. DC sweep for the three different values of VGG

APPENDICES
LAB DATA SHEET: