UNIT 1 MICROPROCESSOR

ARCHITECTURE
Structure Page No.
Introduction
Objectives
Microcomputer Architecture
Structure of 8086 CPU
1.3.1 The Bus Interface Unit
1.3.2 Execut~onUnit (EU)
Register Set of 8086
Instruction Set of 8086
1.5.1 Data Transfer Instructions
1S.2 Arithmetic Instructions
1 S.3 Bit Manipulation Instructions
1 S.4 Program Execution Transfer Instructions
1 S.5 String Instructions .
1.5.6 Processor Control lnsthctions
Addressing Modes
1.6.1 Reg~sterAddressing Mode
1.6 2 Immediate Addressing Modc
1.6.3 Direct Addressing Modc
1.6.4 Indirect Address~ngMode
Summary
Solutions/Answers

1.O INTRODUCTION
In the previous blocks of this course, we have discussed concepts relating to CPU
organization, register set. ~nstructionset, addressing modes with a few examples. Let
us look at one micropmccssor architecture in regard of all the above concepts. We
have selected one of the sl~nplestprocessors 8086, for this purpose. Although the
131-ocessortechnology is old, all the concepts are valid for higher end Intel processor.
'Therefore, in this unit. w will discuss the 8086 microprocessor in some detail.

We have started the discbPb~onof the basic microcomputer architecture. This

discussion is followed b u 'lhe details on the components of CPU of the 8086
microprocessor. Then \\ s.hLve discussed the register organization for this processor.
We have also discussed t i i t ~atructionset and addressing modes for this procFssor.
Thus, this unit presents e\liabf*~.rr\.c
details of the 8086 microprocessor. These details
will then be used in Assembl), 1'1 ogramming.

1.l OBJECTIVES

.I After going through this unit, you should be able to:

describe the features of the 8086 microprocessor;
list various components of the 8086 microprocessor; and
identify the instruction set and the addressing modes of the 8086 microprocessor.
-
1.2 MICROCOMPUTER ARCHITECTURE
The word micro is used in microscopes, microphones, microwaves, microprocessors,
microcomputers, microprogramming, microcodes etc. It means small. A
5
I
 Assembly Language microprocessor is an example of VLSI bringing the whole processor to a single small
Programming
chip. With the popularity of distributed processing, the emphasis has shifted from the
single mainframe system to independently working workstations or functioning units
with their own CPU, RAM, ROM and a magnetic or optical disk memory. Thus, the
advent of the microprocessor has transformed the mainframe environinent to a
\
distributed platform.

Let us recapitulate the basic components of a microprocessor:

Input Device
Data bus .
Control Control Memory 1
I10 Ports CPU a

Bus (RAM & ROM)

Output Device
Address bus
Figure 1: Components of a Microcomputer

Please note the following in the above figure:

ROM stores the boot program. j
The path from CPU to devices is through,Buses. But what would be the size of
these Buses?

Bus Sizes I
1. The Address bus: 8085 microprocessor has 16 bit lines. Thus, it can access up to
216 = 64K Bytes. The address bus of 8086 microprocessor has a 20 bits address
bps. Thus it can access upto 2" = 1M Byte size of RAM directly.

2. Data bus is the number of bits that can be transferred simultaneousli It is 16 bits
in 8086.

I Microprocessors

! The microprocessor is a complete CPU on a single chip. The main advantages of the
microprocessor are:
compact but powerll;
oan be microprogrammed for user's needs;
easily programmable and maintainable due to small size; and
useful in distributed applications.

A microprocessor must demonstrate:

More throughput I
More addressing capability
Powerful addressing modes I

Powerful instruction set

Faster operation through pipelining
Virtual memory management.
, However, RISC machine do not agree with above principles. I

Some of the most commercially available microprocessors are: Pentium, Xeon, G4

etc.

c v

~
-
 - Microprocessor
The assembly language for more advanced chips subsumes the simplest 8086/ 8088 Architecture
asselnbly language. Therefore, we will confine our discussions to Intel 8086/8088
asse~nblylanguage. You must refer to the further readings for more details on
asselnbly language of Pentium, G4 and other processors.

All lnicroprocessors execute a continuous loop of fetch and execute cycles.

while (1)

fetch (instruction); , '

execute (using date);

i 1

1.3 STRUCTURE OF 8086 CPU

1

F -
t Tht: 8086 microprocessor consists of two independent units:
1. The Bus Interface unit, and
a
I 2. The Execution unit.
Please refer to Figure 2 . .
8086 Address and Data Bus

8
I
8
a
8
8
8
a
I

a
I
8'

...*-......*.-..,
8

8
8
8

..--
......
8
a
*

J .-
.-% *

Figure 2: The CPU of lNTEL 8086 Microprocessor

- .
Assembly Language
Programming
The word independent implies that these two units can function parallel to each other.
In other words they may be considered as two stages of the instruction pipeline.

1.3.1 The Bus Interface Unit

The BIU (Bus Interface Unit) primarily interacts with the system bus. It performs
almost all the activities relating to fetch cycle such as:
Calculating the physical address of the next instruction
Fetching the instruction
Reading or writing data memory or 110 port from memory or Input1 Output.
1
The instruction1data is then passed to the execution unit. This BIU consists of
lI
(a) The Instruction Queue

The instruction queue is used to store the instruction "bytes" fetched. Please
note two points here: that it is (1) A Byte (2) Queue. This is used to store
information in byte form, with the underlying queue data structure. The
advantage of this queue would only be if the next expected instructions are
fetched in advance, thus, allowing a pipeline of fetch and execute cycles.

(b) The Segment Registers

These are very important registers of the CPU. Why? We will answer this later.
In 8086 microprocessor, the memory is a byte organized, that is a memory
address is byte address. However, the number of bits fetched is 16 at a time. The
segment registers are used to calculate the address of memory location along
with other registers. A segment register is 16 bits long.

The BIU contains four sixteen-bit registers, viz., the CS: Code Segment, the DS:
Data Segment, the SS: Stack Segment, and the ES: Extra Segment. But what is
the need of the segments: Segments logically divide a program into logical
entities of Code, Data and Stack each having a specific size of 64 K. The
segment register holds the upper 16 bits of the starting address of a logical
group of memory, called the segment. But what are the advantages of using
segments? The main advantages of using segments are:

Logical division of program, thus enhancing the overall possible memory

use and minimise wastage.
The addresses that need to be used,in programs are relocatable as they are
the offsets. Thus, the segmentation supports relocatability. I
Although the size of address, is 20 bits, yet only the maximum segment
size, that is 16 bits, needs to be kept in instruction, thus, reducing
instruction length.
1
 m n H- of extra segment
Microprocessor
Architecture

-
- Offss(t = 001Oh in stack segment

60000h

- Stack segment base S S = 6000h

Top of code segment

t----- IP is having offset 1234

i 448AOh -
- Code segment base CS = 448Ah

Top of data segment

64K
-
-
Offset = OO2Oh in data segment

300qOh --L

u Bottom of data segment DS = 3000h

L Flgure 3: Logical Organisation of Memory in INTEL 8086 Mlcroproccssor

Although the size of each segment can be 64K, as they are overlapping segments we
can create variable sizeof'segments, with maximum as 64K. Each segment has a
specific function. 8086 supports the following segments:
As per model of assembly program, it can have more than one of any type of
segments. However,.at a time only four segments one of each type, can be active.
Assembly Language
Programming
range from OOOOh to FFFFh. But, how will the segment address and offset be added to
calculate physical address? Let us explain using the following examples:
Example 1 (In the Figure above)
The value of the stack segment register (SS) = 6000h
The value of the stack pointer (SP) which is Offset = 0010h

Thus, Physical address of the top of the stack is:

-Implied zero
6 0 0 1 0
Physical Address

This calculation can be expressed as:

Physical address = SS (hex) x 16 + SP (hex)

Example 2
The offset of the data byte = 0020h
The value of the data segment register (DS) = 3000h
Physical address of the data byte

DS
- -

- Implied Zero
Offset

Physical Address
3 0 0 2 0

This calculation can be expressed as physical address = DS (Hex) x 16 + Data byte

offset (hex). + C

Example 3
The value of the Instruction Pointer, holding address of the instruction = 1234h
The value of the code segment register (CS) = 448Ah
Physical address of the instruction

Physical Address 4 5 A 0 4

Physical Address = CS (Hex) x 16 + IP

(c) Instruction Pointer

The instruction pointer points to the offset of the current instruction in the code
segment. It is used for calculating the address of instruction as shown above.
 Microprocessor
1.3.2 Execution Unit (EU) Architecture

Execution unit performs all the ALU operations. The execution unit of 8086 is of 16
bits. It also contains the control unit, which instructs bus interface unit about which
memory location to access, and what to do with the data. Control unit also performs
decoding and execution of the instructions. The EU consists of the following:

(a)! Control Circuitry, Instruction Decoder and ALU

The 8086 control unit is primarily micro-programmed control. In addition it has an
inr;truction decoder, which translates an instruction into sequence of micro operations.
The ALU performs the required operations under the control of CU which issues the
necessary timing and control sequences.

(b) Registers
All CPUs have a defined number of opera' :anal registers. 8086 has several general
purpose and special purpose registers. We ill discuss these registers in the following
sections.

REGISTER SET OF 8086

-1.4
The 8086 registers have five groups of registers. These groupings are done on the
basis of the main functions of the registers. These groups are:
1 General Purpose Register
8086 microprocessors have four general purpose registers namely, AX, BX, CX, DX.
All these registers are 16 - bit registers. However, each register can be used as two
g,eneral-purposebyte registers also. These byte registers are named AH and AL for
AX,BH and BL for BX, CH and CL for CX, and DH and DL for DX. The H in
register name represents higher byte while L represents lower byte of the 16 bits
registers. These registers are primarily used for general computation purposes.
Ilowever, in certain instruction executions they acquire a special meaning.

,4X register is also known as accumulator. Some of the instructions like divide, rotate,
shift etc. require one of the operands to be available in the accumulator. Thus, in such
~nstructions,the value of AX should be suitably set prior to the instruction.

rn BX register is mainly used as a base register. It contains the starting base location of a
memory region within a data segment.

CX register is a defined counter. It is used in loop instruction to store loop counter.

DX register is used to contain I10 port address for 110 instruction.

You will experience their usage in various assembly programs discussed later.
Segment Registers
Segment Registers are used for calculating the physical address of the instruction or
memory. Segment registers cannot be used as byte registers.

Pointer and Index Registers

The 8086 microprocessor has three pointer and index registers. Each of these registers
is of 16 bit and cannot be accessed byte wise. These are Base Pointer (BP), Source
Index (Sl) and Destination Index (DI). Although they can be used as general purpose
registers, their main objective is to contain indexes. BP is used in stack segment, SI in
Data segment and DI in Extra Data segment.
11
Assembly Language
Programming
Special Registers
-4 Last in First Out (LIFO) stack is a data structure used for parameter passing, return
adckess storage etc. 8086 stack is 64K bytes Base of the stack is pointed to by the
stack segment (SS) register while the offset or top of the stack is stored in Stack
Pointer (SP) register. Please note that although the memory in 8086 has byte
addresses, stack is a word stack, which is any push operation will occupy two bytes.

Flags Register
A flag represents a condition code that is 0 or 1. Thus, it can be represented using a 1
flip- flop. 8086 employs a 16-bit flag register containing nine flags. The following
table shows the flags of 8086.

Conditional flags are set by some condition generated as a result of the last

-- CF
PF
Carry Flag
Parity Flag
1 if there 1s a carry bit
1 on evenparity 0 on odd parity
Auxiliary F& -- Set (1) if auxiliary cany for BCD occurs
Set ~fresult is equal to zero
Indicates the sign of the result (1 for minus, 0

. OF Overflow Flag set whekver there is an overflow of the result

Control flags, which are set or reset deliberately to control the operations of the
- execution unit. The control flags of 8086
- are as follows: -------
TF Single step trap Used for single stepping through the program
flag

Interrupt Enable Used to allow/inhibit the interruption of the

Check Your Progress 1

1. What is the purpose of the queue in the bus interface unit of 8086
. microprocessors?
................................................................................................
................................................................................................
................................................................................................
2. Find out the physicil addresses for the following segment register: offset
(a) SS:SP = 0100h:0020h
(b) DS:BX = 0200h:0100h
(c) CS:IP = 4200h:0123h

3. State True or False.

(a) BX register is used as an index register in a data segment.

(b) CX.register is assumed to work like a counter.

i
 Microprocessor
(c) The Source Index (SI) and Destination Index(D1) registeis in 8086 can also be Architecture
used as general registers.

(d) -
Trag Flag (TR) is a conditional flag.
-
1.5 INSTRUCTION SET OF 8086
-
Afler discussing the basic organization of the 8086 micro-processor, let us now
provide an overview of various instructions available in the 8086 microprocessor. The
instruction set is presented in the tabular form. An assembly language instruction in
the 8086 includes the following:
Label: Op-code Operand@); Comment
For example, to add the content of AL and BL registers to get the result in AL, we use
the following assembly instruction.

NEXT: ADD AL,BL ;ALeAL+BL

Please note that NEXT is the label field. It is giving an identity to the statement. It is
an optional field, and is used when an instruction is to be executed again through a
L.OOP or GO TO. ADD is symbol~cop-code, for addition operation. AL and BL are
the two operands of the instructions. Please note that the number of operands is

i -
c~ependentupon the instructions. 8086 instructions can have zero, one or two
operands. An operand in 8086 can be:
1.
2.
A register .
A memory location
3. A constant called literal
4. A label. I

We will discuss the addressing modes of these operands in section 1.6.

Comments in 8086 assembly start with a semicolon, and end with a new line. A long
comment can be extended to more than one line by putting a semicolon at the
beginning of each line. Comments are purely optional, however recommended as they
provide program documentation. In the next few sections we look at the instruction set
of the 8086 microprocessor. These instructions are grouped according to their
functionality.

1.5.1 Data Transfer Instructions

These instructions are used to transfer data from a source operand to a destination
operand. The source operand in most of the cases remains unchanged. The operand
can be a literal, a memory location, a register, or even an 110 port address, as the case
Assembly Langaage
Programming PUSH operand Pushes the operand into a stack. PUSH BX
SP t S P - 2 ; ; decrement stack polnter
value [TOS] t operand. ;by; two, and copy BX to
Initialise stack segment register, and ;stack.
the stack pointer properly before ; decrement stack pointer
using this instruction. No flags are ;by two, and copy
effected by this instruction. The ; BX to stack
operand can be a general purpose
register, a segment register, or a
memory location. Please note ~t is a
word stack and memory address is a
byte address, thus, you decrement by
2 Also you decrement as SP is
initialised to maximum offset and
condition of stackful is a zero offset
(io it is a reversed stack)
POP des POP a word from stack. The des can POP AX
be a general-purpose register, a ; Copy content for top
segment register (except for CS ; of stack to AX.
register), or a memory location. Steps
are:
des t value [TOS]
SP t S P + 2
XCHG des, src Used to exchange bytes or words of XCHG DX,AX
src and des. It requires at least one of ; Exchange word in DX
the operands to be a register operand. ;with word in AX
The other can be a register or memory
operand. Thus, the instruction cannot
exchange two memory iocations
directly. Both the operands should be
either byte m e or word type. The
segment registers cannot be used as
operands for this instruction.
XLAT Translate a byte in AL using a table Example 1s available In
stored in the memory. The instruction Unit 3.
replaces the AL register with a byte
from the lookup table. This
instruction is a complex instruction.
IN accumulator, It transfers a byte or word from IN AL,028h
port address specified port to accumulator register. ; read a byte from port
In case an 8-bit port is supplied as an ; 028h to AL register
operand then the data byte read from
that part will be transferred to AL
register. If a 16-bit port is read then
the AX will get 16 bit word that was
read. The port address can be an
immediate.operand, or contained in
DX register. This instruction does not
change any flags.
OUT port It transfers a byte or word from
address, accumulator register to specified port.
Accumulator This instruction is used to output on
devices like the monltor or the pr~nter.
LEA register, Load "effective address" (refer to this LEA BX, PRICES
source term in block 2, Unit 1 in addressing ;Assume PRICES is
modes) of operand into specified 16 - ; an array in the data
bitregister. Since, an address is an ; segment. The
o f f b e t i n c t i o n loads the
 Microprocessor
be of 16 bits, therefore, the register ; offset of the first byte of Architecture
can only be a 16-bit register. LEA ; PIUCES directly into
instruction does not change any flags. ; the BX register.
The instruction is very useful for
I array processing.
LDS des-reg I It loads data segment register and LDS SI, DATA
. othkr specified register by using ; DStcontent of memory
consecutive memory locations. ; location DATA &
; DATA + 1
; SI t content of
; memory locations
;DATA+2&DATA+
:3
LES des-reg It loads ES register and other
specified register by using
consecutive memory locations. This
instruction is used exactly like the
LDS except in this case ES & other
-
specified registers are initialized.
LAHF Copies the lower byte of flag register
to AH. The instruction does not
change any flags and has no operands.
SAHF Copies the value of AH register to
low byte of flag register. This
instruction is just the opposite of •
LAHF instruction. This instruction
has no operands.
PUSHF Pushes flag register to top of stack.
SP t SP - 2; stack [SP] t Flag
Register.
Pops the stack top to Flag register.
i 'OpF Flag register t stack [SP]
SP t S P + 2

1 1.5.2 Arithmetic Instructions

MNEMONIC DESCRIPTION EXAMPLE
ADD Adds byte to byte, or word to word. ADD AL,74H
The source may be an immediate ;Add the number 74H to
operand, a register or a memory ; AL register, and store the
location. The rules for operands are ;result back in AL
the same as that of MOV instruction. ADD DX,BX
To add a byte to a word, first copy the ;Add the contents of DX to
byte to a word location, then fill up ; BX and store the result in ;
the upper byte of the word with zeros. DX, BX remains
This instruction effects the following ; unaffected.

--t ADC des, src

flags: AF, CF, OF, PF, SF. ZF.
Add byte + byte + carry flag, or word
+ word + carry flag. It adds the two
operands with the carry flag. Rest all
the details are the same as that of
( ADD instruction. i
INC des I It increments svecified bvte or word 1 INC BX
operand by one. The ope;and can be a ; Add 1 to the contents of
register or a memory location. It can ; BX register
effect AF, SF, ZF, PF, and OF flags. INC BL
It does not affect the carry flag, that ';,Add 1 to the contents of
is, if you increment a byte operand 7 ;BL register
Assembly Language
Programming having OFFH, then it will result in 0
value in register and no cany flag.
AAA ASCII adjusts after addition. The data ADD AL,BL
entered fiom the terminal is usually in ;AL=00 1 10101, ASCII 05
ASCII format. In ASCII 0-9 are ; BL=00 1 11001, ASCII 09
represented by codes 30-39. This ; after addition
instruction allows you to add the ;AL = 01 101110, that is,
ASCII codes instead of first ; 6EH- incorrect
converting them to decimal digit ;temporary result
using masking of upper nibble. AAA AAA
instruction is then used to ensure that ;AL = 00000 100.
the result is the correct unpacked ;Unpacked BCD for 04
BCD. ; carry = 1, indicates
; the result is 14
DAA Decimal (BCD) adjust after addition. ; AL = 0 101 1001 (59
This is used to make sure that the ; BCD)
result of adding two packed BCD ; BL = 001 1 0101 (35
numbers is adjusted to be a correct ; BCD)
BCD number. DAA only works on ADD AL, BL
AL register. ; AL = 10001101 or
;8Eh (incorrect BCD)
DAA
; AL = 1001 0100
;E 94 BCD : Correct.
SUB des, src Subtract byte from byte, or word from SUB AX, 3427h
word. (des f des - src). For ; Subtract 342% from AX
subtraction the carry flag r'unctions as ;register, and store the
a borrow flag, that is, if the number in ;result back in AX
the source is greater than the number
in the destination, the borrow flag is
to set 1. Other details are equivalent
to that of the ADD instruction.
SBB des, src Subtract operands involving previous SBB AL,CH
carry if any. The instruction is similar ; subtract the contents
to SUB, except that it allows us to ;of CH and CF from AL
subtract two multibyte numbers, ; and store the result
because any borrow produced by ; back in AL.
subtracting less-significant byte can
be included in the result using this
instruction.
DEC src Decrement specified byte or specified DEC BP
word by one. Rules regarding the ; Decrement the contents
operands and the flags that are ; of BP
affected are same as INC instruction. ;register by one.
Please note that if the contents of the
operand is equal to zero then after
decrementing the contents it bedomes
OFFH or OFFFFH, as the case may be.
The catry flag in this case is not
affected.
NEG src Negate - creates 2's complement of a NEG AL
given number, this changes the sign ; Replace the number in
of-a number. However, please note ; AL with it's 2's
that if you apply this instruction on ;complement
operand having value -128 (byte
operand) or -32768 iword operand) it
will result in overflow condition. The
overflow (OF) flag will be set to
 indicate that operation could not be

operands or two specified word ; Compare the CX register

operands. The source and destination ; with the BX register
operands can be an immediate ; In the example above, the ;
number, a register or a memory CF, ZF, and the SF flags
location. But, both the operands ; will be set as follows.
cannot be memory locations at the ; CX=BX 0 1 0; result of
same time. The comparison is done ;subtraction is zero
simply by internally subtracting the ;CX>BX 0 0 0; no borrow ;
source operand from the destinatiofi required therefore, CF=O
operand. The value of source and the ;CX<BX 1 0 1
destination, operandr is not changed, ; subtraction require
but the flags are set tq indicate the ;borrow, so CF=1
results of the compa~. son.
ASCII adjust after su~traction.This ;AL = 001 1 0101 ASCII 5
instruction is similar to AAA (ASCII ; BL= 001 1 1001 ASCII 9
adjust after addition) instruction. The SUB AL,BL
AAS i n s t m i a n works on the AL ; (5-9) result:
register only. It updates the AF and ;AL= 1111 1100 = - 4 in
CF flags, but the OF, PF, SF and the . ; 2's complement, CF = 1
ZF flags remain undefined. AAS ;result: - - - .
;AL=00000100= - -
; BCD 04,
;CF = 1 borrow needed.

sure the result is the packed BCD. ;AL=2Fh, CF =O

DAS only works on the AL register. DAS
The DAS instruction updates the AF, ;Results in AL = 29 BCD
CF, SF, PF and ZF flags. The
overflow (OF) is undefined after

instruction that multiplies two bytes MOV CX,02; CX=02

to produce a word operand or two MUL CX
words to produce a double word such ;results in DX=O
;AX=OAh
AX t AL* src (byte multiplication

multiplication is two word).

.This instruction assumes one of the
operaad in AL (byte) or AX (word):
the src operand can be register or
memory operand. If the most
significant word of the result is zero
then, the CF and the OF flags are both
made zero. The AF, SF, PF, ZF flags
are not defined after the MUL
instruction. If you want to multiply a
byte with a word, then first convert
- byte to a word operand.
;AL=0000 0101 unpacked
Please note that two ASCII numbers ;BCD 05
cannot be multiplied directly. To ; BH=0000 100 1 unpacked ;
multiply first convert the ASCII
-
 number to numeric digits by masking MUL BH
ofi the upper nibble of each byte. This ; AX=AL * BH=002Dh
leaves unpacked BCD in the register. AAM
AAM instruction is used to adjust the ;AX=00000100 00000101 ;
product to two unpacked BCD digits BCD 45 : Correct result
in AX after the multiplication has
been performed. AAM defined by the
instruction while the CF, OF and the
AF flags are left undefined.
DIV src This instruction divides unsigned ;AX = 37D7h = 14295
word by byte, or unsigned double ;decimal
word by word. For dividing a word by ; BH = 97h = 151 decimal
a byte, the word is stored in AX DIV BH
register, diviso~the src operand and ; AX / BH quotient
the result is obtained in AH : ;AL=5Eh=94
remainder AL: quotient. It can be ; decimal RernainderAH = ;
I represented as: 65h = 101
AH: Remainder ) + Aw src ; decimal
AL: Quotient
Similarly for double word division by
a word we have
DX: Remainder
AX: Quotient > + DX:AXl src

A division by zero result in run time

error. The divisor src can be either in
a register or a memory operand.
IDIV Divide signed word by byte or signed ; AL = 11001010 = -26h =
?
double word by word. For this ; - 38 decimal
division the operand requirement, the ;CH = 0000001 1 = + 3h =
general format of the instruction etc. ;3 decimal
are all same as the DIV instruction. ; According to the operand
IDIV instruction leaves all flags ;rules to divide by a byte
undefined. ;the number should be
; present in a word register, ;
- i.e. AX. So, first convert
; the operand in AL to word
; operand. This can be done ;
by sign extending the
; AL register,
; this makes AX
; 11111111 11001010.
;(Sign extension can also
; be done with the help of
;an instruction, discussed
; later)
I D N CH
;AXICH
; A L = 11110100=-OCH;
= - 12 Decimal
; A H = 11111110=-02H=;-
02 Decimal
;Although the quotient is
;actually closer to -13
;(-'12.66667) than -12, but
; 8086 truncates the result
; t o give-12.
A m ASCII adjust after division. The BCD ;AX= 0607 unpacked
numbers are first unpacked, by ; BCD for 6
 I

Microprocesm ,
\
masking off the upper nibble of each ;and 7 CH = 09h Architecture
byte. Then ADD instruction is used to AAD
convert the unpacked BCD digits in ; adjust to binary before
AL and AH registers to adjust them to ;division AX= 0043 =
equivalent binary prior to division. ;043h = 67 Decimal
Such division will result in unpacked DIV CH
BCD quotient and remainder. The PF, ;Divide AX by unpacked
SF, ZF flags are updated, while the ; BCD in CH
AF, CF, and the OF flags are left ; AL = 07 unpacked BCD
undefined. ;AH = 04 unpacked BCD
;PF=SF=ZF=O
CBW Fill upper-byte or word with copies ; AL = 1001 1011 = - 155
of sign bit of lower bit. This is called ; decimal AH = 00000000
sign extension of byte to word. This CBW ;convert signed
instruction does no1 change any ;byte in AL to signed
flags. This operatio11is done with AL ; word in AX = 11111111
register in the result being stored in ; 10011011 = - 1% decimal
*
AX.
CWD Fill upper word or double word with ; DX : 0000 0000 0000 0000
sign bit of lower word. This ;AX:1111000001010001
instruction is an extension of the CWD
previous instruction. This instruction ;DX:AX=
;
1111 1111 1111 1111:
0000 0101 0001
results in sign extension of AX
register to DX:AX double word.

These instructions are used at the bit level. These instructions can be used for testing a
zero bit, set or reset a bit and to shift bits across registers. Let us look into some such

' NOT
' MNEMONIC
des
DESCRIPTION
Complements each bit to produce
EXAMPLE
; BX = 00 11 1010 000 1 0000
1's complement of the specified NOT BX
byte or word operand. The ; B X = 11000101 1110 1111
operand can be a register or a
memory operand.
AND des, src Bitwise AND of two byte or word ;BH = 001 1 1010 before
operands. The result is des f des AND BH, OFh
AND src. The source can be an ; BH = 0000 1010
immediate operand a register, or a ; after the AND operation
memory operand. ne destination
can be a register or a memory
operand. Both operands cannot be
memory operands at the same
time. The CF and the OF flags are
both zero after the AND
operation. PF, SF and ZF area
updated, Afis left undefined.
OR des, src OR each corresponding bits of the ; BH = 001 l 1010 before
byte or word operands. The other OR BH, OFh
operands rules are same as AND. ; BH = 001 1 1111 after
des C des OR src
XOR des,src XOReachcorrespondingbitina ;BX =0011110101101001
byte or word operands rules are ; CX = 00000000 11111111
two same as AND and OR. XOR BX,CX
des C Des + src ;BX=0011110110010110
;Please note, that the bits in
;the lower byte are inverted.
bsseqbly Language TEST des, src I @ID the operands to update
--' ;AL.= 0101 0001
RriQjogramyping
flags, but-donot change operands TEST AL, 80h.
value. It can be used to ~ eand
t ; This iflsmction would
.test conditions.CF and OF are ;test if b e MSB bit 9f the &
, both set to zero, PF, SF and ZF ;register is zero or one. After
e are all u&ted, @ is left ;the TEST operation ZF will
. : /., . , .undefme&aftqrthe operation,

~coUnt: . cobnt, It puts zero(s) in LSB(s).

MSB is shifted into the carry flag.
-
;if CF 0
; BX = 1000 1001
J
If more than ope bits are shifted ;result :CF = 1
left, then the CF gels the most ; BX = 0001 0010
, remntly moved MSB. If the

nurnber of bits desired to be

shifted is only 1, then the
, immediate number. 1 can be
I
written as one of the operands.
I
However, if the number of bits
'
deSired to be shifted is more than
one, then the second operand is

;BX = 1000 1001

;BX= 01000100
MOV.CL, 02
SHR BX, CL
;with same BX, the
;result would be

; BS = 0010 0100
;i+L=OOOl 1101 = +29
;decimal, CF = 0
MSB to that of old MSB. This is ,SAR 4L,01
also called arithmetic shift ,;AL=0000 1110=+14
, , operation, as it does not change ;decimal, CF = 1
k MSB, which is sign bit of a ;OF = PF = SF = ZF = 0
I - numb&:

SAR BH,Ol
; B H = 1111 1OO1=-7
.: ;decimal, CF =1

ROL des, count Rotate bits of word or byte left,

MSB is transferred to LSB and
also to CF. Diagrammatically, it
can be represented as:

., 1 ,

The operation is called rotate as it

~circdatesbits. The operands~an' 5
:
I s be register or memory operand.
ROR ds, eount Rotate3its of word or byte right, ;CF = 0,
 MStrap&k.wm
Architectare'

;BX-1001 1101 1011 1

carry flag in rotation, .

w Check Your Pmgress 2

1. Point out the error/ t$rors in the following 8086 assembly instruction (if any)?
a. ' PUSHF AX '

c. XCHG MEM-WORDI, MEM-WOW

d: AAAdBL, CL
e. IDNAX, CH

2. > . ,sfate
< .
True or False in the context of 8086 assembly language.
(a) LEA and MOV instruction serve the same purpose. The only difference
between the two is the type of operands they take.

(b) NEG instructimproduces 1's complement of a number.

OR bpersttion, but does not change the value

(e)
'
Suppose .ALc h a i n s 0 110 010 f and CF is set, then instructions ROL AL
and RCL AL will produce the same results.
Assembly Language
Programming 1.5.4 Program Execufion Transfer Instructions
These instructions are the ones that causes change in the sequence of execution of
instruction. This change can be through a condition or sometimes may be
unconditional. The conditions are represented by flags. For example, an instruction
may be jump to an address if zero flag is set, that is the last ALU operation has
resulted in zero value. These instructions are often used after a compare instruction, or
some arithmetic instructions that are used to set the flags, for example, ADD or SUB.
LOOP is also a conditional branch instruction and is taken till loop variable is below a
certain count.
Please note that a "I" is used to separate two mnemonics which represent the same
instruction.
MNEMONIC DESCRIPTION EXAMPLE
CALL proc 1 I This function results in a I CALL procl
procedure1 function call. The CALL proc2
return address is saved on the The new instruction
stack. There are two basic types address is determined by
of CALLS. NEAR or Intra- name declaration proc 1 is
Segment,calls: if the call is made a near procedure, thus,
to a procedure in the same only IP is involved. proc2
segment as the calling program. involves new CS: IP pair.
FAR or Inter segment call: if the On call to proc 1
call is made to a procedure in the stack C IP
segment, other than the calling IP C address offset of
program. The saved return proc 1
address for NEAR procedure on call to proc2
call is just the IP. For FAR Stack [top] C CS
Procedure call IP and CS are Stack [top] C IP
saved as return address. CS C code segment of
proc2
IP C address offset of
proc2
Here we assume that procl
is defined within the same
segment as the calling
procedure, while proc2 is
defined in another
segment. As far as the
calling program is
concerned, both the
procedures have been
called in the same manner.
But while declaring these
procedures, we declare
procl as NEAR procedure
and proc2 as FAR
procedure, as follows:
procl PROC NEAR
proc2 PROC FAR
A procedure can also be called LEA BX, procl
indirectly, by first initializing ;initialize BX with the
some 16-bit register, or some ;offset of the procedure
other memory location with the ;procl
new addresses as follows. CALL BX
;CALL procl indirectly
;using BX register
RET number It returns the control from RET 6
27 .-
 Microprocessor
procedure to calling program. ; In this case, 8086 Architecture
Every CALL should be a RET ; increments the stack
instruction. A RET instruction, ;pointer by this number
causes return from NEAR or ; after popping off the 1P
FAR procedure call. For return ; (for new) or IP and CS
from near procedure the values ;registers (for far) from
of the instruction pointer is ; the stack. This cancels
restored from stack: While for ;the local parameters, or
far procedure the CS:IP pair get ;temporary parameters
is restored. RET instruction can ;created by the
also be followed by a number. ; programmer. RET
; instruction does not
; affect any flags.
Unconditionally go to specified JMP CONTINUE
address and get next instruction ; CONTINUE is the label
from the label specified. The ; given to the instruction
label assigns the instruction to ; where the control needs
which jump has to take place ; to be transferred.
within the program, or it could JMP BX
be a register that has been ; initialize BX with the
initialised with the offset value. ; offset of the instruction,
JMP can be a NEAR JMP or a ; where the control needs

1 1 Conditional Jump I FAR jump, just like CALL. ; to be transferred.

All the conditional jumps follow 1-MOVCX. 05
some conditional statement, or MOV BX, 04
any instruction that affects the c ~ CX, p BX
; this instruction will set
;various flags like the ZF,
;and the CF.
JE LABELl
;conditional jump can
;now be applied, which
; checks for the ZF, and if
; it is set implying CX =
; BX, it makes
; a jump to LABELl,
; otherwise the control
; simply falls
; through to next
;instruction
; in the above example as
; CX is not equal to BX
; the jump will not take
;place and the next
; instruction to conditional
;jump instruction will be
; executed. However, if
;JNE (Jump if not equal
; to) or JA (Jump if
above), ;or JAE (Jump
above or
; equal) jump instructions
; if applied instead of JE,
;will cause the conditional

All the conditional jump instructions which are given below

are self explanatory.

below nor equal 23

 Assembly Language -
- prpgrarnmirg
JAEIJNB Jump if above or equaY Jump if
not below
JBIJNAE Jump if below1 Jump if not
above nor equal
JBEIJNA Jump if below or equal/ Jump if
not above
JC Jump if carry flag set
JEIJZ Jump if equal / Jump if zero flag
is set
JNC Jump if not carry
JNEIJNZ Jump if not equal / Jump if zero
flag is not set
.JO Jump if overflow flag is set
JNO Jump if overflow flag is not set
JPIJPE Juhp ifparity flag is set / Jump
if parity even '
JNP/JPO Jump if not parity /Jump if
- parity odd
JGIJNLE Jump if greater th& I Jump if
nut less than nor equal
JAlJ'I% Jump if above 1 Jump if not less
than
JWJNGE Jump if less than / Jump if not
greater than nor equal
JLEIJNG jump if less than ot equkl to /
,.
jump if not greateftban
JS Jump if sign flag is set
?
JNS jump if sign flag is not set
LOOP label This is a looping instruction of ;Let us assume we want to
assembly. The number of times ;add 07 to AL register,
the looping is required is placed ;three times.
iq CX register. Each iteration MOV CX,03
decrements CX register by one ; count of iterations
'
irpplicitly, and the Zero Flag is Ll : AnD AL,07
checked to check whether to LOOP L1; loop back to Ll,
loop again. If the zero flag is not ; until CX
-
set (CX is zero) greater than the ; becomes equal to zero
control goes back to the ; Loop affects no flags.
specified label in the instruction,
or else the control falls through
to the next instruction. The
LOOP instruction expects the
label destination at offset of-
128 to +I27 from the loop
instruction offszt.
LOOPE/ LOOPZ Loop through a sequence of Let ue assume we have an
label instructions while zero flag = 1 array of 20 bytes. We want
and CX is not equal to zero. to see if all the elements of
There are two ways to exit out of that array are equal to
the loop, firstly, when the count OFFh or not. To scan 20
in the CX register becomes equal elements of the array, we
to zero, or when the quantities loop 20 times. And we
that are being compared become come out of the loop,
unequal. when either the cowt of
iterations has become
equal to 20, or in other
.. words CX register has
 Mieroprocessar
decremented to zero, Architecture
wl~ichmeans all the
elements of the array are
equal to OFFh, or an
element in the array is
found which is not equal ,
to OFFh. In this case, the
CX register may still be
greater than zero, when the
control comes out. This
can be coded as follows:
(Please note here that you
might not understand
everything at this place,
that is because you are still
not familiar with the
various addressing modes.
Just concentrate on the
LOOPE instruction):

MOV BX, OFFSET ARRAY

; Point BX at the start
; of the ARRAY
DEC BX ;put number of
; array elements in CX
MOV CX, 10
L1: INC BX ;point to
;next element in array
CMP [BX] ,OFFh
;compare array element
;with OFFh
LOOPE L1
;When the control comes
; out of the loop, it has
;either scanned all the
;elements and found them
;to be all equal to OFFh, or
; it is pointing to the first
; non-OFFh, element in the
; array.
LOOPNEILOOPNZ
' This instruction causes Loop
through a sequence of
instructions while zero flag = 0
and CX is not equal to zero. This
instruction is just the opposite of
I

=O. This instruction will cause a when you want to check

jump, if the value of CX register whether CX is zero even
is zero. Otherwise it will proceed prior to entering into a
with the next instruction in loop. Please note that
sequence. LOOP instruction executes
the loop at least once
before decrementing and
checking the value of CX
register. Thus, CX=O will
execute the loop once and
decrement the CX register,
Assembly Language
Programming making it OFFFFh, which
is non zero: This will
cause FFFFh times .
execution of loop. To
avoid such type of
conditions you can
proceed as follows:
JCXZ SKIP -LOOP
; if CX is already 0, skip
;loop
Ll : SUB [BX],07h
INC BX
LOOP Ll
;loop until CX=O
SKIP LOOP: ........
In addition to these instructions, there are other intempt handling instructions also,
which too transfer the control of the program to some specified location. We will
discuss these instructions in later units.

1.5.5 String Instructions

These are a very strong set of 8086 instructions as these instructions process strings, in
a compact manner, thus, reducing the size of the program by a considerable amount.
"String" in assembly is just a sequentially stored bytes or words. A string often
consists of ASCII character codes. A subscript B following the instruction indicates
that the string of bytes is to be acted upon, while "W" indicates that it is the string of
words that is being acted upon.
MNEMONIC DESCRIPTION EXAMPLES
REP This is an instruction prefix. It REP MOVSB STRl ,STR2
causes repetition of the following The above example copies
instruction till CX becomes zero. byte by byte contents. The
REP. It is not an instruction, but it CX register is initialized to
is an instruction prefix that causes contain the length of source
the CX register to be decremented. string.REP repeats the
This prefix causes the string operation MOVSB that
instruction to be repeated, until CX copies the source string byte
becomes equal to zero. to destination byte. This
operation is repeated until
the CX register becomes
equal to zero.
REPEIREPZ It repeats the instruction following
until CX =O or ZF is not equal to
one. REPEIREPZ may be used
/
with the compare string instruction
or the scan string instruction.
REPE causes the string instruction
to be repeated, till compared bytes
or words are equal, and CX is not
yet decremented to zero.
REPNEIREPNZ It repeats instruction following it
until CX =O or ZF is equal to 1.
This comparison here is just
inverse of REPE except for CX,
'
which is checked to be equal to
zero.
MOVSIMOVSBI It causes moving of byte or word Assumes both data and extra
MOVSW from one string to another. This segment start at address 1000
26

1
Q

I
 Microprocessor
instruction assumes that: in the memory. Source string Architecturca
Source string is in Data starts at offset 20h and the
segment. destination string starts at
Destination string is in extra offset 30h. Length of the
data segment source string is 10 bytes. To
SI stores offset of source copy the source string to the
string in extra segment destination string, proceed as
DI stores offset of destination follows:
string is in data segment MOV AX, 1000h
CX contains the count of MOV DS,AX
operation ; initialize data segment and
A single bvte transfer rewires: MOV ES,AX

MOV CX, 10
; load leagth of string to CX
; as counter
REP MOVSB
; Decrement CX and
; MOVSB until
; CX =o
; after move SI will be one
; greater than offset of last
; byte in source string, DI
; will be one greater than
; offset of last destination
; string. CX will be equal
:to zero.
CMPSICMPSBI It compares two string bytes or MOV c x , 1 0
, CMPSW words. The source string and the MOV S1,OFFSET SRC-STR
i destination strings should be ; offset of source
present in data segment and the ; string in SI
extra segment respectively. SI and MOV DI, OFFSET DES-STR
DI are used as in the previous ; offset of destination
instruction. CX is used if more ; string in DI
than one bytes or words are to be REPE CMPSB
compared, however for such a case ; Repeat the comparison of
appropriate repeating prefix like ; string bytes until
REP, PEPE etc. need to be used. ; end of string or until
;compared bytes are not
I ;equal.
It scans a string. Compare a string ( MOV AL, ODh
byte with byte in AL or a string ; Byte to be scanned
word with a word in AX. The ; for in AL
instruction does not change the MOV D1,OFFSET DES-STR
operands in AL (AX) or the MOV CX,lO
operand in the string. The string to REPNE SCAS DES-STR
be scanned must be present in the ; Compare byte inDES-STR
extra segment, and the offset of the ; with byte in A .register
string must be contained in the DI ( ;Scanning is repeated while ; 1
register. You can use CX if the bytes are not equal and ;
operation is to be repeated using it is not end of string. If a
REP prefixes. .; carriage return ODh is
;found, ZF = DI will point ;
Assembly Language
Programming at the next byte after the
; carriage return. If a
; carriage return is not
; found then, ZF = 0 and
; CX = 0. SCASB or
; SCASW can be used to
;explicitly state whether
; the byte comparison or the ;
word comparison is
; required.
LODS/LODSB/ It loads string byte into AL or a MOV S1,OFFSET SRC-STR
LODSW string word into AX. The string LODS SRC-STR
byte is assurr,ed to be pointed to by ; LODSB or LODSW can
SI register. ~ f t e the
r load, the SI ;be used to indicate to the
pointer is automatically adjusted to ; assembler, explicitly,
point to the next byte or word as ; whether it is the byte that
the case may be. This instruction ; is required to be loadedbi
does not affect any flag. :the word. I
STOSISTOSBI It stores byte fiom AL or word
STOSW fiom AX into the string present in
the extra segment with offset given
by DI. After the copy, DI is
automatically adjusted to point to
the next byte or word as per the
instruction. No flags are affected.

1.5.6 Processor Control Instructions rn

The objectives of these instructions are to control the processor. This raises two
questions:
1
How can you control processor, as this is the job of control unit?
How much control of processor is actually allowed?

Well, 8086 only allows you to control certain control flags that causes the processing
in a certain direction, processor synchronization if more than one processors are
attached through LOCK instruction for buses etc.

Note: Please note that these instructions may not be very clear to you right now. Thus,
some of these instructions have been discussed in more detail in later units. You must I
MNEMONIC DESCRIPTION EXAMPLE
STC It sets cany flag to 1.
CLC It clears the carry flag to 0..
CMC It complements the state of the CMC; Invert the carry flag
canyflagfiomoto 1 or 1 t o o a s '
the case may be.
STD It sets the direction flag to 1. The
string instruction moves either
forward (increment SI, DI) or
backward (decrement SI, DI)
based on this flag value. STD
ins&ction does not affect any
other flag. The set direction flag
causes stings to move fiom right
to left.
CLD This is opposite to STD, the string CLD
 2
t
Microprocessor
operation occurs in the reverse ;Clear the direction flag Architecture
direction: ;so that the string pointers
;auto-increment.
MOV AX, 1000h
MOV DS, AX
;Initialize data segment
;and extra segment
MOV ES, AX
i MOV SI, 20h
;Load offset of start of
;source string to SI
MOV DI,30h
;Load offset of start of
;destination string to DI
MOV CX,10
;Load length of string to
;CX as counter
REP MOVSB
;Decrement CX and
; increment
;SI and DI to point to next
;byte, then MOVSB until
;CX=O

There are many process control instructions other than these; you may please refer to
further reading for such instructions. These instructions include instructions for setting
and closing interrupt flag, halting the computer, LOCK (locking the bus), NOP etc.

1.6 ADDRESSING MODES

The basic set of operands in 8086 may reside in register, memory and immediate
operand. How can these operands be accessed through various addressing modes? The
answer to the question above is given in the following sub-section. Large number of
addressing modes help in addressing complex data structures with ease. Some specific
Terms and registers roles for addressing:
Base register (BX, BP): These registers are used for pointing to base of an array, stack

Index register (SI, DI): These registers are used as index registers in data andlor extra

Displacement: It represents offset from the segment address.

Addressing modes of 8086

Description
Effective address is the
displacement of memory
variable.
Effective address is the
contents of a register.

of a base register and a

displacement.
- 1
of an index register and a [LIST +Dl]--
displacement. [DI + 21
-
Based Indexed [BX + SI] 29
 Effective address is the sum [BX][DI]
of a base and an index [BP + Dl]
register.
Based Indexed with Effective address is the sum [BX + SI + 21
displacement of a base register, an index
register, and a displacement.
.
1.6.1 Register Addressing Mode
Operand can be a 16-bit register:

Addressing Mode Description Example

AX, BX, CX, DX, SI, In general, the register MOV AL,CH
DI,BP,IP,CS ,DS,ES,SS addressing mode is the most MOV AX,CX
Or it may be AH, AL, BH, BL, efficient because registers are
CH, CL, DH, DL within the CPU and do not
require memory access.

1.6.2 Immediate Addressing Mode

An immediate operand can be a constant expression, such as a number, a character, or
an arithmetic expression. The only constraint is that the assembler must be able to
determine the value of an immediate operand at assembly time. The value is directly
inserted into the machine instruction.
MOV AL,05
Mode Description Example
Immediate Please note in the last MOV AL, 10
examples the expression (2 MOV AL,'A'
+ 3)/5, is evaluated at MOV AX,'ABt
assembly time. MOV AX, 64000
MOV AL, (2 + 3)/5

Mode Description Example

DIRECT The direct operands are also MOV COUNT, CL
called as relocatable operands ;move CL to COUNT (a
as they represent the offset of ;byte variable)
a label fiom the beginning of a MOV AL,COUNT
segment. On reloading a ;move COUNT to AL
program even in a differ& JMP LABEL1
segment will not cause change ;jump to LABEL1
in the offset that is why we MOV AX,DS:5
call them relocatable. Please ;segment register and
note that a variable is ; offset
considered in Data segment MOV BX,CSEG:ZCh
(DS) and code label in code ;segment name and offset
segment (SS) by default. Thus, MOV AX,ES:COUNT
in the example, COUNT, by ; segment register and
;variable.
 1
Microprocessor
default will be assumed to be ' ; The offsets of these Architecture
ln data segment, while LABEL ; variables are calculated
1 , will be assumed to be in ; with respect to the
code segment. If we ssecify, ; segment name (register)
as a direct operand then the ;specified in the .
address is non-relocatable. ; instruction.
Please note the value of
segment register will be
known only at the run time.

1.6.4 Indirect Addressing Mode 1

In indirect addressing modes, operands use registers to point to locations in memory,
So it is actually a register indirect addressing mode. This is a usehl mode for handling
strings/ arrays etc. For this mode two types of registers are used. These are:
Base register BX, BP
Index register SI, DI

BX contain offset/ pointer in Data Segment

BP contains offset/ pointer in Stack segment.
-SI contains offsetlpointer in Data segment.
DI contains offset /pointer in extra data segment.

There are five different types of indirect addressing modes:

1. Register indirect
2. Based indirect
3. Indexed indirect
4. Based indexed
5. Based indexed with displacement.

- Mode Description Example

Register Indirect operands are MOV BX, OFFSET ARRAY
indirect particularly powerful when ; point to start of array
processing list of arrays, MOV AL,[BX]
because a base or an index ; get first element
register may be modified at INC BX
runtime. ; point to next
MOV DL,[BX]
; get second element
The brackets around BX'signify
that we are referring to the contents
of memory location, using the
address stored in BX.
In the following example, three
bytes in an array are added together:
MOV S1,OFFSET ARRAY
; address of first byte
MOV AL,[SI] *
;move the first byte to AL
Assembly Language --
Programming Based and indirect addressing ; Register added to an offset
and Indexed modes are used in the same MOV DX, ARRAY[BX]
Indirect manner. The contents of a MOV DX,[DI + ARRAY]
register are added to a MOV DX,[ARRAY + SI]
displacement to generate an ;Register added to a constant
effective address. The register MOV AX,[BP + 21
must be one of the following: M W DL,[DI - 21 ; DI + (-2)
SI, DI, BX or BP. If the MOV DX,2[SI]
registers used for
displacement are base
registers, BX or BP, it is said
to be base addressing or else
it is called indexed
addressing. A displacemcnt is
either a number or a 1abt.i
whose offset is known at
assembly time. The notation
may take several equivalent
forms. If BX, SI or DI is
used, the effective address is
usually an offset froin the DS
register; BP on the other
hand, usually contains an
offset from the SS reeister.
-
Mode Description Example- --. -- --
Based Indexed In this type of ad Iressing the MOV AL,[BP] [SI]
operand's effective address is MOV DX,[BX SI] 1

formed by combining a base ADD CX,[DII [BX]

register with an index register. ; Two base registers or t\vo
; index registers cannot be
;combined, so the
; following would be
; incorrect:
MOV DL,[BP + BX]
;error : two base registers
MOV AX,[SI + DI]
;error : two index registers
The operand's effective 1 MOV DX,ARRA?CB?(][S~]
Displacement address is formed by I MOV AX, [RX + SI t
I
combining a base register, an ARRAY]
I
index register, and a ADD DL,[BX + SI + 31
displacement. SUB CX, ARRAY [BP +
SII
Two base registers or two
index registers cannot be
combined, so the
following would be
incorrect:
MOV AX,[BP + BX + 21
MOV DX,ARRAY [SI +

Check Your Progress 3

State True or False.

1. CALL instruction should be followed by a RET instruction.
 I
t
2. Conditional jump instructions require one of the flags to be tested. Microprocessor
Architecture

3. REP is an instruction prefix that causes execution of an instruction until CX value

become 0.

4. In the instruction MOV BX, DX register addressing mode has been used.
0
fi. In the instruction MOV BX,ES:COUNTER the second operand is a direct
o~erand. I 7
I. In the instruction ADD CX, [DI] [BX] the second operand is a based index /

operand, whose effective address is obtained by adding the contents of Dl and BX

registers.

7. The instruction ADD AX,ARRAY [bP+ SI] is incorrect.

i 1.7 SUMMARY
.
In this unit, we have studied one of the most popular series of microprocessors, viz.,
Intel 8086. It serves as a base to all its successors,. 8088, 80186, 80286,80486, and
Pentium. The successors of 8086 can be directly run on any successors. Therefore,
though, 8086 has become obsolete from the market point of view, it is still needed to
understand advanced microprocessors.

To summarize the features of 8086, we can say 8086 has:

- a 16-bit data bus
I
- a 20-bit address bus
- CPU is divided into Bus Interface Unit and Execution Unit
- 6-byte instruction prefetch queue
- segmented memory
- 4 general purpose registers (each of 16 bits)
- instruction pointer and a stack pointer
- set of index registers
- powerful instructien set
- powerful addressing modes
- designed for multiprocessor environment
- available in versions of 5Mhz and 8Mhz clock speed.
You can refer to further readings for obtaining more details on INTEL and Motorola
series of microprocessors.

1.8 SOLUTIONSIANSWERS
1 Check Your Progress 1
1. It improves execution efficiency by storing the next instruction in the register
queue.

2. a) 0100 x 10h ( - 16 in decimal) + 0020h

= 01OOOh + 0020h
= 01020h
Assembly Language
Programming

3. a) False b) True c) True d) False

Check Your Progress 2

1. (a) PUSHF instructions do not take any operand.
(b) No error.
(c) XCHG instruction cannot have two memory operands
(d) AAA instruction performs ASCII adjust after addition. It is used after an
ASCII Add. It does not have any operands.
(e) IDIV assumes one operand in AX so only second operand is needed to be
specified.

2. (a) False
(b) False
(c) True
(d) False
(e) False

Check Your Progress 3

1. False
2. True
3. T N ~
4. True
5. True
6. True
7. False