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SCR Report

The document is an assignment from the Department of Electronics and Telecommunication Engineering at Dayananda Sagar College of Engineering. It provides details on simulating various digital circuits using Multisim, including a full adder, full subtractor, binary to gray code converter, 2-bit comparator, and 4:1 multiplexer. The document includes circuit diagrams, truth tables, and test cases for each circuit. It is submitted by student Samhita Bhat for the course Digital System Design Using Verilog.

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0% found this document useful (0 votes)
60 views20 pages

SCR Report

The document is an assignment from the Department of Electronics and Telecommunication Engineering at Dayananda Sagar College of Engineering. It provides details on simulating various digital circuits using Multisim, including a full adder, full subtractor, binary to gray code converter, 2-bit comparator, and 4:1 multiplexer. The document includes circuit diagrams, truth tables, and test cases for each circuit. It is submitted by student Samhita Bhat for the course Digital System Design Using Verilog.

Uploaded by

ShivA 10
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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DIGITAL SYSTEM DESIGN USING VERILOG 2022-2023

Dayananda Sagar College of Engineering


Department of Electronics and Telecommunication
Engineering
2022-23

Assignment on:
Simulating circuits using Multisim

3rd Sem ‘B’ Section


Course Name: Digital System Design Using Verilog
Course Code: 21ET32
Faculty Name: Mrs. Deepthi Raj

Submission date: 15-03-2023


Submitted by: Samhita Bhat - 1DS21ET071

DEPARTMENT OF E&TC, DSCE 1


DIGITAL SYSTEM DESIGN USING VERILOG 2022-2023

1. Full adder using Basic Gates

Full Adder is the adder that adds three inputs and produces two outputs. The first two inputs
are A and B and the third input is an input carry as C-IN. The output carry is designated as C-
OUT and the normal output is designated as S which is SUM. A full adder logic is designed in
such a manner that can take eight inputs together to create a byte-wide adder and cascade the
carry bit from one adder to another. we use a full adder because when a carry-in bit is available,
another 1-bit adder must be used since a 1-bit half-adder does not take a carry-in bit. A 1-bit
full adder adds three operands and generates 2-bit results.

CIRCUIT DIAGRAM

Your text here 1

TRUTH TABLE

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DIGITAL SYSTEM DESIGN USING VERILOG 2022-2023

BOOLEAN EXPRESSION
1) Sum=∑ ( 1,2,4,7)

2) Cout= ∑ ( 3,5,6,7)

CASES

Case 1: A=0; B=0; Cin=0 Case 2: A=0; B=0; Cin=1

Case 3: A=0; B=1; Cin=0 Case 4: A=0; B=1; Cin=1

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DIGITAL SYSTEM DESIGN USING VERILOG 2022-2023

Case 5: A=1; B=0; Cin=0 Case 6: A=1; B=0; Cin=1

Case 7: A=1; B=1; Cin=0 Case 8: A=1; B=1; Cin=1

DEPARTMENT OF E&TC, DSCE 4


DIGITAL SYSTEM DESIGN USING VERILOG 2022-2023

2. Full Subtractor using Basic Gates

Full Adder is the adder that adds three inputs and produces two outputs. The first two inputs are A
and B and the third input is an input carry as C-IN. The output carry is designated as C-OUT and
the normal output is designated as S which is SUM. A full adder logic is designed in such a manner
that can take eight inputs together to create a byte-wide adder and cascade the carry bit from one
adder to another. we use a full adder because when a carry-in bit is available, another 1-bit adder
must be used since a 1-bit half-adder does not take a carry-in bit. A 1-bit full adder adds three
operands and generates 2-bit results.

CIRCUIT DIAGRAM

TRUTH TABLE

DEPARTMENT OF E&TC, DSCE 5


DIGITAL SYSTEM DESIGN USING VERILOG 2022-2023

BOOLEAN EXPRESSION
1) Difference= ∑ ( 1,2,4,7)

2) Bout = ∑ ( 1,2,3,7)

CASES

Case 1: A=0, B=0, Bin=0 Case 2: A=0, B=0, Bin=1

Case 3: A=0, B=1, Bin=0 Case 4: A=0, B=1, Bin=1

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DIGITAL SYSTEM DESIGN USING VERILOG 2022-2023

Case 5: A=1, B=0, Bin=0 Case 6: A=1, B=0, Bin=1

Case 7: A=1, B=1, Bin=0 Case 8: A=1, B=1, Bin=1

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DIGITAL SYSTEM DESIGN USING VERILOG 2022-2023

3. Binary to Grey conversion using NAND gates

This is another binary code that finds application in input/output devices, shaft position encoders,
and several analog-to-digital converters. This is an unweighted code. The gray code exhibits only
a single-bit change from one code number to the next. A code converter is a combinational circuit
that translates the input code word into a new corresponding word. The excess-3 code digit is
obtained by adding three to the corresponding BCD digit. To Construct a BCD-to-excess-3-code
converter with a 4-bit adder feed BCD code to the 4-bit adder as the first operand and then feed
constant 3 as the second operand. The output is the corresponding excess-3 code. To make it work
as an excess-3 to BCD converter, we feed excess-3 code as the first operand and then feed 2's
complement of 3 as the second operand. The output is the BCD code.

CIRCUIT DIAGRAM

TRUTH TABLE

DEPARTMENT OF E&TC, DSCE 8


DIGITAL SYSTEM DESIGN USING VERILOG 2022-2023

BOOLEAN EXPRESSION
1) G3=∑ (8,9,10,11,12,13,14,15)

2) G2=∑ (4,5,6,7,8,9,10,11)

3) G1=∑ (2,3,4,5,10,11,12,13)

4) G0=∑ (1,2,5,6,9,10,13,14)

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DIGITAL SYSTEM DESIGN USING VERILOG 2022-2023

CASES
Case 1: B0=0; B1=0; B2=0; B3=0 Case 2: B0=0; B1=0; B2=0; B3=1

Case 3: B0=0; B1=0; B2=1; B3=0 Case 4: B0=0; B1=0; B2=1; B3=1

Case 5: B0=0; B1=1; B2=0; B3=0 Case 6: B0=0; B1=1; B2=0; B3=1

Case 7: B0=0; B1=1; B2=1; B3=0 Case 8: B0=1; B1=1; B2=1; B3=1

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DIGITAL SYSTEM DESIGN USING VERILOG 2022-2023

Case 9: B0=1; B1=0; B2=0; B3=0 Case 10: B0=1; B1=0; B2=0; B3=1

Case 11: B0=1; B1=0; B2=1; B3=0 Case 12: B0=1; B1=0; B2=1; B3=1

Case 13: B0=1; B1=1; B2=0; B3=0 Case 14: B0=1; B1=1; B2=0; B3=1

Case 15: B0=1; B1=1; B2=1; B3=0 Case 16: B0=1; B1=1; B2=1; B3=1

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DIGITAL SYSTEM DESIGN USING VERILOG 2022-2023

4. 2-bit Comparator
Magnitude Comparator is a logical circuit, which compares two signals A and B, and generates three
logical outputs, whether A > B, A = B, or A < B. IC 7485 is a high-speed 4-bit Magnitude
comparator, which compares two 4-bit words. The A = B Input must be held high for proper compare
operation. The Magnitude Comparator is a combinational circuit that compares two numbers A &
B and determines their relative magnitudes. The outcome of the comparison is specified by three
binary variables that indicate whether A>B, A=B, or A<B.

CIRCUIT DIAGRAM

TRUTH TABLE

DEPARTMENT OF E&TC, DSCE 12


DIGITAL SYSTEM DESIGN USING VERILOG 2022-2023

BOOLEAN EXPRESSIONS
1) A gt B =∑ (4,8,9,12,13,14)

2) A eq B =∑ (0,5,10,15)

3)

4) A lt B =∑ (1,2,3,6,7,11)

CASES
Case 1: A1=0, A0=0, B1=0, B0=0 Case 2: A1=0, A0=0, B1=0, B0=1

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DIGITAL SYSTEM DESIGN USING VERILOG 2022-2023

Case 3: A1=0, A0=0, B1=1, B0=0 Case 4: A1=0, A0=0, B1=1, B0=1

Case 5: A1=0, A0=1, B1=0, B0=0 Case 6: A1=0, A0=1, B1=0, B0=1

Case 7: A1=0, A0=1, B1=1, B0=0 Case 8: A1=0, A0=1, B1=1, B0=1

Case 9: A1=1, A0=0, B1=0, B0=0 Case 10: A1=1, A0=0, B1=0, B0=1

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DIGITAL SYSTEM DESIGN USING VERILOG 2022-2023

Case 11: A1=1, A0=0, B1=1, B0=0 Case 12: A1=1, A0=0, B1=1, B0=1

Case 13: A1=1, A0=1, B1=0, B0=0 Case 14: A1=1, A0=1, B1=0, B0=1

Case 15: A1=1, A0=1, B1=1, B0=0 Case 16: A1=1, A0=1, B1=1, B0=1

DEPARTMENT OF E&TC, DSCE 15


DIGITAL SYSTEM DESIGN USING VERILOG 2022-2023

5. 4:1 Multiplexer using NAND gates

Multiplexers are very useful components in digital systems. They transfer a large number of
information units over a smaller number of channels, (usually one channel) under the control of
selection signals. Multiplexer means many to one. A multiplexer is a circuit with many Inputs but
only one output. By using control signals (select lines) we can select any input to the output.
Multiplexer is also called a data selector because the output bit depends on the input data bit that is
selected. Multiplexer is a digital switch. It allows digital information from several sources to be
routed onto a single output line. There are 2n input lines and n selection lines whose bit combinations
determine which input is selected. Therefore, multiplexer is a ‘many into one’. Multiplexer finds
applications like Parallel to Serial conversion, Data routing, Operation Sequencing, and Logic
function generation.

CIRCUIT DIAGRAM

TRUTH TABLE

DEPARTMENT OF E&TC, DSCE 16


DIGITAL SYSTEM DESIGN USING VERILOG 2022-2023

BOOLEAN EXPRESSION

CASES

Case 1: S1=0; S0=0; E=0; I0=0; I1=X; I2=X; I3=X

Case 2: S1=0; S0=0; E=0; I0=1; I1=X; I2=X; I3=X

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DIGITAL SYSTEM DESIGN USING VERILOG 2022-2023

Case 3: S1=0; S0=1; E=0; I0=X; I1=0; I2=X; I3=X

Case 4: S1=0; S0=1; E=0; I0=X; I1=1; I2=X; I3=X

Case 5: S1=1; S0=0; E=0; I0=X; I1=X; I2=0; I3=X

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DIGITAL SYSTEM DESIGN USING VERILOG 2022-2023

Case 6: S1=1; S0=0; E=0; I0=X; I1=X; I2=1; I3=X

Case 7: S1=1; S0=1; E=0; I0=X; I1=X; I2=X; I3=0

Case 8: S1=1; S0=1; E=0; I0=X; I1=X; I2=X; I3=1

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DIGITAL SYSTEM DESIGN USING VERILOG 2022-2023

DEPARTMENT OF E&TC, DSCE 20

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