DE09 DIGITALS ELECTRONICS

TYPICAL QUESTIONS & ANSWERS

PART - I

OBJECTIVE TYPE QUESTIONS

Each Question carries 2 marks.

Choose correct or the best alternative in the following:

Q.1 The NAND gate output will be low if the two inputs are
(A) 00 (B) 01
(C) 10 (D) 11

Ans: D
The NAND gate output will be low if the two inputs are 11
(The Truth Table of NAND gate is shown in Table.1.1)
X(Input) Y(Input) F(Output)

0 0 1

0 1 1

1 0 1

1 1 0

Table 1.1 Truth Table for NAND Gate

Q.2 What is the binary equivalent of the decimal number 368

(A) 101110000 (B) 110110000 (C) 111010000 (D) 111100000
Ans: A
The Binary equivalent of the Decimal number 368 is 101110000
(Conversion from Decimal number to Binary number is given in Table 1.2)

2 368
2 184 --- 0
2 92 --- 0
2 46 --- 0
2 23 --- 0
2 11 --- 1
2 5 --- 1
2 2 --- 1
2 1 --- 0
0 --- 1
Table 1.2 Conversion from Decimal number to Binary number
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Q.3 The decimal equivalent of hex number 1A53 is

(A) 6793 (B) 6739
(C) 6973 (D) 6379

Ans: B
The decimal equivalent of Hex Number 1A53 is 6739
(Conversion from Hex Number to Decimal Number is given below)
1 A 5 3 Hexadecimal
16³ 16² 16¹ 16° Weights

(1A53)16 = (1X16³) + (10 X 16²) + (5 X 16¹) + (3 X 16º)

= 4096 + 2560 + 80 + 3
= 6739

Q.4 ( ) ( ) 8 16 734 =
(A) C 1 D (B) D C 1
(C) 1 C D (D) 1 D C

Ans: D
(734)8 = (1 D C)16
0001 │ 1101 │ 1100
1DC

Q.5 The simplification of the Boolean expression (ABC)+ (ABC) is

(A) 0 (B) 1
(C) A (D) BC

Ans: B
The Boolean expression is (ABC)+ (ABC) is equivalent to 1
(ABC)+ (ABC) = A + B +C + A + B +C = A + B + C + A + B + C
= (A+ A )(B+ B )(C+C ) = 1X1X1 = 1

Q.6 The number of control lines for a 8 – to – 1 multiplexer is

(A) 2 (B) 3
(C) 4 (D) 5

Ans: B
The number of control lines for an 8 to 1 Multiplexer is 3 (The control signals are used
to steer any one of the 8 inputs to the output)

Q.7 How many Flip-Flops are required for mod–16 counter?

(A) 5 (B) 6
 (C) 3 (D) 4

Ans: D
The number of flip-flops is required for Mod-16 Counter is 4.

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(For Mod-m Counter, we need N flip-flops where N is chosen to be the smallest number
for which 2N is greater than or equal to m. In this case 24 greater than or equal to 1)

Q.8 EPROM contents can be erased by exposing it to

(A) Ultraviolet rays. (B) Infrared rays.
(C) Burst of microwaves. (D) Intense heat radiations.

Ans: A
EPROM contents can be erased by exposing it to Ultraviolet rays
(The Ultraviolet light passes through a window in the IC package to the EPROM chip
where it releases stored charges. Thus the stored contents are erased).

Q.9 The hexadecimal number ‘A0’ has the decimal value equivalent to
(A) 80 (B) 256
(C) 100 (D) 160

Ans: D
The hexadecimal number ‘A0’ has the decimal value equivalent to 160
(A0
161 160 = 10X161 + 0X160 = 160)

Q.10 The Gray code for decimal number 6 is equivalent to

(A) 1100 (B) 1001
(C) 0101 (D) 0110

Ans: C
The Gray code for decimal number 6 is equivalent to 0101
(Decimal number 6 is equivalent to binary number 0110)

+++
0110

0101

Q.11 The Boolean expression A.B+ A.B+ A.B is equivalent to

(A) A + B (B) A.B
(C) A + B (D) A.B

Ans: A
The Boolean expression A .B + A. B + A.B is equivalent to A + B ( A .B + A. B + A.B =
B( A + A ) + A. B
= B + A. B {Q( A + A ) = 1}
= A + B {Q(B + A. B ) = B + A}

Q.12 The digital logic family which has minimum power dissipation is

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(A) TTL (B) RTL

(C) DTL (D) CMOS

Ans: D
The digital logic family which has minimum power dissipation is CMOS. (CMOS being an unipolar logic
family, occupy a very small fraction of silicon Chip area)

Q.13 The output of a logic gate is 1 when all its inputs are at logic 0. the gate is either
(A) a NAND or an EX-OR (B) an OR or an EX-NOR
(C) an AND or an EX-OR (D) a NOR or an EX-NOR

Ans: D
The output of a logic gate is 1 when all inputs are at logic 0. The gate is either a NOR or an
EX-NOR .
(The truth tables for NOR and EX-NOR Gates are shown in fig.1(a) & 1(b).)

Input Output Input Output

AB Y AB Y

00 1
00 1
01 0
01 0
10 0
10 0
11 1
11 0

Fig.1(a) Truth Table for NOR Gate Fig.1(b) Truth Table for EX-NOR Gate

Q.14 Data can be changed from special code to temporal code by using
(A) Shift registers (B) counters
(C) Combinational circuits (D) A/D converters.

Ans: A
Data can be changed from special code to temporal code by using Shift Registers.
(A Register in which data gets shifted towards left or right when clock pulses are applied
is known as a Shift Register.)

Q.15 A ring counter consisting of five Flip-Flops will have

(A) 5 states (B) 10 states
(C) 32 states (D) Infinite states.
 Ans: A
A ring counter consisting of Five Flip-Flops will have 5 states.

Q.16 The speed of conversion is maximum in

(A) Successive-approximation A/D converter.
(B) Parallel-comparative A/D converter.
(C) Counter ramp A/D converter.
(D) Dual-slope A/D converter.

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Ans: B
The speed of conversion is maximum in Parallel-comparator A/D converter
(Speed of conversion is maximum because the comparisons of the input voltage are
carried out simultaneously.)

Q.17 The 2’s complement of the number 1101101 is

(A) 0101110 (B) 0111110
(C) 0110010 (D) 0010011

Ans: D
The 2’s complement of the number 1101101 is 0010011
(1’s complement of the number 1101101 is 0010010
2’s complement of the number 1101101is 0010010 + 1 =0010011)

Q.18 The correction to be applied in decimal adder to the generated sum is

(A) 00101 (B) 00110
(C) 01101 (D) 01010

Ans: B
The correction to be applied in decimal adder to the generated sum is 00110. When the four bit sum is
more than 9 then the sum is invalid. In such cases, add +6(i.e. 0110) to the four bit sum to skip the six
invalid states. If a carry is generated when adding 6, add the carry to the next four bit group .

Q.19 When simplified with Boolean Algebra (x + y)(x + z) simplifies to

(A) x (B) x + x(y + z)
(C) x(1 + yz) (D) x + yz

Ans: D
When simplified with Boolean Algebra (x + y)(x + z) simplifies to x + yz [(x +
Q
y) (x + z)] = xx + xz + xy + yz = x + xz + xy + yz ( xx = x) = x(1+z) + xy + yz = x +
Q Q
xy + yz { (1+z) = 1} = x(1 + y) + yz = x + yz { (1+y) = 1}]

Q.20 The gates required to build a half adder are

(A) EX-OR gate and NOR gate (B) EX-OR gate and OR gate (C) EX-OR
gate and AND gate (D) Four NAND gates.
 Ans: C
The gates required to build a half adder are EX-OR gate and AND gate Fig.1(d)
shows the logic diagram of half adder.
C
A
B

Fig.1(d) Logic diagram of Half Adder

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Q.21 The code where all successive numbers differ from their preceding number by single bit is
(A) Binary code. (B) BCD.
(C) Excess – 3. (D) Gray.

Ans: D
The code where all successive numbers differ from their preceding number by single bit is Gray Code.
(It is an unweighted code. The most important characteristic of this code is that only a
single bit change occurs when going from one code number to next.)

Q.22 Which of the following is the fastest logic

(A) TTL (B) ECL
(C) CMOS (D) LSI

Ans: B
ECL is the fastest logic family of all logic families.
(High speeds are possible in ECL because the transistors are used in difference amplifier
configuration, in which they are never driven into saturation and thereby the storage
time is eliminated.

Q.23 If the input to T-flipflop is 100 Hz signal, the final output of the three T-flipflops in cascade is (A)
1000 Hz (B) 500 Hz
(C) 333 Hz (D) 12.5 Hz.

Ans: D
If the input to T-flip-flop is 100 Hz signal, the final output of the three T flip-flops in
cascade is 12.5 Hz
{The final output of the three T-flip-flops in cascade is
Frequency
100
=12.5Hz}

2= 3
(T) = N 2

Q.24 Which of the memory is volatile memory

(A) ROM (B) RAM
(C) PROM (D) EEPROM

Ans: B
RAM is a volatile memory
(Volatile memory means the contents of the RAM get erased as soon as the power goes off.)

Q.25 -8 is equal to signed binary number

(A) 10001000 (B) 00001000
(C) 10000000 (D) 11000000

Ans: A
- 8 is equal to signed binary number 10001000

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(To represent negative numbers in the binary system, Digit 0 is used for the positive sign
and 1 for the negative sign. The MSB is the sign bit followed by the magnitude bits. i.e.,
- 8 = 1000 1000
-
------- -----------------
Sign Magnitude
------- ---------------

Q.26 DeMorgan’s first theorem shows the equivalence of

(A) OR gate and Exclusive OR gate.
(B) NOR gate and Bubbled AND gate.
(C) NOR gate and NAND gate.
(D) NAND gate and NOT gate

Ans: B
DeMorgan’s first theorem shows the equivalence of NOR gate and Bubbled AND gate (Logic
diagrams for De Morgan’s First Theorem is shown in fig.1(a)

Y
A

BY
B

Fig.1(a) Logic Diagrams for De Morgan’s First Theorem

Q.27 The digital logic family which has the lowest propagation delay time is
(A) ECL (B) TTL
(C) CMOS (D) PMOS

Ans: A
The digital logic family which has the lowest propagation delay time is ECL (Lowest propagation
delay time is possible in ECL because the transistors are used in difference amplifier
configuration, in which they are never driven into saturation and thereby the storage time is
 eliminated).

Q.28 The device which changes from serial data to parallel data is
(A) COUNTER (B) MULTIPLEXER
(C) DEMULTIPLEXER (D) FLIP-FLOP

Ans: C
The device which changes from serial data to parallel data is demultiplexer. (A demultiplexer takes
in data from one line and directs it to any of its N outputs depending on the status of the select
inputs.)

Q.29 A device which converts BCD to Seven Segment is called

(A) Encoder (B) Decoder
(C) Multiplexer (D) Demultiplexer

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Ans: B
A device which converts BCD to Seven Segment is called DECODER. (A decoder coverts
binary words into alphanumeric characters.)

Q.30 In a JK Flip-Flop, toggle means

(A) Set Q = 1 and Q = 0.
(B) Set Q = 0 and Q = 1.
(C) Change the output to the opposite state.
(D) No change in output.

Ans: C
In a JK Flip-Flop, toggle means Change the output to the opposite state.
Q.31 The access time of ROM using bipolar transistors is about
(A) 1 sec (B) 1 msec
(C) 1 µsec (D) 1 nsec.

Ans: C
The access time of ROM using bipolar transistors is about 1 ∝ sec.

Q.32 The A/D converter whose conversion time is independent of the number of bits is (A) Dual
slope (B) Counter type
(C) Parallel conversion (D) Successive approximation.

Ans: C
The A/D converter whose conversion time is independent of the Number of bits is Parallel
conversion.
(This type uses an array of comparators connected in parallel and comparators compare the input
voltage at a particular ratio of the reference voltage).

Q.33 When signed numbers are used in binary arithmetic, then which one of the following
notations would have unique representation for zero.
 (A) Sign-magnitude. (B) 1’s complement.
(C) 2’s complement. (D) 9’s complement.
Ans: A

Q.34 The logic circuit given below (Fig.1) converts a binary code 1 2 3
y into y y

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(A) Excess-3 code. (B) Gray code.

(C) BCD code. (D) Hamming code.

Ans: B
Gray code as
X1=Y1, X2=Y1 XOR Y2 , X3=Y1 XOR Y2 XOR Y3
For Y1 Y2 Y3 X1 X2 X3
000000
001001
010011
011010

Q.35 The logic circuit shown in the given fig.2 can be minimised to

(A) (B)

(C) (D)
Ans: D
As output of the logic circuit is
Y=(X+Y’)’+(X’+(X+Y’)’)’
(X+Y’)’=X’Y Using DE Morgan’s
Now this is one of input of 2nd gate.
F=(A+X’)’=A’X=[(X’Y)’.X]
=[(X+Y’)X]=X+XY’=X(Y’)
=X

Q.36 In digital ICs, Schottky transistors are preferred over normal transistors because of their
(A) Lower Propagation delay. (B) Higher Propagation delay. (C) Lower Power dissipation. (D)
Higher Power dissipation.

Ans: A
Lower propagation delay as shottky transistors reduce the storage time delay by
preventing the transistor from going deep into saturation.

Q.37 The following switching functions are to be implemented using a Decoder: f

= = ( 7 6, 5, 4, 2, ) =
m( 8, 4, 2, 1, 10,14 ) 1 ∑ f ( 11 9, 5, 2, ) 2 ∑ mf 3 ∑m

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The minimum configuration of the decoder should be

(A) 2 – to – 4 line. (B) 3 – to – 8 line.
(C) 4 – to – 16 line. (D) 5 – to – 32 line.
Ans: C
4 to 16 line decoder as the minterms are ranging from 1 to 14.

Q.38 A 4-bit synchronous counter uses flip-flops with propagation delay times of 15 ns each. The
maximum possible time required for change of state will be
(A) 15 ns. (B) 30 ns.
(C) 45 ns. (D) 60 ns.
Ans: A
15 ns because in synchronous counter all the flip-flops change state at the same time.

Q.39 Words having 8-bits are to be stored into computer memory. The number of lines required for
writing into memory are
(A) 1. (B) 2.
(C) 4. (D) 8.

Ans: D
Because 8-bit words required 8 bit data lines.
Q.40 In successive-approximation A/D converter, offset voltage equal to 1
2 LSB is added to the
D/A converter’s output. This is done to
(A) Improve the speed of operation.
 (B) Reduce the maximum quantization error.
(C) Increase the number of bits at the output.
(D) Increase the range of input voltage that can be converted.

Ans: B

Q.41 The decimal equivalent of Binary number 11010 is

(A) 26. (B) 36.
(C) 16. (D) 23.

Ans: A
4 3 2 1
11010 = 1 X 2 + 1 X 2 + 0 X 2 + 1 X 2 = 26

Q.42 1’s complement representation of decimal number of -17 by using 8 bit representation is
(A) 1110 1110 (B) 1101 1101
(C) 1100 1100 (D) 0001 0001

Ans: A
(17) = (10001)
10 2
In 8 bit = 00010001
1's Complement = 11101110

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Q.43 The excess 3 code of decimal number 26 is

(A) 0100 1001 (B) 01011001
(C) 1000 1001 (D) 01001101

Ans: B
(26)
10 in BCD is ( 00100110 ) BCD
Add 011 to each BCD 01011001 for excess – 3

Q.44 How many AND gates are required to realize Y = CD+EF+G

(A) 4 (B) 5
(C) 3 (D) 2

Ans: D
To realize Y = CD + EF + G
Two AND gates are required (for CD & EF).

Q.45 How many select lines will a 16 to 1 multiplexer will have

(A) 4 (B) 3
(C) 5 (D) 1

Ans: A
4
In 16 to 1 MUX four select lines will be required to select 16 ( 2 ) inputs.
Q.46 How many flip flops are required to construct a decade counter
(A) 10 (B) 3
(C) 4 (D) 2

Ans: C
Decade counter counts 10 states from 0 to 9 ( i.e. from 0000 to 1001 )
Thus four FlipFlop's are required.

Q.47 Which TTL logic gate is used for wired ANDing

(A) Open collector output (B) Totem Pole
(C) Tri state output (D) ECL gates

Ans: A
Open collector output.

Q.48 CMOS circuits consume power

(A) Equal to TTL (B) Less than TTL
(C) Twice of TTL (D) Thrice of TTL

Ans: B
As in CMOS one device is ON & one is Always OFF so power consumption is low.

Q.49 In a RAM, information can be stored

(A) By the user, number of times.

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(B) By the user, only once.

(C) By the manufacturer, a number of times.
(D) By the manufacturer only once.

Ans: A
RAM is used by the user, number of times.

Q.50 The hexadecimal number for ( )10 95 is 5.

(A) ( )16 5 8.F (B) ( ) B.A 16 9
(C) ( )16 2 F.E (D) ( )16 5 4.A

Ans: A
(95.5)10 = (5F.8)16
Integer part Fractional part 16 95 0.5x16=8.0 16 5 15

05

Q.51 The octal equivalent of ( )10 247 is

(A) ( )8
 252 (B) ( )8
350
(C) ( )8
367 (D) ( )8
400

Ans: C
(247)10 = (367)8

8 247
8 30 7
836
03

Q.52 The chief reason why digital computers use complemented subtraction is that it
(A) Simplifies the circuitry.
(B) Is a very simple process.
(C) Can handle negative numbers easily.
(D) Avoids direct subtraction.

Ans: C
Using complement method negative numbers can also be subtracted.

Q.53 In a positive logic system, logic state 1 corresponds to

(A) positive voltage (B) higher voltage level (C) zero voltage level (D)
lower voltage level

Ans: B

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We decide two voltages levels for positive digital logic. Higher voltage represents logic 1
& a lower voltage represents logic 0.

Q.54 The commercially available 8-input multiplexer integrated circuit in the TTL family is
(A) 7495. (B) 74153.
(C) 74154. (D) 74151.

Ans: B
MUX integrated circuit in TTL is 74153.

Q.55 CMOS circuits are extensively used for ON-chip computers mainly because of their extremely
(A) low power dissipation. (B) high noise immunity.
(C) large packing density. (D) low cost.

Ans: C
Because CMOS circuits have large packing density.
Q.56 The MSI chip 7474 is
(A) Dual edge triggered JK flip-flop (TTL).
(B) Dual edge triggered D flip-flop (CMOS).
(C) Dual edge triggered D flip-flop (TTL).
(D) Dual edge triggered JK flip-flop (CMOS).

Ans: C
MSI chip 7474 dual edge triggered D Flip-Flop.

Q.57 Which of the following memories stores the most number of bits
(A) a 5M⋅8 memory. (B) a 1M ⋅ 16 memory.
(C) a 5M ⋅ 4 memory. (D) a 1M ⋅12 memory.

Ans: A
5Mx8 = 5 x 220 x 8 = 40M (max)

Q.58 The process of entering data into a ROM is called

(A) burning in the ROM (B) programming the ROM
(C) changing the ROM (D) charging the ROM

Ans: B
The process of entering data into ROM is known as programming the ROM.

Q.59 When the set of input data to an even parity generator is 0111, the output will be
(A) 1 (B) 0
(C) Unpredictable (D) Depends on the previous input

Ans: B
In even parity generator if number of 1 is odd then output will be zero.

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Q.60 The number 140 in octal is equivalent to

(A) ( )10 96 . (B) ( )10 86 .
(C) ( )10 90 . (D) none of these.

Ans: A
(140)8 = (96)10
1 x 82 + 4 x 8 + 0x 1 = 64 + 32 = 96

Q.61 The NOR gate output will be low if the two inputs are
(A) 00 (B) 01
(C) 10 (D) 11

Ans: B, C, or D
O/P is low if any of the I/P is high
Q.62 Which of the following is the fastest logic?
(A) ECL (B) TTL
(C) CMOS (D) LSI

Ans: A

Q.63 How many flip-flops are required to construct mod 30 counter

(A) 5 (B) 6
(C) 4 (D) 8

Ans: A
Mod - 30 counter +/- needs 5 Flip-Flop as 30 < 25
Mod - N counter counts total ' N ' number of states.
To count 'N' distinguished states we need minimum n FlipFlop's as [N = 2n]
For eg. Mod 8 counter requires 3 Flip-Flop's (8 = 23)

Q.64 How many address bits are required to represent a 32 K memory

(A) 10 bits. (B) 12 bits.
(C) 14 bits. (D) 16 bits.

Ans: D
32K = 25 x 210 = 215,
Thus 15 address bits are required, Only 16 bits can address it.

Q.65 The number of control lines for 16 to 1 multiplexer is

(A) 2. (B) 4.
(C) 3. (D) 5.

Ans: B
As 16 = 24, 4 Select lines are required.

Q.66 Which of following requires refreshing?

(A) SRAM. (B) DRAM.
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(C) ROM. (D) EPROM.

Ans: B

Q.67 Shifting a register content to left by one bit position is equivalent to

(A) division by two. (B) addition by two.
(C) multiplication by two. (D) subtraction by two. Ans:C

Q.68 For JK flip flop with J=1, K=0, the output after clock pulse will be
(A) 0. (B) 1.
(C) high impedance. (D) no change.

Ans: B
Q.69 Convert decimal 153 to octal. Equivalent in octal will be
(A) ( )8
231 . (B) ( )8
331 .
(C) ( )8
431 . (D) none of these.

Ans: A
(153)10 = (231)8

8 153 1
8 19 3
822

Q.70 The decimal equivalent of ( )2

1100 is
(A) 12 (B) 16
(C) 18 (D) 20

Ans: A
(1100)2 = (12)10

Q.71 The binary equivalent of ( )16 FA is

(A) 1010 1111 (B) 1111 1010 (C) 10110011 (D) none of these

Ans: B
(FA)16 = (11111010)10

Q.72 The output of SR flip flop when S=1, R=0 is

(A) 1 (B) 0
(C) No change (D) High impedance

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Ans: A
As for the SR flip-flop S=set input R=reset input ,when S=1, R=0, Flip-flop will be set.

Q.73 The number of flip flops contained in IC 7490 is

(A) 2. (B) 3.
(C) 4. (D) 10.

Ans: A

Q.74 The number of control lines for 32 to 1 multiplexer is

 (A) 4. (B) 5.
(C) 16. (D) 6.

Ans: B
The number of control lines for 32 (25) and to select one input among them total 5 select
lines are required.

Q.75 How many two-input AND and OR gates are required to realize Y=CD+EF+G
(A) 2,2. (B) 2,3.
(C) 3,3. (D) none of these.

Ans: A
Y=CD+EF+G
Number of two input AND gates=2
Number of two input OR gates = 2
One OR gate to OR CD and EF and next to OR of G & output of first OR gate.

Q.76 Which of following can not be accessed randomly

(A) DRAM. (B) SRAM.
(C) ROM. (D) Magnetic tape.

Ans: D
Magnetic tape can only be accessed sequentially.

Q.77 The excess-3 code of decimal 7 is represented by

(A) 1100. (B) 1001.
(C) 1011. (D) 1010.

Ans: D
An excess 3 code is always equal to the binary code +3

Q.78 When an input signal A=11001 is applied to a NOT gate serially, its output signal is
(A) 00111. (B) 00110.
(C) 10101. (D) 11001.

Ans: B
As A=11001 is serially applied to a NOT gate, first input applied will be LSB 00110.

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Q.79 The result of adding hexadecimal number A6 to 3A is

(A) DD. (B) E0.
(C) F0. (D) EF.

Ans: B

Q.80 A universal logic gate is one, which can be used to generate any logic function. Which of the
following is a universal logic gate?
 (A) OR (B) AND
(C) XOR (D) NAND

Ans: D
NAND can generate any logic function.

Q.81 The logic 0 level of a CMOS logic device is approximately

(A) 1.2 volts (B) 0.4 volts
(C) 5 volts (D) 0 volts

Ans: D
CMOS logic low level is 0 volts approx.

Q.82 Karnaugh map is used for the purpose of

(A) Reducing the electronic circuits used.
(B) To map the given Boolean logic function.
(C) To minimize the terms in a Boolean expression.
(D) To maximize the terms of a given a Boolean expression.

Ans: C

Q.83 A full adder logic circuit will have

(A) Two inputs and one output.
(B) Three inputs and three outputs.
(C) Two inputs and two outputs.
(D) Three inputs and two outputs.

Ans: D
A full adder circuit will add two bits and it will also accounts the carry input generated in
the previous stage. Thus three inputs and two outputs (Sum and Carry) are there.

Q.84 An eight stage ripple counter uses a flip-flop with propagation delay of 75 nanoseconds. The
pulse width of the strobe is 50ns. The frequency of the input signal which can be used for
proper operation of the counter is approximately
(A) 1 MHz. (B) 500 MHz.
(C) 2 MHz. (D) 4 MHz.

Ans: A

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Maximum time taken for all flip-flops to stabilize is 75ns x 8 + 50 = 650ns. Frequency of
operation must be less than 1/650ns = 1.5 MHz.

Q.85 The output of a JK flipflop with asynchronous preset and clear inputs is ‘1’. The output can be
changed to ‘0’ with one of the following conditions.
(A) By applying J = 0, K = 0 and using a clock.
(B) By applying J = 1, K = 0 and using the clock.
(C) By applying J = 1, K = 1 and using the clock.
 (D) By applying a synchronous preset input.

Ans: C
Preset state of JK Flip-Flop =1
With J=1 K=1 and the clock next state will be complement of the present state.

Q.86 The information in ROM is stored

(A) By the user any number of times.
(B) By the manufacturer during fabrication of the device.
(C) By the user using ultraviolet light.
(D) By the user once and only once.

Ans: B

Q.87 The conversation speed of an analog to digital converter is maximum with the following
technique.
(A) Dual slope AD converter.
(B) Serial comparator AD converter.
(C) Successive approximation AD converter.
(D) Parallel comparator AD converter.

Ans: D

Q.88 A weighted resistor digital to analog converter using N bits requires a total of
(A) N precision resistors. (B) 2N precision resistors.
(C) N + 1 precision resistors. (D) N – 1 precision resistors.

Ans: A

Q.89 The 2’s complement of the number 1101110 is

(A) 0010001. (B) 0010001.
(C) 0010010. (D) None.

Ans: C
1’s complement of 1101110 is = 0010001
Thus 2’s complement of 1101110 is = 0010001 + 1 = 0010010

Q.90 The decimal equivalent of Binary number 10101 is

(A) 21 (B) 31
(C) 26 (D) 28

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DE09 DIGITALS ELECTRONICS

Ans: A
1x24 + 0x23 +1x22 +0x21 + 1x20
= 16 + 0 + 4 + 0 + 1 = 21.

Q.91 How many two input AND gates and two input OR gates are required to realize Y
= BD+CE+AB
(A) 1, 1 (B) 4, 2
(C) 3, 2 (D) 2, 3

Ans: A
There are three product terms, so three AND gates of two inputs are required. As only
two input OR gates are available, so two OR gates are required to get the logical sum of
three product terms.

Q.92 How many select lines will a 32:1 multiplexer will have
(A) 5. (B) 8.
(C) 9. (D) 11.

Ans: A
For 32 inputs, 5 select lines will be required, as 25 = 32.

Q.93 How many address bits are required to represent 4K memory

(A) 5 bits. (B) 12 bits.
(C) 8 bits. (D) 10 bits.

Ans: B
For representing 4K memory, 12 address bits are required as
4K = 22 x 210 = 212 (1K = 1024 = 210)

Q.94 For JK flipflop J = 0, K=1, the output after clock pulse will be
(A) 1. (B) no change.
(C) 0. (D) high impedance.

Ans: C
J=0, K=1, these inputs will reset the flip-flop after the clock pulse. So whatever be the
previous output, the next state will be 0.

Q.95 Which of following are known as universal gates

(A) NAND & NOR. (B) AND & OR.
(C) XOR & OR. (D) None.

Ans: A
NAND & NOR are known as universal gates, because any digital circuit can be realized
completely by using either of these two gates.

Q.96 Which of the following memories stores the most number of bits
(A) 64K ⋅8 memory. (B) 8 1M⋅ memory.

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DE09 DIGITALS ELECTRONICS

(C) 32M ⋅8 memory. (D) 64⋅ 6 memory.

Ans: C
32M x 8 stores most number of bits
25 x 220 = 225 (1M = 220 = 1K x 1K = 210 x 210)
Q.97 Which of following consume minimum power
(A) TTL. (B) CMOS.
(C) DTL. (D) RTL.

Ans: B
CMOS consumes minimum power as in CMOS one p-MOS & one n-MOS transistors are
connected in complimentary mode, such that one device is ON & one is OFF.

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PART – II

NUMERICALS
Q.1 Convert the octal number 7401 to Binary. (4)
Ans:
Conversion of Octal number 7401 to Binary:
Each octal digit represents 3 binary digits. To convert an octal number to binary
number, each octal digit is replaced by its 3 digit binary equivalent shown below.
7401

111 100 000 001

Thus, (7401)8 = (111100000001)2

Q.2 Find the hex sum of 16 DE 16 (93) + ( ) .

(4) Ans:
Hex Sum of (93)16 + (DE)16
Convert Hexadecimal numbers 93 and DE to its binary equivalent shown below:-
93 → 10010011
DE → 11011110
----------------
101110001 → 171
-----------------
Thus (93)16 + (DE)16 = (171)16

Q.3 Perform 2’s complement subtraction of 10 10 (7) − (11) . (4)

Ans:
2’s Complements Subtraction of (7)10 – (11)10
First convert the decimal numbers 7 and 11 to its binary equivalents. (7)10 =
(0111)2
(11)10 = (1011)2 in 4-bit system
Then find out the 2’s complement for 1011 i.e.,

1’s Complement of 1011 is 0100

2’s Complement of 1011 is 0101
So, (7)10 – (11)10 = 0111
0101
---------
1100
---------

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Since there is no carry over flow occurring in the summation, the result is a negative
number, to find out its magnitude, 2’s Complement of the result must be found. 2’s
Complement of 1100 is 0011
1
--------
 0100
--------
Here the answer is (-4)10 (or) in 2’s complement it is 1100.

Q.4 What is the Gray equivalent of ( )10 25 . (2)

Ans:
Gray equivalent of (25)10
The binary equivalent of Decimal number 25 is (00100101)2
1. The left most bit (MSB) in gray code is the same as the left most in binary 2.
Add the left most bit to the adjacent bit
3. Add the next adjacent pair and so on., Discard if we get a carry.
0+0+1+0+0+1+0+1

0 0 1 1 0 1 1 1 Gray Number

Q.5 Evaluate x = A.B+ C(A.D) using the convention A = True and B = False. (4)

Ans:
Evaluate x = A .B + C(A. D)
= AB + C ( A + D ) (Since A.D = A + D by using Demorgan’s Law) = A .B + C
. A + C. D
By using the given convention, A = True = 1; B = False = 0
=1.0 + C.1+ C. D = 0 + 0 + C. D = C. D

Q.6 Simplify the Boolean expression F = C(B + C)(A + B + C). (6)

Ans:
Simplify the Boolean Expression F = C (B +C) (A+B+C)
F = C (B+C) (A+B+C)
= CB + CC [(A+B+C)]
= CB + C [(A+B+C)] (Q CC = C)
= CBA + CBB + CBC + CA + CB + CC
= ABC + CB + CB + CA + CB + CC (Q CBB =CB & CBC = CB) = ABC + CB +
CA + C (Q CB+CB+CB = CB; CC = C)
= ABC + BC + C (1+A)
= ABC + BC + C (Q1+A = 1)
= ABC + C (1+B)

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= ABC + C (Q 1+B = 1)
= C (1+AB) = C {Q(1+AB)=1}
 F(A,B,C,D) =
Q.7 Simplify the following expression into sum of products using Karnaugh map ∑
12,9,7,6,5,4,3,1( 13, ) (7)

Ans:
Simplification of the following expression into sum of products using Karnaugh
Map:
F(A,B,C,D) = Σ (1,3,4,5,6,7,9,12,13)
Karnaugh Map for the expression F(A,B,C,D) = Σ (1,3,4,5,6,7,9,12,13) is
shown in Fig.4(a). The grouping of cells is also shown in the Figure.

The
equations for (1) is AB; (2) is C D; (3) is A D; (4) is BC
Hence, the Simplified Expression for the above Karnaugh map is
F(A,B,C,D) = AB+C D+ A D+BC
= A (B + D) +C ( B + D)

Q.8 Simplify and draw the logic diagram for the given expression
F = ABC+ ABC+ ABC+ ABC+ ABC. (7)

Ans:
Simplification of the logic expression
F = ABC + AB C + ABC + A BC + A B C
F = ABC + AB C + ABC + A BC + A B C

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F = A + B +C + ( A + B )C + ABC + A ( B +C ) + A B C
 (Q ABC = A + B +C and AB = A + B by using Demorgan’s Law) = A + B +C +
AC + B C + ABC + A B + AC + A B C
= A + AC+ B + B C +C + AC + ABC +A B + A B C
= A (1+C)+ B (1 + C) +C (1 + A) + ABC + A B + A B C = A + B +C +
ABC + A B + A B C {Q (1+C) = 1 and (1+A) = 1} = ( A + A B ) + B (1 +
AC) +C (1+ AB)
= ( A + B )+ B +C {Q ( A + A B ) = ( A + B ); (1+AC) = 1 and (1+ AB) =1} F = ( A + B
+C ) (Q B + B = B )
The logic diagram for the simplified expression F = ( A + B +C ) is given in fig.5(a)
_

A A

_
B B ___F=A+B+C

_
C C

Fig.5(a) Logic diagram for the expression F = ( A + B +C )

Q.9 Determine the binary numbers represented by the following decimal numbers. (6) (i) 25.5 (ii)
10.625 (iiii) 0.6875

Ans:
(i) Conversion of decimal number 25.5 into binary number:
Here integer part is 25 and fractional part is 0.5. First convert the integer part 25 into its
equivalent binary number i.e., divide 25 by 2 till the quotient becomes 0 shown in table 2(a)

Quotient Remainder

25 12 1
2

12 6 0
2

6 3 0
2

3 1 1
2

1 0 1
2
 Table 2(a)

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So, integer part (25)10 is equivalent to the binary number 11001. Next convert fractional
part 0.5 into binary form i.e., multiply the fractional part 0.5 by 2 till you get remainder
as 0
0.5
X2
------
1.0 Remainder

1 (Quotient)
The decimal fractional part 0.5 is equivalent to binary number 0.1. Hence, the decimal
number 25.5 is equal to the binary number 11001.1

(ii) Conversion of decimal number 10.625 into binary number:

Here integer part is 10 and fractional part is 0.625. First convert the decimal number 10
into its equivalent binary number i.e., divide 10 by 2 till the quotient becomes 0 shown
in table 2(b)
Quotient Remainder

10 5 0
2

5 2 1
2

2 1 0
2

1 0 1
2

Table 2(b)

So, the integer part 10 is equal to binary number 1010. Next convert the decimal
fractional part 0.625 into its binary form i.e., multiply 0.625 by 2 till the remainder
becomes 0
0.625 0.250 0.50
X2X2X2
------- -------- -------
1.250 0.50 1.0 (Remainder)
 1 0 1 (Quotient)
So, the decimal fractional part 0.625 is equal to binary number 0.101. Hence the decimal
number 10.625 is equal to binary number 1010.101.

(iii)Conversion of fractional number 0.6875 into its equivalent binary number:

Multiply the fractional number 0.6875 by 2 till the remainder becomes 0 i.e.,

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0.6875 0.3750 0.75 0.5

X2X2X2X2
----------- --------- -------- ------
1.3750 0.75 1.5 1.0 (Remainder)

1 0 1 1 (Quotient)

So, the decimal fractional number 0.6875 is equal to binary number 0.1011.

Q.10 Perform the following subtractions using 2’s complement method. (8) (i) 01000 – 01001 (ii)
01100 – 00011 (iii) 0011.1001 – 0001.1110

Ans:
(i) Subtraction of 01000-01001: 1’s complement of 01001 is 10110 and 2’s
complement is
10110+ 1 =10111. Hence
01000 = 01000
- 01001 = +10111 (2's complement)
-------------------------
11111 (Summation)
-------------------------
Since the MSB of the sum is 1, which means the result is negative and it is in 2's
complement form. So, 2's complement of 1111 =00001= (1)10. Therefore, the result is – 1.

(ii) Subtraction of 01100-00011: 1’s complement of 00011 is 11100 and 2’s complement
is 11100 + 1 = 11101. Hence

01100 = 01100
– 00011 = + 11101 (2's complement)
--------------------------------------------------
1 01001 = + 9

Ignore
--------------------------------------------------

If a final carry is generated discard the carry and the answer is given by the remaining bits Which
is positive i.e., (1001)2 = (+ 9)10
 (iii) Subtraction of 0011.1001 – 0001.1110: 1’s complement of 0001.1110 is 1110.0001
and its 2’s complement is 1110.0010.

0011.1001 = 0011.1001
- 0001.1110 = + 1110.1011 (2’s complement)
-------------------------------------------
1 0001.101I = + 1 .68625

Ignore

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If a final carry is generated discard the carry and the answer is given by the remaining bits which is
positive i.e., (0001.1011)2 = (+ 1.68625)10

Q.11 Simplify the expressions using Boolean postulates (9) (i) XY + XYZ + X (Y + XY) (ii) Y = (A +
B)( A + C)(B + C)
(iii) XY + XZ + XY Z (XY + Z)

Ans:
(i) XY + XYZ + X (Y + XY)
= XY + XYZ + X (Y + XY)
= X (Y + YZ) + X (Y + XY)
= X (Y + Z) + X (Y + X )
(Because Y +YZ = Y + Z andY + XY = Y + X )
= XY + XZ + XY + XX
= XY + XZ + XY + X (Because XX=X)
= XY + XZ + X 1( + Y)
= XY + XZ + X (Because (1+Y=1)
= (X + Y)(X + Z) + X (Because XY = X + Y )
=XX+XZ+YX+YZ+X
= X + X Z + Y X + Y Z + X (Because X X = X )
= X 1( + Z + Y) + Y Z + X
=X+YZ+X
= (X + X ) + Y Z
= 1+ Y Z (Because X + X = 1)
=1 = 0 (Because 1 +Y Z =1)
(ii) Y = (A + B)( A + C)(B + C)
Y = (A + B)( A + C)(B + C)
= (A A + AC + B A + BC) (B + C)
 = (AC + B A + BC) (B + C) (Because A A = 0)
= ABC + BB A + BBC + ACC + B AC + BCC
= ABC + B A + BC + AC + B AC + BC (Because BB = B)
= ABC + AC + B A + B AC + BC (Because BC + BC = BC)
=AC (B+1) + B A + BC ( A +1)
= AC + B A + BC (Because B + 1 = 1 and A + 1 = 1) = AC + B A + BC (A + A )
(Because A + A = 1)
= AC + B A + BCA + BC A
= AC(1 + B) + B A (1 + C)
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= AC + B A {Because (1 + B) = 1 and (1 + C) =1} (iii) XY + XZ + XY Z (XY + Z)

= XY + XZ + XY Z (XY + Z)
= XY + XZ + XXYY Z + XY Z Z
= XY + XZ + XY Z (Because YY = 0 & ZZ = Z)
= XY + X + Z + XY Z (Because XZ = X + Z )
= X + XY + Z + XY Z
= X + X (Y +Y Z) + Z
= X + X (Y +Z) + Z (Because Y +Y Z = Y +Z)
= X + X Y (Z+ Z ) + XZ + Z (Because Z+ Z =1)
= X + X Y Z + XY Z + XZ + Z
= X + XZ (1+ Y) + Z (1+XY)
= X + XZ + Z (Because 1+ Y = 1 &1+XY = 1)
= X + XZ) + Z
=( X + Z) + Z (Because X + XZ = X + Z
= X +( Z + Z )
= X +1 (Because Z + Z = 1)
=1 (Because X +1 = 1)

Q.12 Minimize the logic function Y(A,B,C,D) = ∑m(0 1,, 2 3 5,,, 7 8 9,,, 11,14) . Use Karnaugh
map. Draw logic circuit for the simplified function. (9)
Ans:
Fig. 4(a) shows the Karnaugh map. Since the expression has 4 variables, the map has 16
cells. The digit 1 has been written in the cells having a term in the given expression.
The decimal number has been added as subscript to indicate the binary number for the
concerned cell. The term ABC D cannot be combined with any other cell. So this term
will appear as such in the final expression. There are four groupings of 4 cells each.
These correspond to the min terms (0, 1, 2, 3), (0, 1, 8, 9), (1, 3,5,7) and (1, 3, 9, 11).
These are shown in the map. Since all the terms (except 14) have been included in
groups of 4 cells, there is no need to form groups of two cells.
 28
DE09 DIGITALS ELECTRONICS

The simplified expression is Y (A,B,C,D) = ABC D + A B + B C + B D+ A D Fig.4

(b) shows the logic diagram for the simplified expression Y (A,B, C, D) = ABC D +
A B + B C + B D+ A D

ABCD
_
ABCD

__
AB
BC

_
BD

Y
_
AD

__
 Fig.4(b) Logic diagram for Y

Q.13 Simplify the given expression to its Sum of Products (SOP) form. Draw the logic circuit for the
simplified SOP function Y = (A + B)(A + AB)C + A(B+C)+ AB+ ABC (5)

Ans:
Simplification of given expression
Y = (A + B) (A + AB ) C + A (B + C ) + AB + ABC
in some of products (SOP) form:-
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DE09 DIGITALS ELECTRONICS

Y = (A + B) (A + AB ) C + A (B + C ) + AB + ABC
=(A + B) (A + AB ) C + A (B + C ) + AB + ABC
=(A + B) (A + A + B )C + A (B + C ) + AB + ABC
=(A + B) (1+ B )C + A (B + C ) + AB + ABC (Because A + A = 1) =
(A + B) (C+ B C) + AB + A C + AB + ABC
= (A + B) (C+ B C) + AB + A C + AB + ABC
=AC + A B C + BC + B B C + AB + A C + AB + ABC = AC + AC( B +
B) + BC + 0 + AB + A C + AB (Because B B = 0) = AC + AC+ BC+ AB
+ A C (Because B + B = 1)
= AC+ BC+ AB + A C (Because AC + AC = AC)
= C (A+ B) + A (B + C )

A
BC

A+B

C (A + B)

Y
_

A C _ _ A(B + C)

_B+C
_
 Fig.4(c) Simplified Logic Circuit

Q.14 Design a 8 to 1 multiplexer by using the four variable function given by F(A,B,C,D) = ∑m(0 1
3,,, 4 8 9,,, 15). (10)
Ans:
Design of 8 to 1 Multiplexer: This is a four-variable function and therefore we need a
multiplexer with three selection lines and eight inputs. We choose to apply variables B, C,
and D to the selection lines. This is shown inTable 8.1. The first half of the minterms are
associated with A' and the second half with A. By circling the minterms of the function and
applying the rules for finding values for the multiplexer inputs, the implementation shown in
Table.8.2.
The given function can be implemented with a 8-to-1 multiplexer as shown in fig.8(a). Three
of the variables, B, C and D are applied to the selection lines in that order i.e., B is
connected to s2, C to s1 and D to s0. The inputs of the multiplexer are 0, 1, A and A’. When
BCD = 000,001 & 111 output F = 1 since I0 & I8 = 1 for BCD(000), I1 = 1and I9 =1
respectively. Therefore, minterms m0 = A’ B’ C’ m1 = A’ B’ C, m8 = A’, B’, C’ and
m9 = A’ B’ C produce a 1 output. When BCD = 010, 101 and 110, output F = 0, since I2, I5
and I6 respectively are equal to 0.

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Minterm ABCD F

0 0000 1

1 0001 1

2 0010 0

3 0011 1

4 0100 1

5 0101 0

6 0110 0

7 0111 0

8 1000 1

9 1001 1

10 1010 0
 11 1011 0

12 1100 0

13 1101 0

14 1110 0

15 1111 1

Table .8.1 Truth Table for 8-1 Multiplexer

Table 8.2 Implementation Table for 8 to 1 MUX

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IIII 6
0 7
1 BCD
1

2
0 3
A 8X1
4 YF
IIII MUX
5
 S
SS

210

Fig.8(a) Logic circuit for 8-to-1 Multiplexer

Q.15 Convert the decimal number 82.67 to its binary, hexadecimal and octal equivalents. (6)

Ans:
(i)Conversion of Decimal number 82.67 to its Binary Equivalent Considering the
integer part 82 and finding its binary equivalent

2 82
2 41 Remainder ----- 0 (LSB)
2 20 Remainder ----- 1
2 10 Remainder ----- 0
2 5 Remainder ------0
2 2 Remainder ----- 1
2 1 Remainder ---- 0
0 Remainder ---- 1 (MSB)

The Binary equivalent is (1010010)2

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Now taking the fractional part i.e., 0.67

 Fraction Fraction X 2 Remainder Integer
New
Fraction

0.67 1.34 0.34 1

0.34 0.68 0.68 0

0.68 1.36 0.36 1

0.36 0.72 0.72 0

0.72 1.44 0.44 1

0.44 0.88 0.88 0

0.88 1.76 0.76 1

0.76 1.52 0.52 1

It is seen that, it is not possible to get a zero as remainder even after 8 stages. The process
continued further on an approximation can be made and the process is terminated here. The binary
equivalent is 0.10101011
Therefore, the binary equivalent of decimal number 82.67 is (1010010.10101011)2
(ii)Conversion of the binary equivalent of decimal number 82.67 into Hexadecimal: The
binary equivalent of decimal number 82.67 is (1010010.10101011)2
Convert each 4-bit binary into an equivalent hexadecimal number i.e.
0101 0010 .1010 1011
52AB

Therefore, the hexadecimal equivalent of decimal number 82.67 is (52.AB)16 (iii)Conversioin of the
binary equivalent of decimal number 82.67 into Octal number: The binary equivalent of decimal
number 82.67 is (1010010.10101011)2
Convert each 3-bit binary into an equivalent octal number i.e.

001 010 010 .101 010 110

122.526

Therefore, the Octal equivalent of decimal number 82.67 is (122.526)8

Q.16 Add 20 and (-15) using 2’s complement. (4)

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DE09 DIGITALS ELECTRONICS
 Ans:
Addition of 20 and (-15) using 2’s Complement:
Remainder ----- 0 2 2 Remainder
----- 1 2 1 Remainder ------0 0
Remainder ----- 1(MSB)

2 16
2 8 Remainder ----- 0 (LSB) 2 4
Remainder ----- 0 2 2 Remainder
----- 0 2 1 Remainder ------0 0

2 20 Remainder ----- 1(MSB)

2 10 Remainder ----- 0 (LSB) 2 5

=10100
(20)10 (16)10 = 1 0 0 0 0

(-16)10 = 0 1 1 1 1(1’s Complement)

+1(2’s Complement)
---------------------
10000
---------------------
Therefore, 20 = 1 0 1 0 0
-16 = 1 0 0 0 0
-----------------------------
100100

(Neglect)
--------------------------------
Since the MSB of the sum is 0, which means the result is positive i.e +4 Q.17 Add 648 and 487 in

BCD code. (4)

Ans:
Addition of 648 and 487 in BCD Code:
648=011001001000
487=010010000111
--------------------------------------------------
101011001111

10 12 15
--------------------------------------------------
In the above problem all the three groups are invalid, because the four bit sum is more than
9. In such cases, add +6(i.e. 0110) to the four bit sum to skip the six invalid states. If a carry
 is generated when adding 6, add the carry to the next four bit group i.e.

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DE09 DIGITALS ELECTRONICS

648=011001001000
487=010010000111
--------------------------------------------------
101011001111
011001100110
11111111
------------------------------------------------------
0001 0 0 0 1 0 0 1 1 0 1 0 1

1135
-------------------------------------------------------
Addition of 648 and 487 in BCD Code is 1135.

Q.18 Prove the following Boolean identities. (4) (i) XY + YZ + Y Z = XY + Z

(ii) A.B+ A.B+ A.B = A + B

Ans:
(i) Prove the Boolean Identity XY + YZ + Y Z = XY + Z
L.H.S = XY + YZ + Y Z
Q
= XY(Z+ Z ) + YZ + Y Z ( Z + Z = 1)
= XYZ + XY Z + YZ + Y Z
= YZ(1+X) + XY Z +Y Z
Z
= YZ + XY +Y Z (Q1+X = 1)
Y
= Z (Y+ ) + XY Z
= Z + XY Z (Q Y+Y =1)
Z
= Z + XY(QZ + XY = Z + XY)
= R.H.S (Hence Proved)

(ii) Prove the Boolean Identity A B + A B + A B = A + B

R.H.S = A + B
Q
= A (B + B ) + B (A + A ) ( B + B = 1 & A + A = 1)
= A (B + B ) + B (A + A )
AB
= AB + +BA+BA
= AB + AB + B A ( AB + AB = AB)
= L.H.S (Hence Proved)

Q.19 For F = A.B.C+ B.C.D + A.B.C , write the truth table. Simplify using Karnaugh map and realize
the function using NAND gates only. (10)
Ans:
Simplification of Logic Function F = A B C + B C D + A B C

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(i)The Truth Table is given in Table 4.1

Inputs Output
(F)
ABCD

0000 0

0001 0

0010 0

0011 0

0100 0

0101 1

0110 1

0111 1

1000 0

1001 0

1010 0

1011 0

1100 0

1101 1

1110 1

1111 1

Table 4.1

(ii) The Karnaugh Map is shown in fig.4(a).

The simplified expression is F = BC + BD
 (iii)
The NAND-NAND Realization is shown in fig.4(b)

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__ __ __
BC F = BC . BD = BC + BD

BC
__
BD
______
BD

Fig. 4(b) NAND-NAND Realization

Q.20 Determine the analog output voltage of 6-bit DAC (R-2R ladder network) with Vref as 5V when
the digital input is 011100. (10)

Ans:
For 6-bit R-2R DAC ladder network, the output voltage is given by
V
()0
Vn
n − 1 − 2 1

R
= + +⋅⋅⋅⋅+ + 0 12 2 2 2 2a a a a

− n − 2 1 0
nn

Given Data : VR = 5V, n = 6, a5=0, a4=1,a3=1,a2=1,a1=0,a0=0

5
 ( )0
5 4 3 2 1
V = a + a + a + a + a + a 0 6 52 2 2 2 2 2
4 2 0
2 5 3 1

()
543210
V=⋅+⋅+⋅+⋅+⋅+⋅
0
60 2 1 2 1 2 1 2 0 2 0 2
2
28
64 5 V0 = ⋅ = 2.1875 V

Q.21 Solve the following equations for X (6) 23.6 = (ii) 65.53510 = X16
(i) 10 X2

Ans:
(i) Solve the equation 23.610 = X2 for X
23.610 = X2
In order to find X, convert the Decimal number 23.610 into its Binary form. First take the
decimal integer part 23 to convert into its equivalent binary form
2 23
2 11 ------- 1
2 5 --------1
2 2 --------1
2 1 --------0
0 --------1

Hence 2310 = 101112

Next take the decimal fractional part 0.6 to convert into its equivalent binary form.

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Fraction Fraction X 2 Remainder Integer
new fraction

0.6 1.2 0.2 1

0.2 0.4 0.4 0

0.4 0.8 0.8 0

0.8 1.6 0.6 1

0.6 1.2 0.2 1

0.2 0.4 0.4 0

0.4 0.8 0.8 0

 It is seen that it is not possible to get a zero as remainder even after 7 stages. The process
can be continued further or an approximation can be made and the process terminated here.
The binary equivalent is 0.1001100.
Hence 23.610 = 10111.10011002.
(ii) In order to find X, convert the Decimal number 65.535 into its equivalent Hexadecimal
form. First taking the integer part 65 to convert into its equivalent Hexadecimal form.

16 65
16 4 ---- 1
0 ---- 4

Hence 6510 = 4116

Next take the decimal fractional part 0.6 to convert into its equivalent binary form.
Fraction Fraction X 16 Remainder Integer
new fraction

0.535 8.56 0.56 8

0.56 8.96 0.96 8

0.96 15.36 0.36 15 (F)

0.36 5.76 0.76 5

0.76 12.16 0.16 12(C)

0.16 2.56 0.56 2

0.56 8.96 0.96 8

It is seen that it is not possible to get a zero as remainder even after 7 stages. The process
can be continued further or an approximation can be made and the process terminated here.
The Hexadecimal equivalent is 0.88F5C28.
Hence 65.53510 = 41.88F5C2816.

Q.22 Perform the following additions using 2’s complement (5) (i) -20 to +26 (ii) +25 to -15

Ans:

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(i) First convert the two numbers 20 and 26 into its 8-bit binary equivalent and find out the
2’s complement of 20, then add -20 to +26.
20 = 0 0 0 1 0 1 0 0 (8-bit binary equivalent of 20) 20 = 1 1 1 0 1 0 1 1 (1’s
complement)
+1
-------------------------------
20 = -20 = 1 1 1 0 1 1 0 0 (2’s complement of 20)
+26 = 0 0 0 1 1 0 1 0 (8-bit binary equivalent of 26)
-----------------------------
Addition of -20 to +26
= +6 = 0 0 0 0 0 1 1 0
-----------------------------
Hence -20 to +26 = (6)10 = (0110)2.

(ii) First convert the two numbers 25 and 15 into its 8-bit binary equivalent and find out
the 2’s complement of 15, then add +25 to -15.
15 = 0 0 0 0 1 1 1 1 (8-bit binary equivalent of 15)
15 = 1 1 1 1 0 0 0 0 (1’s complement)
+1
------------------------------
15 = -15 = 1 1 1 1 0 0 0 1 (2’s complement of 15)
+25 = 0 0 0 1 1 0 0 1 (8-bit binary equivalent of 25)
------------------------------
Addition of -15 to +25
= +10 = 0 0 0 0 1 0 1 0
-------------------------------
Hence -15 to +25 = (10)10 = (1010)2.

Q.23 (i) Convert the decimal number 430 to Excess-3 code: (6) (ii) Convert the binary number
10110 to Gray code:

Ans:
(i) Excess 3 is a digital code obtained by adding 3 to each decimal digit and then converting
the result to four bit binary. It is an unweighted code i.e., no weights can be assigned to
any of the four digit positions.
430
+3+3+3
-----------------------------
763

0111 0110 0011 (Excess-3 Code)

--------------------------------
(ii) The rules for changing binary number 10110 into its equivalent Gray code are, the left
most bit (MSB) in Gray code i.e., 1 is the same as the left most bit in binary and

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DE09 DIGITALS ELECTRONICS

add the left most bit (1) to the adjacent bit (0) then add the next adjacent pair and discard
the carry. Continue this process till completion.
++++
10110

11101
Hence Gray equivalent of Binary number 10110 is 11101.

Q.24 Verify that the following operations are commutative but not associative (6) (i) NAND (ii)
NOR

Ans:
(i) Commutative Law is AB = BA . To verify whether the NAND operation is Commutative
or not, prepare truth table shown in Table No.3.1
A B AB BA

0 0 1 1

0 1 1 1

1 0 1 1

1 1 0 0

Table No.3.1

From the Table No.3.1, we observe that the last two columns are identical, which means AB = BA
Associative Law is A(. B.C) = (A.B .)C
To verify whether the NAND operation is Associative or not, prepare truth table shown in
Table No.3.2
A B C A(. B.C) ( A.B .)C

0 0 0 1 1

0 0 1 1 0

0 1 0 1 1

0 1 1 1 0

1 0 0 0 1

1 0 1 0 0

1 1 0 0 1

1 1 1 1 1
Table No.3.2

From the Table No.3.2, we observe that the last two columns are not identical, which means A(. B.C)
≠ (A.B .)C

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(ii) Commutative Law is A + B = B + A. To verify whether the NOR operation is

Commutative or not, prepare truth table shown in Table No.3.3

A B A+B B+A

0 0 1 1

0 1 0 0

1 0 0 0

1 1 1 1

Table No.3.3

From the Table No.3.3, we observe that the last two columns are identical, which means A + B = B
+A
Associative Law is A + (B + C) = (A + B) + C
To verify whether the NOR operation is Associative or not, prepare truth table shown in Table No.3.4

A B C A + (B + C) (A + B) + C

0 0 0 0 0

0 0 1 1 0

0 1 0 1 1

0 1 1 1 0

1 0 0 0 1

1 0 1 0 0

1 1 0 0 1

1 1 1 0 0

Table No.3.4
From the Table No.3.4, we observe that the last two columns are not identical, which means A.+ (B +
C) ≠ ( A + B) + C

Q.25 Prove the following equations using the Boolean algebraic theorems: (5) (i) A + A .B + A . B =
A + B (ii) ABC + A B C + ABC + ABC = AB + BC + AC

Ans:
(i) Given equation is A + A .B + A. B = A + B
L.H.S. = A + A .B + A. B
= (A + A. B ) + A .B
= A (1+ B ) + A .B
= A + A .B (Q 1+ B =1)
= (A + A ) (A + B)
= (A + B) (QA + A = 1)
= R.H.S
Hence Proved

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(ii) Given equation is ABC + A B C + ABC + ABC = AB + BC + AC

L.H.S = ABC + A B C + ABC + ABC
= ABC + A B C + ABC + ABC
= ABC + A B C + AB (C +C )
= ABC + A B C + AB (Q C +C = 1)
= ABC + A (B + B C)
= ABC + A (B + C) (QB + B C = B + C)
= ABC + A B + AC
= C (A + AB) + A B + AC
= C (A + B) + A B + AC (QA + AB = A + B)
= AC + BC + AB + AC
= AB + BC + AC (QAC + AC = AC)
= R.H.S
Hence Proved

Q.26 A staircase light is controlled by two switches one at the top of the stairs and another at the
bottom of stairs (5) (i) Make a truth table for this system.
(ii) Write the logic equation is SOP form.
(iii) Realize the circuit using AND-OR gates.

Ans:
A staircase light is controlled by two switches S1 and S2, one at the top of the stairs and
another at the bottom of the stairs. The circuit diagram of the system is shown in fig.4(a).

1
 00 1

S
SL
12

BULB
ON = 1 OFF
=0

SUPPLY

Fig.4(a) Circuit diagram

(i) The truth table for the system is given in truth table 4.1
S1 S2 L

0 0 0

0 1 1

1 0 1

1 1 0

Table 4.1
(ii) The logic equation for the system is given by L = 1 S S2 + S1 2

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(iii) Realization of the circuit using AND-OR gates is shown in fig 4(b)
_
S.S
SS

12
1

_
S.S
L
2 12

Fig.4(b) Logic Diagram for the system

Q.27 Minimize the following logic function using K-maps and realize using NAND and NOR gates.
F(A,B,C,D) = ∑m 1 3 5 8 9,,,,,( 11,15) + d(2,13) (9)
Ans:
Minimization of the logic function F(A, B, C, D) = ∑ m(1,3,5,8,9,11.15) + d(2,13) using K
maps and Realization using NAND and NOR Gates
 (i) Karnaugh Map for the logic function is given in table 4.1

The minimized logic

expression in SOP form is F = A B C + C D + B D + AD The minimized logic expression in POS
form is F = (A + B +C ) (C +D) ( B+D) (A+D)

(ii) Realization of the expression using NAND gates:

The minimized logic expression in SOP form is F = A B C + C D + B D + AD and the logic
diagram for the simplified expression is given in fig.4(c)

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ABCD

_
A+B+C _

C+D

_
B+D

F
__
A+D
 Fig.4(c) Logic Diagram

(iii) Realization of the expression using NOR gates:

The minimized logic expression in POS form is F = (A + B +C ) (C +D) ( B+D) (A+D) and
the logic diagram for the simplified expression is given in fig.4(d)
D
ABC ________
_
C+D

_____
_
B+D

Fig.4(d) Logic ____

A+D
Diagram F
__
A+B+C

____

Q.28 Design a 4 to 1 Multiplexer by using the three variable function given by F(A,B,C) = ∑m 1 3 5,,,(
6) (7)
Ans:
Design of 4 to 1 Multiplexer by using the three variable function given by
F(A,B,C) = ∑ m(1,3,5,6)
The function F(A,B,C) = ∑ m(1,3,5,6) can be implemented with a 4-to-1 multiplexer as
shown in Fig.7(a). Two of the variables, B and C are applied to the selection lines in that
order, i.e., B is connected to S1 and C to S0. The inputs of the multiplexer are 0, I, A, and A'.
When BC = 00, output F = 0 since I0 = 0. Therefore, both minterms m0 = A' B' C' and m4 =
A B' C' produce a 0 output, since the output is 0 when BC = 00 regardless of the value of A.
When BC = 01, output F = 1, since I1 = 1. Therefore, both minterms m1 =A' B'C and

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DE09 DIGITALS ELECTRONICS

m5 = AB'C produce a 1 output, since the output is 1. when BC = 01 regardless of the value of
A.
When BC = 10, input I2 is selected. Since A is connected to this input, the output will be
equal to 1 only for minterm m6 = ABC', but not for minterm m2 = A' BC', because when A' =
I, then A = 0, and since I2 = 0, we have F = 0.
Finally, when BC = 11, input I3 is selected. Since A' is connected to this input, the output
will be equal to 1 only for minterm m3 = A' BC, but not for m7 = ABC. This is given in the
Truth Table shown in Table No 7.1

Minterm A B C F

0 0 0 0 0

1 0 0 1 1

2 0 1 0 0

3 0 1 1 1

4 1 0 0 0

5 1 0 1 1

6 1 1 0 1

7 1 1 1 0

Table 7.1 Truth Table

Fig.7(a) Implementation Table

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A' I
I 0
4x1
0 Y
MUX
I 12
1
I S
S
A F

310

Fig.7(b) Logic Diagram of 4X1 Multiplexer

Q.29 Find the conversion time of a Successive Approximation A/D converter which uses a 2 MHz
clock and a 5-bit binary ladder containing 8V reference. What is the Conversion Rate? (4) Ans:
Given data:
Frequency of the clock (F) = 2 MHZ
Number of bits (n) = 5
n
=6
5
(i) Conversion Time (T) = = 2.5 ∝ sec
clockrate X 2 10

(ii) Conversion Rate = 1

T = 61

−
X = 400,000 conversions/sec
2.5 10

Q.30 A 6-bit R-2R ladder D/A converter has a reference voltage of 6.5V. It meets standard linearity.
Find
(i) The Resolution in Percent.
(ii) The output voltage for the word 011100. (4)

Ans:
 Given Data Number of Bits (n) = 6
Reference Voltage (VR) = 6.5 V
For R-2R Ladder D/A Converter,
1 1 1
=
6==
(i)The Resolution in Percent is given by 59.1 n %

− − 63
21 21
(ii)The Output Voltage (VO ) of 6-bit R-2R Ladder D/A Converter for the word 011100 is
given by

V
[] 0

− 1 − 2 1
Vn
n

O = + + − − − − + + 2a a a a −

12. 2. 2 2 R
−
2
1
0

nn
n

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5.6
[] −−−−−

61514131210
VO = + X + X + X + X + X
62.0 1 2 1 2 1 2 0 2 0 2 2

5.6
[]
432
VO = + +
2
2226
84.2 VO = V.

Q.31 Convert 2222 in Hexadecimal number. (4)

Ans:
2222
16 138 14
 16 8 10 =8AE
08

Q.32 Subtract –27 from 68 using 2’s complements. (6)

Ans:
68-(-27)=68-(-27)using 2’s complement
2’s complement representation of 68=01000100(64+4)
2’s complement representation of - (-27) = 00011011 =+ 27
11100101 =-27 in 2’s complement
Now add 68 and 27
68 0 1 0 0 0 1 0 0
-(-27) + 0 0 0 1 1 0 1 1
95 0 1 0 1 1 1 1 1 1

Which is equal to +95

Q.33 Divide ( )2
101110 by ( )2
101 . (4)

Ans:
1011011101001
101
000110
101
001
Quotient -1001
Remainder -001

Q.34 Prove the following identities using Boolean algebra:

(i) (A + B)(A + AB)C + A(B + C)+ AB + ABC = C(A + B) + A(B + C). (ii) A(
) A ⋅B ⋅ B( ) A ⋅ B = A ⊕ B .

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DE09 DIGITALS ELECTRONICS

(iii) AB + A + AB = 0 . (9)

Ans:
(i) (A+B)(A+A’B’)C+A’(B+C’)+A’B+ABC
=C(A+B)+A’(B+C’)
LHS (A+B)(A+A’+B’)C+A’B+A’C’+A’B+ABC
= (A+B)(1+B’)C+A’B+ A’C’+ABC as (A+A’=1)
= (A+B).1.C+A’B+ A’C’+ABC
 = AB+AC+A’B+ A’C’+ABC
= ABC+AB+ABC+AC+A’B+A’C’
AB(C+1)+AC(B+1) +A’B+ A’C’
= AB+AC+A’B+ A’C’
= C(A+B) + A’(B+C’) = RHS
Hence Proved
(ii) A(A.B .) B(A.B) = A⊕ B
Let us take X = A(A.B)
Y = B(A.B)
So we have X.Y = A⊕ B -------3
Also X = A(A.B)
= A(A′ + B′)
By using DeMorgan’s Law (AB)’=A’+B’
X = (A(A’+B’))’=(AA’+AB’)’=(AB’)’=(A’+B) ------1
Now Y = (B(AB)’)’=[B(A’+B’)]’= [A’B+BB’]’=(A’B)’=(A+B’) ------2
Now Combining X & Y from 1 & 2 above, we have L.H.S in 3 as :
((A+B’)(A’+B))’
=[AA’+BB+A’B’+AB]’
=(AB+A’B’)’
=A XOR B = RHS
Hence Proved
(iii) ((AB)’+A’+AB)’=0
LHS AB)
(AB + A +
= ) 1( + A′ ′ since AB + AB =1
= 1′ since 1+ A′ =1
= 0 = RHS Hence Proved

Q.35 A combinational circuit has 3 inputs A, B, C and output F. F is true for following input
combinations
A is False, B is True
A is False, C is True
A, B, C are False
A, B, C are True
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(i) Write the Truth table for F. Use the convention True=1 and False = 0. (ii) Write the
simplified expression for F in SOP form.
(iii) Write the simplified expression for F in POS form.
(iv) Draw logic circuit using minimum number of 2-input NAND gates. (7)

Ans:
(i) Making the truth table
 A B C F

0 0 0 1

0 0 1 1

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 0

1 1 0 0

1 1 1 1

A is false b is true For both value of c F is true.

(ii) Simplified expression for F can be found by K-map

In SOP Form
F = A’+BC
(iii) Simplified expression for F in POS form
I. In POS Form MINIMIZE ZEROS
F’=AB’+AC’
II. F=A’+BC taking complement twice
F’=( A’+BC)’=(A.(BC)’)
F”=F=(A.(BC)’)’
(iv) Logic circuit by using minimum number of 2-input NAND gates

Q.36 Minimise the logic function

F (A,B,C, D) = Π M ( 9, 8, 3, 2, 1, 10,11,14)⋅ d ( 15 7, )
Use Karnaugh map. Draw the logic circuit for the simplified function using NOR gates only. (7)

49
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Ans:
F=∏M(1,2,3,8,9,10,11,14).d(7, 15)

F’=B’D+B’C+AC+AB’
By Complementing F
F=(B’D+B’C+AC+AB’)’
= [(B’D)’(B’C)’(AC)’(AB’)’]’
= (B+D’)(B+C’)(A’+C’)(A’+B)
Taking complement twice and without opening the bracket
F=[(B+D’)+(B+C’)’(‘A’+C’)+(A’+B)]’
The logic circuit for the simplified function using NOR gates

Q.37 The capacity of 2K ⋅ 16 PROM is to be expanded to 16 K ⋅ 16. Find the number of PROM chips
required and the number of address lines in the expanded memory. (4)
Ans:
Required capacity =16k x 16
Available chip (PROM) =2k x 16
The no of chip =16k x 16 = 8
2k x 16
In the chip total word capacity = 2 x 210

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 Thus the address line required for the single chip = 11
In the expanded memory the word capacity 16k = 214
Now the address lines required are 14. Among then 11 will be common and 3 will be
connected to 3 x8 decoder.

Q.38 Perform following subtraction

(i) 11001-10110 using 1’s complement
(ii) 11011-11001 using 2’s complement (8)

Ans:
(i ) 11001 - 10110
1' s Compliment of 10110 = 01001
11001
+01001
------------------
100010
Add 1 and ignore carry.
Ans is 00011 = 3.
(ii) 11011 – 11001 = A – B
2's complement of B = 00111
11011
+00111
100010
Ignore carry to get answer as 00010 = 2.

Q.39 Reduce the following equation using k-map

Y = ABC+ ACD + AB+ ABCD + ABC (8)
Ans:
Y = ABC + ACD+ AB+ ABC
Y = ABCD + ABCD + ABCD + ABCD+ ABCD + ABCD
+ ABCD + ABCD + ABCD+ ABCD + ABCD

Q.40 Write the expression for Boolean function

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F (A, B, C) = ∑m (1,4,5,6,7) in standard POS form. (8)

Ans:
f (A,B,C)= ΣM (1,4,5,6,7) in standard POS form
F = m1 + m4 + m5 + m6 + m7
F = Σm(1,4,5,6,7)
= ∏ M(0,2,3)
= M0 M2 M3
= (A+B+C)(A+B +C)(A+B +C )

Q.41 Design a 32:1 multiplexer using two 16:1 multiplexers and a 2:1 multiplexer. (8)

Ans:
To design a 32 X 1 MUX using

s2
s3 s0
s1

I0
16 X1
I15 2X1
s1 MUX
s 2

I16 I31 s3 s0

16X1
MUX Select line
MUX
M

Two 16 X 1 MUX & one 2 X 1

There are total 32 input lines and one O/P line. The 2 X 1 MUX will transmit
one of the two I/P to output depending upon its select line M. For M = 0 upper MUX
( I0 – I15 ) will be selected and M = 1 lower MUX ( I16 – I31 ) will be selected.

Q.42 Implement the following function using a 3 line to 8 line decoder.

S (A,B,C) = ∑ m(1,2,4,7)
C (A,B,C) = ∑ m ( 3,5,6,7) (8)
Ans:
S (A,B,C) = m (1,2,4,7)
C (A,B,C) = m (3,5,6,7)
These are full adder's output as sum (S) and carry ( C ). We know that 3 to 8 line decoder
generates all the minterms from 0 to 7. In the decoder shown in the figure, Do correspond
to minterm mo, and so on. So by ORing appropriate outputs of the decoder we can
implement these functions.
 52
DE09 DIGITALS ELECTRONICS

Q.43 Perform the following operations using the 2’s complement method: (i) 23 – 48 (ii)
– 48 – 23 (4)

Ans:
(i) 23 - 48
add them
23 0 1 0 1 1 1
- (- 48) + 0 1 0 0 0 0
71 1 0 0 1 1 1
(ii) – 48 - 23 = - 48 + (-23)
-48 = 1 1 0 1 0 0 0 0
-23 = 1 1 1 0 1 0 0 1
1 1 0 1 1 1 0 0 1 = -71

Carry is discarded

Q.44 Prove the following Boolean identities using the laws of Boolean algebra:
(i) (A + B)(A + C) = A + BC
(ii) ABC + ABC + ABC = A(B + C) (4)

Ans:
(i) (A+B)(A+C)=A+BC
LHS AA+AC+AB+BC=A+AC+AB+BC
OR A((C+1)+A(B+1))+BC
OR A+A+BC
OR A+BC = RHS
Hence Proved
(ii) ABC+AB’C+ABC’=A(B + C)
LHS AC(B+B’)+AB(C+C’)
 OR AC+AB
OR A(B+C)= RHS
Hence Proved

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Q.45 The Karnaugh map for a SOP function is given below in Fig.1. Determine the simplified SOP
Boolean expression. (5)

Ans:

Q.46 A certain memory has a capacity of 4K⋅8

(i) How many data input and data output lines does it have?
(ii) How many address lines does it have?
(iii) What is its capacity in bytes? (5)

Ans:
(i) available capacity =4Kx8
= 210 x210 x 8
= 212x8
As in the 4Kx8 ,the second number represents the number of bits in each word so the
number of data input lines will be 8(also the data output lines) .
(ii) It has total 4K (2 12) address line which are required to address 212 locations. (iii)
Its capacity in bytes is 4K bytes.

Q.47 A 5-bit DAC produces an output voltage of 0.2V for a digital input of 00001. Find the value of
the output voltage for an input of 11111. What is the resolution of this DAC? (6)

Ans:
For the Digital output of 00001
 Output voltage is =0.2 volt =Resolution
The output=.2x31=15.5volts
Resolution=(0.2volt)/(15.5v)x100=1.290

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Q.48 An 8-bit successive approximation ADC has a resolution of 20mV. What will be its digital
output for an analog input of 2.17V? (4)

Ans:
Resolution =20mv
Analog input =2.17v
Equivalent value=(2.17)/(2.17)=108.5
Equivalent Binary value=1101100.1

Q.49 A microprocessor uses RAM chips of 1 1024 ⋅ capacity.

(i) How many chips will be required and how many address lines will be connected to
provide capacity of 1024 bytes.
(ii) How many chips will be required to obtain a memory of capacity of 16 K bytes. (5)

Ans:
( i ) Available chips = 1024 x 1 capacity
Required capacity = 1024 x 8 capacity

No.of Chips=1024X8
=8
1024X1
Number of address lines are required = 10 (i.e. 1024 = 210 )
As the word capacity is same ( 1024 ) so same address lines will be connected to all chips.

( ii )

No.Of Chips Required =16X1024X8

1024X1= 128
Q.50 Find the Boolean expression for logic circuit shown in Fig.1 below and reduce it using
Boolean algebra. (6)

Ans:
Y = (AB)’ + (A’ + B)’
= A’ + B’ + AB’ Using Demorgan’s Theorem.
= A’ + B’(1+A)
 = A’ + B’ Since 1+A=1

Q.51 Implement the following function using 4-to-1 multiplexer.

= ( 6,5,3,2 ) (8)
Y( ,A ,B C) ∑

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Ans:
Y(A,B,C)=∑(2,3,5,6)
Let us take B,C as the select bits and A as input. To decide the input we write.
Y = A’BC’+A’BC+AB’C+ABC’
= 0 if B=0, C=0
= A if B=0, C=1
= 1 if B=1, C=0
= A’ if B=1, C=1
The corresponding implementation is shown in the figure. Thus

0
A 4x1 Y
1 MUX
A’

BC

Q.52 Design a mod-12 Synchronous up counter. (8)

Ans:
Design a mod 12 synchronous counter using D-flipflops.
I state table
Present state Next state Required D Inputs
A B C D A B C D DA DB DC DD

0 0 0 0 0 0 0 1 0 0 0 1

0 0 0 1 0 0 1 0 0 0 1 0

0 0 1 0 0 0 1 1 0 0 1 1

0 0 1 1 0 1 0 0 0 1 0 0

0 1 0 0 0 1 0 1 0 1 0 1

0 1 0 1 0 1 1 0 0 1 1 0

0 1 1 0 0 1 1 1 0 1 1 1
 0 1 1 1 1 0 0 0 1 0 0 0

1 0 0 0 1 0 0 1 1 0 0 1

1 0 0 1 1 0 1 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 1 1

1 0 1 1 0 1 0 0 0 1 0 0

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First draw the state table having present state, next state and required flip-flop input to give the
transition. D flip flop gives the output same as the next state itself. Then solve by using K
maps to find out DA DB DC DD for all states.
Unused states are 1100,1101,1110,1111 they can be treated as don’t care conditions from the
table. Draw Karnaugh-maps for DA, DB, DC and DD as follows and obtain Boolean expressions
for them.
 57
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 58
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 Logic diagram for mod-12 Synchronous up-counter

Q.53 Find how many bits of ADC are required to get an resolution of 0.5 mV if the maximum full
scale voltage is 10 V. (8)

Ans:
Resolution=.5mv
Full scale output=+10v
%resolution =(5mv)/10x100=0.05%
No of bits =Log2(2x1000) = 20

Q.54 Convert the decimal number 45678 to its hexadecimal equivalent number. (4)

Ans:
(45678)10=(B26E)16

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 16 45678

16 2854 14 E
16 178 6 6
16 11 2 2
0 11 B

(45678)10=(B26E)16

Q.55 Write the truth table of NOR gate. (4)

Ans:
ABF
001
010
100
110

Q.56 Design a BCD to excess 3 code converter using minimum number of NAND gates. Hint: use k
map techniques. (8)

Ans:
First we make the truth table
BCD no EXCESS-3 NO
ABCD WXYZ

0000 0011

0001 0100

0010 0101

0011 0110

0100 0111

0101 1000

0110 1001

0111 1010

1000 1011

1001 1100

Then by using K maps we can have simplified functions for w, x, y, z as shown below:
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 61
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 NAND gate implementation for simplified function
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W = BD + AD + AB’ + BC
By complementing twice we get
W = ((BD + AD + AB’ + BC)’)’
= ((BD)’ . (AD)’ . (AB’)’ . (BC)’)’
X = BC’D + B’D + B’C
By complementing twice we get
X = BC’D + B’D + B’C
= ((BC’D)’ . (B’D)’ . (B’C)’)’
Y = C’D’ + CD
= ((C’D’)’ + (CD)’)’
Z = D’
Logic diagram for BCD to excess 3 code converter by using minimum number of NAND gates

Q.57 With the help of a suitable diagram, explain how do you convert a JK flipflop to T type flipflop.
(4)

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Ans:
Given flip flop is JK flip flop and it is required to convert JK into T. First we draw the
characteristic table of T flip flop and then relate the transition with excitation table of JK flip
flop.
 Now we solve K maps for J and K by
considering T and Q(t) as input.

Logic diagram convert a JK flipflop to T type flipflop.

Q.58 A number of 256 x 8 bit memory chips are available. To design a memory organization of 2 K
x 8 memory. Identify the requirements of 256 x 8 memory chips and explain the details. (8)

Ans:
Chips available=256x8
Required capacity=2048x8
Number of chips=(2048x8)/(256x8)=8=(256=28)
Address lines required for 2048x8chip=11(2048=211)
Thus the size of the decoder=3x8
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Q.59 Convert ( )10 177 to octal. 25. (8)

Ans:
(177.25)10 = ( )8
First we take integer part
2 1 6 2 (177)10 =
8 8 8
0 (261)8
177 22
Thus

Now as 0.25 x 8 = 2.00

and 0.00 x 8 = 0
Thus (0.25)10 = (0.2)8
Therefore, Thus (177.25)10 = (261.2)8

Q.60 Perform the following subtraction using 1’s complement

(i) 11001 – 10110 (ii) 11011 - 11001 (8)

Ans:
(i) 11001 – 10110 = X – Y
X = 11001
1’s complement of Y = 01001
Sum = 1 00010
End around carry = 1
So X-Y = 00011
(ii) 11011 – 11001 = X – Y
X = 11011
1’s complement of Y = 00110
Sum = 1 00001
End around carry = 1
So X-Y = 00010

Q.61 Prove the following identities

(i) C B A + C B A + A C B + A C B = C
(ii) A B+ A C B + B A + A C B = B+ A C (8)

Ans:
(i) LHS = A’B’C’ + A’BC’ + AB’C’ + ABC’
= A’C’ (B’ + B) + AC’ (B’ + B)
= A’C’ + AC’ [as B’+B = 1]
 = C’ (A’ + A)
= C’ [as A’+A =1]

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= RHS.
Hence Proved

(ii) LHS = AB + ABC + A’B + AB’C = B + AC

= B (A + A’) + AC (B + B’)
= B + AC [as B + B’ = A + A’ = 1]
= B + AC
= RHS.
Hence Proved

Q.62 Find the boolean expression for the logic circuit shown below. (8)

Ans:
Output of Gate-1 (NAND) = (AB)’
Output of Gate-2 (NOR) = (A’+B)’
Output of Gate-3 (NOR) = [(AB)’ + (A’+B)’]’
Now applying De-Morgans law, (X+Y)’ = X’Y’
and (XY)’ = (X’+Y’)
[(AB)’ + (A’+B)’]’ = [(AB)’]’ [(A’+B)’]’
= (AB) (A’+B)
= AA’B + ABB
= ABB
= AB.

Q.63 Reduce the following equation using k-map

Y = D C B + B A D C + A D C B + D C B A + A D C B (8)

Ans:
Multiplying the first term by (A+A’)
Y = A’BC’D’ + ABC’D’ + A’BC’D + ABC’D + A’BCD + ABCD
=
∑
12,4( 15,7,5, 13, )

= BC’ + BD
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Q.64 Implement the following function using 8 to 1 multiplexer

= ( 11,9,5,2,1,0 13, 15, ) (8)
Y( ,A ,B ,C D) ∑
Ans:
We will take three variables B,C & D at selection lines and A as input. Now there are
eight inputs and they can be 0,1,A or A’ depending on the Boolean function.

I0 I1 I2 I3 I4 I5 I6 I7
A’ 0 1 2 3 4 5 6 7
A 8 9 10 11 12 13 14 15
A’ 1 A’ A 0 1 0 A

Now, the realization is:

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I0 = A’
I1 = 1 8x1 Y
I2 = A’ MUX
I3 = A
I4 = 0
I5 = 1
I6 = 0
I7 = A

B C D Select Lines

Q.65 (i) How many 8 128⋅ RAM chips are required to provide a memory capacity of 2048 bytes.
(ii) How many lines of address bus must be used to access 2048 bytes of memory. How many lines
of these will be common to each chip?
(iii) How many bits must be decoded for chip select? What is the size of decoder? (8)
Ans:
(i) Available RAM chips = 128 x 8
Required memory capacity = 2048 x 8
Number of chips required = (2048 x 8) / (128 x 8)
= 16.
(ii) Chips available are of 128 x 8 in size. It means that total 128 (27) locations are there and each
location can store 8 bits. Thus the total number of address lines required to access 128
locations is 7. As seven address lines can address 27 locations. These seven lines are
 common to all chips.
Now to access 2048 locations, we require 11 address lines, as 2048 = 211 (iii) These higher order
lines will be applied to decoder input. The number of inputs to the decoder will be 11 - 7 =
4. The size of the decoder will be 4x16. These 16 decoder outputs will be connected to the
chip select input of individual chips.
D0 To chip select input of of chip-16

A10 A9 A8 A7
chip-1 D15 To chip select input
A6

4 x 16 Decoder
~
A0To all chips

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Q.66 How many bits are required at the input of a ladder D/A converter, if it is required to give a
resolution of 5mV and if the full scale output is +5V. Find the %age resolution. (8) Ans:
First we find out the ratio of Full scale output to Resolution = 5V / 5 mV = 1000.
Now number of bits = log2 1000 = 10.
Percentage Resolution = 5 mV / 5 V * 100 = 0.1%

Q.67 A 6-bit Dual Slope A/D converter uses a reference of –6V and a 1 MHz clock. It uses a
fixed count of 40 (101000). Find Maximum Conversion Time. (4)

Ans
The time T1 given by
T1 = 2NTC where N = no. of Bits, Tc = time period of clock pulse Given N = 6, TC =
1/ 1MHz = 1 µs.
Therefore T1 = 26 X 10 -6 s = 64 µs.

Q.68 A 2-digit BCD D/A converter is a weighted resistor type with ER = 1 Volt, with R = 1MΩ , Rf
= 10KΩ . Find resolution in Percent and Volts. (5)

Ans
Resolution = 1/22 = 0.25 volts.
As the resolution is determined by number of input bits of D/A converter; For example two
bit converter has 22 (4) possible output levels, therefore its resolution is 1 part in 4 In percent
it will be ¼ X 100 = 25%
In volts, it will be 0.25 volts.
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PART – III

DESCRIPTIVES

Q.1 Distinguish between min terms and max terms. (6) Ans: Distinguish between Minterms and

Maxterms:

(i) Each individual term in standard Sum Of Products form is called as minterm whereas
each individual term in standard Product Of Sums form is called maxterm.
(ii) The unbarred letter represent 1’s and the barred letter represent 0’s in min terms,
whereas the unbarred letter represent 0’s and the barred represent 1’s in maxterms. (iii) If a
system has variables A, B, C then the minterms would be in the form ABC, whereas the
maxterm would be in the form A+B+C.
(iv) The minterm designation for three variable expression be
Y=∑m (1, 3, 5, 7)
Where the capital ∑ represents the product and m stands for minterms.
Decimal number 1 corresponds to binary number 001 or A B C
Decimal number 3 corresponds to binary number 011 or ABC
Decimal number 5 corresponds to binary number 101 or A B C
Decimal number 7 corresponds to binary number 111 or ABC.
Whereas the Maxterm designation for three variable expression be
Y=∏M (0, 1, 3, 4)
Where the capital ∏ represents the product and M stands for maxterms.
Decimal 0 means binary 000 and term is A+B+C
 Decimal 1 means binary 001 and term is A+B+C
Decimal 3 means binary 011 and term is A+ B +C
Decimal 4 means binary 100 and term is A +B+C

Q.2 What are universal gates. Construct a logic circuit using NAND gates only for the expression x
= A . (B + C). (7)

Ans:
Universal Gates: NAND and NOR Gates are known as Universal gates. The AND, OR,
NOT gates can be realized using any of these two gates. The entire logic system can be
implemented by using any of these two gates. These gates are easier to realize and consume
less power than other gates.
Construction of a logic circuit for the expression X = A (B + C) using NAND gates is
Shown in fig.4 (b)

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AC _________
___ AB ____ ____
AB (AB) (AC) = AB + AC

___ AC

Fig.4(b) Logic Diagram for the expression X = A (B + C)

Q.3 Mention the various IC logic families. (7)

Ans:
Various IC Logic Families: Digital IC’s are fabricated by employing either the Bipolar or the
Unipolar Technologies and are referred to as Bipolar Logic Family or Unipolar Logic
Family
I Bipolar Logic Families:
There are two types of operations in Bipolar Logic Families
1. Saturated Logic Families
2. Non-saturated Logic Families
1. Saturated Logic Families: In Saturated Logic, the transistors in the IC are
driven to saturation.
(i) Resistor-Transistor Logic (RTL).
(ii) Direct-Coupled Transistor Logic (DCTL)
(iii) Integrated-Injection Logic (I²L)
(iv) Diode -Transistor Logic (DTL)
(v) High-Threshold Logic (HTL)
(vi)Transistor-Transistor Logic (TTL)
 2. Non-saturated Logic: In Non-saturated Logic, the transistors are not driven into
saturation.
(i) Schottky TTL
(ii) Emitter Coupled Logic (ECL)
II Unipolar Logic Families:
MOS devices are Unipolar devices and only MOSFETs are employed in MOS logic
circuits. The MOS logic families are
(i) PMOS
(ii) NMOS, and
(iii) CMOS
while in PMOS only p-channel MOSFETs are used and in NMOS only n-channel
MOSFETs are used, in complementary MOS (CMOS), both P and N channel
MOSFETs are employed and are fabricated on the same silicon chip.

Q.4 What is a half-adder? Explain a half-adder with the help of truth-table and logic diagram. (10)
Ans:
Half Adder: A logic circuit for the addition of two one-bit numbers is referred to as an half-adder.
The addition process is illustrated in truth table shown in Table 6.1. Here A and B are
the two inputs and S (SUM) and C (CARRY) are two outputs.

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A B S C

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Table 6.1 Truth Table for Half Adder

From the truth table, we obtain the logical expressions for S and C outputs as S = A
B+A B
C = AB
The logic diagram for an Half-adder using gates is shown in fig.6(a)
A

BS

Fig.6(a) Logic Diagram for an Half-adder

Q.5 Using a suitable logic diagram explain the working of a 1-to-16 de multiplexer. (7)
Ans:
Working of a 1-to-16 Demultiplexer: A demultiplexer takes in data from one line and directs it to any
of its N outputs depending on the status of the selected inputs. If the number of output lines
is N (16), the number of select lines m is given by 2m = N.i.e., 24 = 16. So, the number of
select lines required for a 1-to-16 demultiplexer is 4. Table 7.1 shows the Truth Table of
1-to-16 Demultiplexer. The input can be sent to any of the 16 outputs, D0 to D15. If DCBA =
0000, the input goes to D0. If DCBA = 0001, the input goes to D1 and so on.
Fig.7(a) shows the logic diagram of a 1-to-16 demultiplexer, consists of 8 NOT gates, 16
NAND gates, one data input line(G), 4 select lines (A,B,C,D) and 16 output lines (D0, D1, D2
------D16). The 8 NOT gates prevent excessive loading of the driving source. One data input
line G is implemented with a NOR gate used as negative AND gate. A low level in each input

G1and G2is required to make the output G high. The output G of enable is one of the inputs to
all the 16 NAND gates. G must be high for the gates to be enabled. If the enable gate is not
activated then all sixteen de multiplexer outputs will be high irrespective of the state of the
select lines A,B,C,D.

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Demulti Selection Logic Demultiplexer Outputs
plexer Lines
Function D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
Input DCBA

0 0000 DCBA 0111111111111111

1 0001 DCBA 1011111111111111

2 0010 DCBA 1101111111111111

3 0011 DCBA 1110111111111111

4 0100 DCBA 1111011111111111

5 0101 DCBA 1111101111111111

6 0110 DCBA 1111110111111111

7 0111 DCBA 1111111011111111

8 1000 DCBA 1111111101111111

9 1001 DCBA 1111111110111111

10 1010 DCBA 1111111111011111

 11 1011 DCBA 1111111111101111

12 1100 DCBA 1111111111110111

13 1101 DCBA 1111111111111011

14 1110 DCBA 1111111111111101

15 1111 DCBA 1111111111111110

Table 7.1 Truth Table of 1-to-16 Demultiplexer

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G
____
_
_
A _
D(ABCD)

_
G
1

B C _
 _
G
C B 0

___D(ABCD)1

___D(ABCD)2

Data Input _

__
G
__D(ABCD)5
_
A
__D(ABCD)6

_D(ABCD)7
B

___ D(ABCD)8

_
S B __
E D(ABCD)9
L
E __
C C D ( A B C D ) 10
T
_
L _ D ( A B C D ) 11
I C
N __
E D ( A B C D ) 12
S
2 D
_
D ( A B C D ) 13
_
D
A _
D ( A B C D ) 14

D ( A B C D ) 15

_
A

D C
D
D(ABCD)3

___D(ABCD)4
A

Fig.7(a) Logic Diagram of 1-to-16 De multiplexer

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Q.6 . With relevant logic diagram and truth table explain the working of a two input EX-OR gate.
(7)
Ans:
Two-Input EX-OR Gate: An Exclusive-OR (EX-OR) gate recognizes words which have
an odd number of ones. Fig.7(b) shows the logic diagram of an EX-OR gate and Fig.7(c)
shows the symbol of an EX-OR Gate. The upper AND gate gives an output A B and the
lower AND gate gives an output A B .
_ B
A
_
AB
AB
__ Y=AB+AB

_AB
_

Fig.7(b) Logic Diagram of EX-OR Gate

BY

Fig.7(c) Symbol of EX-OR Gate

Therefore, the output equation becomes Y = A B + A B = A EX-OR B = A ⊕ B If both A

and B are low, the output is low. If either A or B (not both) are high (and the other is low),
the output is high. If both A and B are high, output is low. Thus the output is 1 when A and
B are different. Table 7.2 shows the Truth Table for EX-OR gate.
A B Y(AB+AB)

0 0 0

0 1 1

1 0 1

1 1 0

Table 7.2 Truth Table of EX-OR Gate

Q.7 With the help of clocked JK flip flops and waveforms, explain the working of a three bit binary
ripple counter. Write truth table for clock transitions. (14)

Ans:
3-Bit Binary Ripple Counter: In Ripple Counters, all the Flip-Flops are not clocked
simultaneously and the flip-flops do not change state exactly at the same time. A 3-bit

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Binary Counter has maximum of 23 states i.e., 8 states, which requires 3 Flip-Flops. The
word Binary Counter means a counter which counts and produces binary outputs
000,001,010--111.It goes through a binary sequence of 8 different states (i.e, from 0 to
7). Fig.8(a) shows the logic circuit of a 3-bit Binary Ripple Counter consisting of 3 Edge
Triggered JK flip-flops. As indicated by small circles at the CLK input of flip
flops, the triggering occurs when CLK input gets a negative edge. Q0 is the Least
Significant Bit (LSB) and Q2 is the Most Significant Bit (MSB). The flip-flops are
connected in series. The Q0 output is connected to CLK terminal of second flip-flop. The
Q1 output is connected to CLK terminal of third flip-flop. It is known as a Ripple
Counter because the carry moves through the flip-flops like a ripple on water.
Working: Initially, CLR is made Low and all flip-flops Reset giving an output Q = 000. When CLR
becomes High, the counter is ready to start. As LSB receives its clock pulse, its output
changes from 0 to 1 and the total output Q = 001. When second clock pulse arrives, Q0
resets and carries (i.e., Q0 goes from 1 to 0 and, second flip flop will receive CLK input).
Now the output is Q = 010. The third CLK pulse changes Q0 to 1 giving a total output Q =
011. The fourth CLK pulse causes Q0 to reset and carry and Q1 also resets and carries
giving a total output Q = 100 and the process goes on. The action is shown is Table 8.1.The
number of output states of a counter are known as Modulus (or Mod). A Ripple Counter
with 3 flip-flops can count from 0 to 7 and is therefore, known as Mod-8 counter.
Counter State Q2 Q1 Q0

0 0 0 0

1 0 0 1

2 0 1 0

3 0 1 1

4 1 0 0

5 1 0 1

6 1 1 0

7 1 1 1

Table.8.1 Counting Sequence of a 3-bit Binary Ripple Counter

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01 2
0

HIGH CLOCK
Q 0 PULSES
QQ 12 1

FF FF FF 0 12

JJJ

QQQ2

K K K Cr Cr Cr
2
0
1

CLEAR

Fig.8(a) Logic Diagram of 3-Bit Binary Ripple Counter

Ripple counters are simple to fabricate but have the problem that the carry has to propagate
through a number of flip flops. The delay times of all the flip flops are added. Therefore,
they are very slow for some applications. Another problem is that unwanted pulses occur at
the output of gates.

1 2 3 4 5 6 7 8 9 10

CLOCK 1
PULSES
0

Q 1
0
1

0
Q
1
0
 1
Q
2
0
Time

Fig.8(b) Timing Diagram of 3-bit Binary Ripple Counter

The timing diagram is shown in Fig.8(b). FF0 is LSB flip flop and FF2 is the MSB flip flop.
Since FF0 receives each clock pulse, Q0 toggles once per negative clock edge as shown in
Fig. 8(b).The remaining flip flops toggle less often because they receive negative clock edge
from preceding flip flops. When Q0 goes from 1 to 0, FF1 receives a negative edge and
toggles. Similarly, when Q1 changes from 1 to 0, FF2 receives a negative edge and toggles.
Finally when Q2 changes from 1 to 0, FF3 receives a negative edge and toggles. Thus
whenever a flip flop resets to 0, the next higher flip flop toggles.
This counter is known as ripple counter because the 8th clock pulse is applied, the trailing
edge of 8th pulse causes a transition in each flip flop. Q0 goes from High to Low, this causes
Q1 go from High to Low which causes Q2 to go from High to Low which causes Q3

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to go from High to Low. Thus the effect ripples through the counter. It is the delay caused
by this ripple which result in a limitation on the maximum frequency of the input signal.

Q.8 Using D-Flip flops and waveforms explain the working of a 4-bit SISO shift register. (14)
Ans:
Serial In - Serial Out Shift Register: Fig.9(a) shows a 4 bit serial in - serial out shift
register consisting of four D flip flops FF0 , FF1 , FF2 and FF3. As shown it is a positive
edge triggered device. The working of this register for the data 1010 is given in the
following steps.
12 3 _
DATA IN
Q3
D 0 1 2 3
DQ QDQDQ 0 1 2 3

FF FF FF FF
0

CLOCK

Fig.9(a) Logic Diagram of 4-bit Serial In – Serial Out Shift Register

2
1 34
CLK
 DATA 1 0 10
0

Q
1

Q
2

Q
3

Fig.9(b) Output Waveforms of 4-bit Serial-in Serial-out Register

1. Bit 0 is entered into data input line. D0 = 0, first clock pulse is applied, FF0 is reset and
stores 0.
2. Next bit 1 is entered. Q0 = 0, since Q0 is connected to D1, D1 becomes 0. 3. Second
clock pulse is applied, the 1 on the input line is shifted into FF0 because FF0 sets. The 0
which was stored in FF0 is shifted into FF1.
4. Next bit 0 is entered and third clock pulse applied. 0 is entered into FF0, 1 stored in FF0 is
shifted to FF1 and 0 stored in FF1 is shifted to FF2.
5. Last bit 1 is entered and 4th clock pulse applied. 1 is entered into FF0, 0 stored in FF0 is
shifted to FF1, 1 stored in FF1 is shifted to FF2 and 0 stored in FF2 is shifted to FF3.

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This completes the serial entry of 4 bit data into the register. Now the LSB 0 is on the
output Q3.
6. Clock pulse 5 is applied. LSB 0 is shifted out. The next bit 1 appears on Q3 output. 7.
Clock pulse 6 is applied. The 1 on Q3 is shifted out and 0 appears on Q3 output. 8. Clock
pulse 7 is applied. 0 on Q3 is shifted out. Now 1 appears on Q3 output. 9. Clock pulse 8 is
applied. 1 on Q3 is shifted out.
10. When the bits are being shifted out (on CLK pulse 5 to 8) more data bits can be
entered in.

Q.9 With the help of R-2R binary ladder, explain the working of a 4-bit D/A converter (14)
Ans:
R-2R Ladder network method: In a R-2R ladder network method of digital to analog
conversion, irrespective of number of bits of the DAC only two convenient values of
resistors are needed in the ratio of 1:2 as depicted in fig 10(a). An R-2R Ladder Network
based on constant reference current. In the circuit of fig 10(a) points G are actual ground
and points G' are virtual ground. Therefore the potential at all the Gs and G’s is zero.
Between ground (actual or virtual) and node A there are two resistors each of value 2R
in parallel. Therefore this resultant resistance between ground and node A is R and the
current through each of the 2R resistance connected to node A must be same. Let us say
this current is I. Then the current flowing from A to B through the resistor R is 2I. Then
the total resistance from ground to node B through the node A becomes 2R. Also the
resistance directly connected between ground and B is also 2R. So between the node B
 and ground there are two equal resistances in parallel each of value 2R. Therefore, the
resultant resistance is R and the current approaching to node B from both sides must be
equal. Since current approaching from the side of node A is 2I, therefore the current
approaching to the node B from the resistor 2R under it must also be 2I. Hence the total
current approaching the node C from the side of node B is 4I. On the basis of the same
logic the current approaching to node D from the side of node C must be 8I and the
current approaching it form the 2R resistor under node D should also be 8I.
RRR
DCBA

4I8I 2II
I = 16 I ref

Iref

-V
2R 2R
2R 2R 2R 8 I 4 I 2 I I

I out
D -
DDD Virtual Ground Line G '
3 1 +
2 0 G
f

R
GGGG Vo
G'G'G'G'

Fig.10(a) R-2R Ladder Network D/A Converter

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DE09 DIGITALS ELECTRONICS

Whenever any of the bit or bits of the digital input word D3 D2 D1D0 is high, the
corresponding transistor switch is ON i.e. connected to virtual ground and the current of that
vertical branch of the ladder comes from the output, otherwise the current of the vertical
branch comes directly from the actual ground without any effect on the output. Hence the
output current (lout) gives the analog current value corresponding to the digital input word.
This analog current gets converted to the analog voltage Vo.
An R-2R 4-Bit Ladder Network DAC based on reference voltage: An R-2R 4-bit Ladder
Network D/A Converter is shown in fig. 10(b)

Vref

LOW HIGH
DDD
D

0123

R
f
2R 2R 2R 2R

2R
RRRR
 -
ABCD
Vo
+

Fig.10(b) R-2R 4-bit Ladder Network D/A Converter

Proof:
Step 1: If the digital value to be converted to analog value is 0001 i.e.D0 is on the high side
connected to Vref while D1, D2, and D3 are connected to ground. Then the circuit redrawn as
shown inFig.10(c).
R
f

XXXX
1 2 3 4
2R
2R
V 2R 2R 2R
ref
RRRR
ABCD

-
Vo
+ X'X'X'X'
1 2 3 4

Fig.10(c) R-2R Ladder Network D/A Converter when D0 is connected to Vref and
D1,D2,D3 are connected to ground

Applying Thevenin’s theorem at X1,X1’ , the circuit of fig.10(c) becomes the equivalent
circuit shown in fig.10(d)

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