Green University of Bangladesh
Department of Computer Science and Engineering (CSE)
Faculty of Sciences and Engineering
Semester: (Spring, Year:2023), B.Sc. in CSE (Day)
CLP
Course Title: Digital Logic Design Lab
Course Code: CSE-204 Section: 221-DC
Student Details
Name Student Id
Md. Tasnimur Rahman Shakir 221902285
Submission Date : 08.06.2023
Course Teacher’s Name : Md. Sultanul Islam Ovi
[For Teachers use only: Don’t Write Anything inside this box]
Lab Report Status
Marks: ………………………………… Signature:.....................
Comments:.............................................. Date:..............................
J-K Flip Flop
Truth table.
Figure: J-K flip flop truth table
Output Screenshot
Clock X, J = 0, K = 0 and Q = 1
Clock X, J = 0, K = 0 and Q’ = 1, Q = 0.
Reset
Clock 1, J = 0, K=1, Q = 1, Q’ = 0
Set
Clock = 1, J = 1, K= 0 , Q = 0, Q’ = 1
Toggle
J-K Master-Slave Flip-flop