Unit-II

The 8085 MPU architecture: 8085 bus organization, demultiplexing the bus AD7-AD0, generating
control signals. ALU, timing and control unit, instruction register and decoder, register array,
decoding and executing an instruction.

1. Bus organization of 8085 microprocessor

The bus organization of the 8085 microprocessor is the way in which the microprocessor
communicates with other devices in a computer system. The 8085 microprocessor has a 16-bit address
bus, an 8-bit data bus, and various control signals that are used to manage data transfer and other
operations.

The address bus is used to specify the memory location or device with which the microprocessor
wants to communicate. It is 16 bits wide, which allows the microprocessor to address up to 64K bytes
of memory. The address bus is unidirectional, which means that data can only flow in one direction
from the microprocessor to the addressed device.

The data bus is used to transfer data between the microprocessor and other devices. It is 8 bits wide,
which means that data can be transferred in byte-sized chunks. The data bus is bidirectional, which
means that data can flow in either direction between the microprocessor and other devices.

In addition to the address and data buses, the 8085 microprocessor has various control signals that are
used to manage data transfer and other operations. These control signals include the read (RD), write
(WR), and hold (HLDA) signals, among others. The RD and WR signals are used to control data
transfer to and from memory or other devices, while the HLDA signal is used to indicate that the
microprocessor is in a hold state and cannot execute instructions.
Bus is a group of conducting wires which carries information, all the peripherals are connected to

microprocessor through Bus. Diagram to represent bus organization system of 8085 Microprocessor. 

2.  Why use Bus organization in 8085 microprocessors?

 There are several reasons why bus organization is used in the 8085 microprocessors:
1. Memory access: The bus organization is used for accessing memory by transferring the
address of the memory location through the address bus and the data to be stored or
retrieved through the data bus. This enables the microprocessor to read and write data to
and from memory, which is essential for executing instructions and storing data.
 2. I/O operations: The bus organization is used for performing input/output (I/O)
operations by transferring the input/output device address through the address bus and the
data to be input or output through the data bus. This enables the microprocessor to
communicate with peripheral devices such as keyboards, displays, and sensors.
3. Interrupt handling: The bus organization is used for interrupt handling, where the
microprocessor uses the address bus to fetch the interrupt vector and the data bus to fetch
the interrupt service routine. This enables the microprocessor to respond to external
events and perform time-critical operations.
4. DMA operations: The bus organization is used for performing Direct Memory Access
(DMA) operations, where the data transfer between the memory and I/O devices takes
place without the intervention of the microprocessor. This enables high-speed data
transfer between devices and reduces the load on the microprocessor.
5. Control signal transfer: The bus organization is used for transferring control signals
between the microprocessor and other components of the system. This enables the
microprocessor to control the operation of devices and coordinate the execution of
instructions.
There are three types of buses.
 Address bus – 
The address bus is a unidirectional bus that is used to carry the memory or I/O device address to
which the data is to be transferred. The address bus in the 8085 microprocessor is 16-bit wide.
It is a group of conducting wires which carries address only. Address bus is unidirectional because
data flow in one direction, from microprocessor to memory or from microprocessor to Input/output
devices (That is, Out of Microprocessor). Length of Address Bus of 8085 microprocessor is 16 Bit
(That is, Four Hexadecimal Digits), ranging from 0000 H to FFFF H, (H denotes Hexadecimal). The
microprocessor 8085 can transfer maximum 16 bit address which means it can address 65, 536
different memory location. The Length of the address bus determines the amount of memory a system
can address.Such as a system with a 32-bit address bus can address 2^32 memory locations. If each
memory location holds one byte, the addressable memory space is 4 GB. However, the actual amount
of memory that can be accessed is usually much less than this theoretical limit due to chipset and
motherboard limitations.
 Data bus –
The data bus is an 8-bit bidirectional bus that is used to transfer data between the microprocessor and
other components such as memory and I/O devices. It is used to carry data to or from the memory or
input/output devices.
 It is a group of conducting wires which carries Data only.Data bus is bidirectional because data flow
in both directions, from microprocessor to memory or Input/Output devices and from memory or
Input/Output devices to microprocessor. Length of Data Bus of 8085 microprocessor is 8 Bit (That is,
two Hexadecimal Digits), ranging from 00 H to FF H. (H denotes Hexadecimal). When it is write
operation, the processor will put the data (to be written) on the data bus, when it is read operation, the
memory controller will get the data from specific memory block and put it into the data bus. The
width of the data bus is directly related to the largest number that the bus can carry, such as an 8 bit
bus can represent 2 to the power of 8 unique values, this equates to the number 0 to 255.A 16 bit bus
can carry 0 to 65535.
 Control bus – 
The control bus is a bidirectional bus that is used to carry control signals between the microprocessor
and other components such as memory and I/O devices. It is used to transmit commands to the
memory or I/O devices for performing specific operations.
It is a group of conducting wires, which is used to generate timing and control signals to control all
the associated peripherals, microprocessor uses control bus to process data, that is what to do with
selected memory location. Some control signals are:
1. I/O read
 2. I/O Write
3. Opcode fetch

3. DEMULTIPLEXING OF ADDRESS/DATA BUS

Multiplexed AD BUS The signal lines AD0 to AD7 in 8085 microprocessors used for dual purpose. They
carry address bits as well as data bits. This is called multiplexed address/data bus. This bus is used as
low order address bus and data bus. The address bus and data bus are multiplexed to reduce
number of pins in the IC package.

Latch To avoid mixing up of address and data bits this must be de-multiplexed. This can be done with
the help of a latch (74LS373). This bus is connected as input to the latch.
Address Latch Enable (ALE) The Address Latch Enable (ALE) signal is connected to the enable pin (G)
of the latch and output control (OC) pin is grounded.
When ALE goes high, the latch is transparent and it enables lower order address bits (A0 to A7).
When ALE goes low, the latch enables lower order data bits (D0 to D7)

4. GENERATE CONTROL SIGNALS

Functions of Control Pins:
 • IO/M’ – It is a status signal which determines whether the address is for input-output or
memory. When it is high (Logic 1) the address on the address bus is for input-output devices.
When it is low (Logic 0) the address on the address bus is for the memory.
• RD’ – It is a signal to control READ operation. When it is low the selected memory or input-
output device is read.
• WR’ – It is a signal to control WRITE operation. When it goes low the data on the data bus is
written into the selected memory or I/O location.

3:8 Decoder A 3 to 8 line decoder IC 74138 is used. It has 3-inputs and 8-outputs. Three signals
from the 8085 microprocessor namely read (RD’), write (WR’) and Input Output/Memory
(IO/M’) are connected as input to the decoder. Four output signals are taken from output pins of
decoder.
Control Signals The table list input conditions required or different inputs. • S1, S0 – These are
status signals. They distinguish the various types of operations such as halt, reading, instructions
fetching or writing. • RD’, WR’ – Read and write are two basic control signals for reading and
writing operations respectively.
Functions of the control signals
• MEMR’ – It indicates Memory Read operation
• MEMW’ – It indicates Memory Write operation
• IOR’ – It indicates Input Read operation
• IOW’ – It indicates Output Write operation

5. Inside the ALU of the 8085 microprocessors

The arithmetic-logic unit is a fundamental part of any computer, performing addition, subtraction,
and logic operations, but how it works is a mystery to many people. I've reverse-engineered the
ALU circuit from the 8085 microprocessor and explain how it works. The 8085's ALU is a
surprisingly complex circuit that at first looks like a mysterious jumble of gates, but it can be
understood if you don't mind diving into some Boolean logic.

The following diagram shows the location of the ALU in the 8085. The ALU is 8 bits wide, with
the high-order bit on the left. The register file is the large block below the ALU. The registers are
16 bits wide, made up of pairs of 8-bit registers. Surprisingly, the register file has the high-order
bit on the right, the opposite order from the ALU.
The ALU takes two 8-bit inputs, which I'll call A and X, and performs one of five basic
operations: ADD, OR, XOR, AND, and SHIFT-RIGHT. As well, if the input X is inverted, the
ALU can perform subtraction and complement operations. You might think SHIFT-LEFT is
missing from this list. However, it is simply performed by adding the number to itself, which
shifts it to the left one bit in binary. Note that the 8085 arithmetic operations are very basic. There
is no multiplication or division operation - these were added in the 8086.

The ALU consists of 8 mostly-identical slices, one for each bit. For addition, each slice of the
ALU adds the appropriate input bits, computing the sum A + X + carry-in, generating a sum bit
and a carry-out bit. That is, each bit of the ALU implements a full adder. The logic operations
simply operate on the two input bits: A AND X, A OR X, A XOR X. Shift-right simply outputs
the A bit from the slice to the right.

ALU schematic
The following schematic shows one bit of the ALU. The schematic has roughly the same layout
as the implementation on the chip, flowing from bottom to top. Eight of these circuits are stacked
side-by-side, with the low-order bit on the right. Carries flow from right to left, and bits shifted
right flow from left to right.
Negation
Starting at the bottom of the schematic, is the complex gate labeled Negation. This gate
optionally selects a negated second argument by selecting either XN or /XN. (XN is the Nth bit of
the second argument, which I'll call X. The / indicates the complement.) For most of the
discussion below I'll assume XN is uncomplemented to keep things simpler.

Operation
Above the complement selector are a few gates labeled Operation that perform the desired 2-
input operation. The NAND gate on the left generates either A NAND X or 1 based on
the select_op1 control line. The OR gate on the right generates either A OR X or 1, based on
the select_op2 control line. Combining these in the NAND gate yields four different possibilities:
select_op select_op
Result
1 2

0 0 A NOR X

0 1 0

1 0 A NXOR X

1 1 A AND X
Note that instead of OR and XOR, the complemented value is produced by this circuit. This will
be fixed in the next step.

Combine with carry

Above the operation circuit is the next block of gates labeled Combine with carry that generates
the ALU output by merging the carry-in with the operation value via XOR.

To understand this circuit, first consider the following simple XOR circuit, which is used a couple
times in the ALU. It can be understood fairly simply: if both inputs are 0 (top) or both inputs are
1 (bottom) then the output is 0.

Ignoring the shift_right circuit for a moment, the block of gates is simply the XOR circuit above.
Note that XOR with 0 is a no-op, while XOR with 1 complements the value. And A XOR X
XOR CARRY is the low-order bit of adding A, X, and CARRY.

The key point of this circuit is that the incoming carry is generated with the proper value to
convert the operation output into the desired final result. The incoming carry /carry(N-1) is either
0, 1, or the complemented carry from bit N-1 as appropriate.

Op Operation output Carry Result

or A NOR X 1 A OR X

add A NXOR X /carry A XOR X XOR CARRY

xor A NXOR X 1 A XOR X

and A AND X 0 A AND X

shift right 0 0 A(N+1)

complemen
A NOR /X 1 A OR /X
t

subtract A NXOR /X /carry A XOR /X XOR CARRY

Note that the carry-in line must have the right value in order to generate the appropriate output.
For addition it passes the inverted carry from one bit to the next. But for OR, XOR, the line is set
to 1. And for AND and SHIFT_RIGHT it is set to 0. As will be seen below, the carry circuitry
generates the right value for the right operation.

The final aspect of this circuit is the shift-right circuit. With a 0 op input, 0 carry input, and
shift_right set, the output is simply the bit from the right: A(N+1).

Generate carry
The circuit on the left, labeled Generate carry generates the carry out. It can generate three
different outputs: 1, 0, or the (complemented) carry from the sum. If  select_op2 is set, it will
force the carry to 0. Otherwise if force_ncarry_1 is set, it will force the carry to 1. Otherwise, the
carry is generated for the sum of A + X + carry-in through straightforward logic: If the carry-in is
set, and one of the inputs is set, there will be a carry out. If both input bits are set, there will be a
carry out.

Flags
The 8085 has a parity flag, which is 1 if the number of 1 bit is even, and 0 if the number of parity
bits is odd. The parity flag is generated by XORing all the result bits together (and
complementing). Each bit is XORed with the lower-order parity value by the parity circuit near
the top of the schematic. The XOR circuit is the same circuit described above.

The zero flag is computed by a simple circuit: each result bit drives a transistor that will pull the
zero-line low if the bit is set. This forms an 8-input NOR gate, spread across the ALU.

The control lines

As seen in the schematic, the 8085 uses multiple control lines to control the activity inside the
ALU. In total, the ALU provides 7 different operations and the following table summarizes the
control lines that are used for each operation. It also lists the opcodes that use each ALU
operation.
Operati select_ select_ select_ shift_r force_nca
Opcodes
on neg op1 op2 ight rry_1

or 0 0 0 0 1 ORA, ORI (and default)

INR,DCR,RLC,DAD,RAL,DAA,A
add 0 1 0 0 0 DD,ADC,ADI,ACI (and
undocumented LDSI,LDHI,RDEL)

xor 0 1 0 0 1 XRA,XRI

and 0 1 1 0 1 ANA,ANI

shift
0 0 1 1 1 RRC,RAR (ARHL)
right

comple
1 0 0 0 1 CMA
ment

SUB,SBB,SUI,SBI,CMP,CPI
subtract 1 1 0 0 0
(DSUB)

The ALU control lines are generated from the opcode by the programmable logic array.
Specifically, they are outputs from PLA F, which is to the right of the ALU. More details are
in my article on the PLA. The ALU has additional control lines to set up the registers, initialize
the carry bits, and set the flags.

6. Timing and Control Unit of 8085

We use Timing and Controlling unit in 8085 for the generation of timing signals and the
signals to control. All the operations and functions both interior and exterior of a
microprocessor are controlled by this unit. X2 and CLK output pins: To do or rather perform
the operations of timing in the microcomputer system, we have a generator called clock
generator in the CU of 8085. Other than the quartz crystal the complete circuit of the
oscillator is within the chip. The two pins namely X1 and X2 are taken out from the chip to
give the connection to the crystal externally. We connect a capacitor of 20pF between the
terminal X2 and ground just to analyze if the crystal is getting started. The frequency of the
crystal is divided by 2 which divides the counter of the unit of control by 2. Internally 8085A
works with a frequency of 3 MHz internally with clock frequency. Hence a crystal of
frequency of 6-MHz crystal gets connected between X1 and X2. Every operation in the
entire 8085 system occurs with the given synchronization process with the clock. There are
Peripheral chips like 8251 USART, which does not operate until a small clock signal is in
need.
An LC tuned circuit can also be connected between X1 and X2. In some systems carrying
low cost, a resistor gets connected between X1 and X2, and the capacitor between X1 and
ground for the generations of number of oscillations. Moreover, to get a very good stability
we prefer to use quartz crystal. With the internal frequency to be 3 MHz, the period of clock
should be 333 ns. Moreover, the 8085 clock strikes once in every 333nS but our watch
strikes once in a second. The cycle of the clock of 8085 microprocessor is termed as
a T state, where t stands for timing.
The minimum frequency required for the operation of 8085 internally is 500 KHz i.e. 1
MHZ. But the point to be noted that at low frequencies every information from the registers
gets lost. It is so since the registers are dynamic in nature and are cells of Random Access
Memory, which are to be refreshed in a continuous manner.
Status signals IO/M*, S1 and S0: We require five machines cycles to carry the operation
procedure. Specific operations are performed by each machine cycle, like reading and
writing from memory. A particular machine cycle needs a fixed cycles of clock, the
minimum is three for a particular clock. The call the first clock cycle is as T1 and the second
to be T2, here the period of time is T.
The status signals IO/M* describes the type of machine cycle which 8085 microprocessor
executes. These status signals get emitted by the 8085 processor during T1 phase of the first
machine cycle.
7. Instruction Register and Instruction Decoder
Instruction Register (IR)
The purpose of Instruction Register is to shift in instruction through TDI and having the provision to
store the instruction till a new instruction is fully shifted in.
Typically an IR has two registers inside it as shown below. The Hold Register stores the previous
instruction and the Shift Register is used to shift-in the next instruction without affecting the previous
instruction’s execution.

Figure 1: A top level view of Instruction Register (IR)

The control signals to the Instruction register originates from the TAP controller and depending upon
the FSM state can either cause a shift-in/shift-out through the Shift Register (serial update operation
in Shift-IR state ), or cause the contents of the Shift Register to be passed across to the Hold Register
(parallel update operation in Update-IR state).
Suppose we have a 4 bit instruction register and we want to load a value, say 1100 to it. Then we have
to follow the steps below –
  1.  Move to “Shift-IR” state from the initial “Test Logic Reset” state by applying –
       TMS = 0 (1st clock)
       TMS = 1 (2nd clock)
       TMS = 1 (3rd clock)
       TMS = 0 (4th clock)
       TMS = 0 (5  clock)
th

  2.  While in “Shift-IR” state, keep TMS = 0 for the next 3 clock cycles to serially shift-in the data
(1100) through TDI.
NOTE: 3 clock cycles to shift 4 bits data because the LSB (logic 0) of data 1100 was made available
in the TDI port after 4th clock, thus in the 5th clock itself the LSB was loaded when the FSM entered
the “Shift-IR” state. The MSB (logic 1) of data 1100 was shifted in 8 th clock. You can refer the
example shown here  for a better understanding.
  3.  Move to “Update-IR” state from the “Shift-IR” state by applying –
       TMS = 1 (9th clock)
       TMS = 1 (10  clock)
th

When the FSM entered the “Update-IR” state, the data (1100) in the Shift Register was loaded to the
Hold Register in parallel. Thus the instruction is now made available for the instruction decoder.
Instruction Decoder
The instruction from the Instruction Register (IR) is fed to a decoder logic, which selects the Data
Register for JTAG operation. We assign a unique value (or opcode) to each and every Data Register in
the JTAG. In order to select a Data Register, we load the IR with the corresponding opcode and the
Instruction Decoder decodes the value and establishes an access path between the TDI/TDO and the
required Data Register.
Suppose we have two Data Registers DR-1 and DR-2, and a 4 bits Instruction Register in our JTAG.
So we will assign opcodes to the Data Registers and specify the same to the IR –
       DR-1 (say opcode = 4’b0010)
       DR-2 (say opcode = 4’b0011)
NOTE: 4 bits opcode, because the IR is 4 bits.
If we want to access DR-2 for any JTAG operation, then we have to load the instruction register with
a value 4’b0011 and the instruction decoder will be able to decode this value to select the DR-2.

8- Decoding and Executing

The CPU executes the instructions regarding a program stored in the memory. There’s one general
rule applied to all these instructions being carried out in the processors. The execution definition is
outlined by a cycle of instructions conducted in the particular execution. This cycle, better known as
the instruction cycle, has three stages – fetch, decode and execute.

What is the Instruction Cycle?

The execution instructions define the instruction cycle. This is the thorough methodology computer
processors use for executing a given instruction. Many times processors can be compared to
combustion engines. Both follow a process continuously being carried out to fetch the desired
outcome. Every processor shows a three-step instruction cycle. These three steps of the instruction
execution cycle are,
1.Fetch:  
The processor copies the instruction data captured from the RAM. 
2. Decode: 
Decoded captured data is transferred to the unit for execution.
3. Execute: 
Instruction is finally executed. The result is then registered in the processor or RAM
(memory address). 

First step: Fetch (instruction cycle)

According to the execution instruction definition, the instruction cycle’s first step is to
capture or fetch the instruction. This instruction in the fetch stage is captured from RAM.
This memory is assigned to the processor through various units and registers; they are:
 Program counter: 
It works by pointing towards the next memory line, where the next instruction for the
processor is stored. 
 Register (memory address): Responsible for copying PC content and sending it to
the RAM. This is done through the CPU’s address pins. 
 Register (memory data):  
It takes the responsibility of copying the memory address to the internal register. 
 Register (instruction): 
It has involvement in the last step of the fetch phase. It is where the instruction is written. The
control unit from here copies the content for carrying out the instruction cycle.

How does the control unit work?

As discussed earlier, the control unit plays an important part and is present in a processor.
The tasks that it performs are,
 The control unit is responsible for controlling both internal and external movements
of the data in the processor. Also, it is responsible for controlling the movement of the
data in various subunits involved
 Various units of the capture stage of an instruction cycle are considered part of the
hardware. This hardware is called a control unit or a processor’s front-end
 It is responsible for interpreting various instructions and sending them to the
execution units 
  Communicate that data for instruction to the various ALUs and execution units at
work
 It is the part of the processor that captures and decodes the instruction for execution.
Also, it is responsible for writing results on the registers and even in the respective
addresses of the RAM

Second step: Decode (instruction cycle) 

There are various instructions, and we can never be sure which instruction belongs to which
execution unit. Decoding sorts this out. A decoder is responsible for taking in the instruction
and decoding it to assign the respective execution unit to complete the execution instruction
cycle. 
The easiest example of how an instruction works is visualising them as trains that keep
circulating through a complex railway network. The control unit here acts as the station at the
terminal and, therefore, it is held in charge of being the execution unit to solve the given
instruction. 

Third step: Execute (instruction cycle) 

The last stage of the execute instruction definition is to execute. It involves executing the
given instruction that was fetched at the first stage. No two instructions ever get resolved in
the same manner because their ways of utilising the hardware depend on their functions.
There are four types of instructions that are generally present,
 Bit movement instructions: 
This instruction involves the manipulation of the bits’ order. These bits contain the data. 
 Arithmetic instructions: 
These are the instructions that involve logical as well as mathematical operations. They are
most often solved in arithmetic logical units (ALUs)
 Jump instructions: 
The code in this instruction is used recursively because the value for the next program
counter is changed.
 Instructions to memory: 
These instructions involve the processor writing as well as reading the information from the
memory of the system. 
On completing the cycle, that is, the instruction being executed, a new instruction gets
fetched, and the cycle continues.