(MCS-51)

10.1 INTEL 8051 SERIES OF MICROCONTROLLERS

The 8051 series of microcontrollers were developed in the year 1980. They are the
tion of 8-bit microcontrollers. They are faster and more powerful than Intel
set and
8048 second
series generaf-
(1976)
microcontrollers. They have been provided with improved instruction
containa
additional electronic circuitry for specific functions. The 8-bit microcontrollers are used nu
involving limited calculations and relatively simple control for avariety
of applications strategies..They are used
for industrial and commercial control applications, appliances control,
8051 contains Boolean processor, full duplex serial port and power saving instrumnentation,
circuitry in etc. Theto
essential components such as 8-bit CPU, RAM, ROM/EPROM/OTPROM, timer/counteraddi andtion
lel I/O lines.This series has a wide variety of versions with some of special functions such as DMA
channels,
of its
A/D converter, pulse-width modulation, watch-dog timer, etc. Table 10.1 shows the detsi
family members.
 External
Interrupts

4/8/16/32/
Interrupt ROM/EPROM/ 128/256/512/ Timer
control OTPROM 1KB RAM

CPU

Bus VO Ports
FullDuplex
OSC Serial Port
Control

HE
PO P2 P1 P3 TxD RxD

Address/
Data

8051.
Fig. 10.1 Block Diagram of Intel
8051. The common features of 8051 series of
diagram of Intel
Fig. 10.1 shows the block
microcontrollers are:
(0 8-bit CHMOS CPU contain 256 bytes on-chip RAM which acts as
Most of the microcontrollers of 8051 family 8XC251SP/SQ contain 512 bytes, and the
(1) 8XC51RA/RB/RC and such as 80C51BH,
memory. The microcontrollers
data
contains 1 KBRAM., A few entry level
8XC251SA/SB
80C31BH and 87C51 contain 128 bytes RAM. capacity varies from version to version, see
ROM/EPROM/OTPROM. The ROMless versions external
case of
) 4/8/16/32 KB are also available. In applicatiorn.
Table 10.1. ROMless versions
depends on the particular timer/counters. The
isused. The capacity 16-bit
Program memorymicrocontrollers contain 3 multimode 2timers//counters.
(iv) Most of the contain
80C51BH, 80C31BH and87C51
i.e. four 8-bit ports. The
lines
8XC152JA/JB/JC,microcontrollers contain 32 I/0 controller contains 5 or7I/0 ports.
(o) Most of the communication
universal I/Oports.
8XC152JA/JB/JC/JD, thecontroller contains 3 multifunctionneeded in industrial control
The 8XC51SL, keyboard It is
capabilities.
(pi) (single-bit logic)
Boolean processing8 8XC152JA/JB/JC/JD contains UART.
applications. The may be 5, 6, 7,10 or 15.
(oi) Multimode,fulll duplexserial port.differs from versionto version.interrupt
It
sources are : one
sources important
(oii) The number of interrupt proyided. The
interrupt priorityhas been
evel
 from the serial port when a
transmission or reception is Complete, two
from input pins INTO and INT1,
etc. from timners, twy
(ix) 64 KB external datamemory space.
(a) 64 KBexternal program memory space.
(xi) Power saving modes.
Some versions are designed for specific applications, and therefore, they are provided wit h spe
cial features requied by the typical applications. Special features are :
(i) Pulse-width modulation. Afew versions have this feature, for example,

(i)
8XC51GB, 8XC151SA/SB and 8XC251SA/SB/SP/SQ.
DMA channel. Afew versions havethis feature, for example
(ii) A/D converter. Afew versions have A/D converter, for example, 8XC51GB.
,8XC51FA/F
8XC152JA/JB/JC/JD.
B/FC
ir) Watchdog-timer. It is adedicated internal timer which resetsthe:system when the
does not operate properly. Some versions have been provided with this
example, 8XC51GB,8XC51RA/RB/RC, 8XC151 and 8XC251. featsofture,waefor
(o) Programmable counter array to provide features like high-speed output, compare/cap
operation, etc. Some versions have this feature, for example, 8XC51FA/FB/FC, 8XCS1C
8XC151 and 8XC251.
The 8051 microcontrollers have two versions : COMMERCIAL and EXPRESS. The onerahns
temperature range for commercial versions is 0°C to 70°C and that for the express version is 40°C to
+85°C.

10.1.1 Registers
The 8051 is an accumulator based microcontroller. Its registers are :
PSW, register B,8-bit stack pointer, 16-bit data pointer, program register A (an accumulator),
16-bit timer registers for timer/counters, instruction register, control counter, program address register,
serial data buffer, capture registers, special function registers, etc. registers, RAM address register,
and divide operations. For other instructions it is used as Register Bis used during muliply
another scratch pad register. The daa
pointer consists of ahigh byte and a low byte. It holds 16-bit address.
or two independent 8-bit registers. The serial data It can beused as a 16-bit register
buffer and a receive buffer register. buffer is actually two separate registers :atranst
The 8051 has been provided with 4 banks of
registers, RO-R7. Physically these banks occupy the working registers. Each bank consists of 8wOTKIS
hex). Only one bank is active at a time. Bits 3 first 32 bytes of on-chip data RAM (address
and 4 of PSW
As the 8051 is a bit as well as
byte microcontroller, some ofdecideits
which bank is to be made acue
addressable. registers are both bit as weu d
Besides working registers, there are a
are both bit-and number of special function registers (SFRs). Some o
Symbol byte-addressable.
Name
Alist of SFRs is given
below:
ACC Address
B Accumulator E0
Remarks
Both bit-and byte-addressable
Bregister
PSW FO
SP
Program Status Word DO
do
Stack Pointer do
DPTR Data Pointer (DPH & 81
PO Port 0 DPL) 83 and 82 Consists of DPH and DPb
P1 Port 1 80 and byte-addressable
90
Both bit-and
do
 Port 2
A0 do
Port 3
BO do
Interrupt Priority Control
B8
Interrupt Enable Control do
IE Serial Control A8 do
KON
98
Serial Data Buffer Both bit-and byte-addressable
SBUF 99
Power Control
PCON 97
TMOD Timer/Counter 0&1 Mode Control 89
T2CON Timer/Counter 2 Control
88
Both bit-and byte-addressable.
TCON Timer/Counter 0&1 Control It is in 8052 only.
C8
TLO Timer/Counter 0(low byte) 8A
THO Timer/Counter 0 (high byte) 8C
Timer/Counter 1 (low byte) 8B
IHI Timer/Counter 1 (high byte) 8D
Timer/Counter 2 (low byte) CC
TH2 Timer/Counter 2(high byte) CD
RCAP2L Timer/Counter 2Capture CA
Register (low byte)
RCAP2H
Timer/Counter 2Capture CB
Register (high byte)
Description of some registers are given below:
Data Pointer. It consists of DPH (a high byte)and
be used as a 16-bit register or as two DPL(a low byte). It holds 16-bit address. It can
PO, P1, P2 and P3. These are SFRindependent &-bit registers.
latches for Port 0, 1,2 and 3 respectively.
Serial Data Buffer. It consists of two separate
bufer register. registers, a transmit buffer register and a receive
Timer Registers. (TLO,THO), (TL1, TH1) and (TL2, TH2) are
are 16-bit counting registers for Timer/Counter 0, 1 and 2 register pairs. These registerpairs
respectively.
Capture Registers. RCAP2Land RCAP2H is a register pair. These registers are
for
the Timer2 cpature capture registers
mode.
Control Registers. Special Function Registers IE, IP TMOD, TCON,T2CON and SCON hold
Control and status bitsfor the interrupt
system, timer/counters, and the serial port. PCON is power
Oregister. The 8051 is provided with power-saving modes of operation. For applications where
rCOnsumption is critical, both HMOSand CHMOS versions provide reduced power modes of
Operation. For CHMOS version of the 8051 microcontroller, the reduced popower modes, Idle and
Power
able. Down modes sarethe standardfeatures. In HMOS versions only reduced power mode is avail-
ig, 10.PSW (Program Status Word). PSW register contains program status information as shown in
2. Its bitssare indicated as PSW.0, PSW.1, PSW.2,..PSW.7.
7 6 5 4 3 2 1 0 Bit No

CY AC FO RS1 RSO OV P Status information

Fig. 10.2 PSW: Program Status Word Register

 It is for parity status (parity flag, P)
Bit No. 0, PSW.0. Reserved
Bit No. 1, PSW.1.
(OV)
Bit No. 2, PSW.2.Overflow flag working register bank.
Bit No. 3, PSW:3. (RS0)¬ These bits are to select
Bit No.4, PSW.4.(RS1)
Bit No. 5, PSW.5. It is flag 0 (FO) available to users for general purpose.
Bit No. 6, PSW.6. It isauxiliary carry flag (AC)
Bit No. 7, PSW.7.It iscarry flag (CY) 8-bit
Stack Pointer(SP). Intel 8051 microcontroller contains an stack pointer register.
mented before data is stored during PUSH and CALL operations. It is decremented Itis incre
RET (Return)operation takes place. Any area of on-chip RAM can be used as stack when POP or
Program Counter (PC). The Intel 8051 microcontroller contains a 16-bit Program
register. It points to the address of the next instruction of the program, which is to be
Counter
executed. It is automaticallyincremented after fetching an instruction. It keeps the track of fetched and
addresses of the instructions in the program being executed. It is affected
structions.
by JUMP and memory
CALLi
10.1.2 Pins of Intel 8051
Fig. 10.3 shows the pin diagram of Intel 8051 Microcontroller.
P1.01 40

P1.1|2 39 PO. 0/ADO

P1.2 3 38 P0.1/AD1
P1.34 37 PO.2/AD2
P1.4 5 36 PO.3/AD3
P1.5 6
35PO.4/AD4
P1.6|7
34 PO.5/AD5
P1.7 8
33PO.6/AD6
RST9
RXD/P3.010 Intel 8051
32PO.7/AD7
31 EA
TXD/P3.11 11
30 ALE
INTOP3.212 29 PSEN
INTi/P3.313 28P2.7/A15
TO/P3.4|14
27 P2.6/A14
T1/P3.515
WRVP3.6 |16 26P2.5/A13
RD/P3.7 17 25P2.4/A12
24 P2.3/A11
XTAL2 18
XTAL119 23P2.2/A10
Vgs 20 22P2.1/A9
21P2.0/A8
Flg.
10.3 Pin Diagram of Intel 8051 Microcontroller.
Pins 1-8 are for the
Port 0. The alternate Port 0, Pins 10-17 for Port 3, Pins 21 - 28 for Port 2 and Pins 32--39Subserforthe
tion). function of Pins 10-17 are given Lines Next
RST (Pin 9). It is the under the heading of I/0
XTAL2 (Pins 18). It isresetting pin offorinverting
the output the deviceamplifier
(8051). which is a Oscillatat
When external clock is used, it is part of the on-chip oscl
left
unconnected.
 NIC
(Pin19), It is input to the
When external clockis used, it isinverting amplifier
XTALI which is a part of the on-chip
inuit.
20). It is the circuit ground.
connected
All the
to the external oscillator signal. oscillator
Vss(Pin
I is for power supply, +5V.
voltage
are specified with respect to it.
VcclPin40).It
PSEN(Pin 29). It is program Store Enable. It is output control signal. It is aread
programmemory. strobe to external
ALE(Pin 30). It is
Address Latch Enable output (control signal) for
accessesto external memory.
latching the lowbyte of the
ddress during
EA(Pin 31).Itis External. Access. It controls the access of program mernory. See Table 10.5.
j0.1.3 VO Lines
Mostofthe S051 microcontrollerssccontain four &-bit parallel ports: P0, P1, P2 and P3. Altogether
ther are 32 I/O lines. All ports in 8051 are bidirectional. The I/0 lines of 8051 are not simply
nput/outputlines,1rather they are: multifunctional lines. If an application does not need any external
memory besides s on-chip memory, then all four ports can be used as input/output ports. If external
nemory is used, then Port 0 and Port 2 act as a multiplexed address/data bus. When external
memory is employed,two lines of Port 3 are used to generate the RD and WR signals. Two pins of
Port 3act as RXD and TXD for serial data transmission. Two pins of Port 3can be used as external
nput for timers, one for Timer 0 and one for Timer 1. Two pins of Port 3 can be used as external
interrupts.
Alternative function of port pins are given below:
P1.0 T2 (Timer/Counter 2 external input). P1.0 provides alternative function only on
the 8052 microcontroller.
P1.1 T2EX (Timer/Counter 2 capture/reload trigger). P1.1 provides alternative
function only on the 8052 microcontroller.
P3.0 RXD (Serial input port)
P3.1 TXD (Serial output port)
P3.2 INTO(External interrupt)
P3.3 INTI (External interrupt)
P3.4 TO(Timer/Counter 0 external input)
P3.5 T1 (Timer/Counter 1external input)
Strobe)
P3.6 WR External Data Memory Write
Read Strobe)
P3.7 RD (External Data Memory output driver and an input buffer. The
a latch (SFR PO-P3), an accessing
are employed while
cn port of Intel 8051 consists of and the input buffer of Port 0,time-multiplexed
output drivers of Ports 0and Port 2 with the byte
external memory address, addressis of 16 bits.
extbeingernal Port 0 sends 8 LSBs of address when
memory.
written or1read. Port 2 sends 8 MSBs of the external memoryother words Port 2acts as I/Oport.
In
emit the P2 SFR content.
Otherwise the Port 2 pins continue to
sources dif-
10.14 The 8051 number of interrupt fromthe
Interrupts
The 8051 microcontrollers have 4-level to priorityinterrupts.
The important
The
interrupt sources are:
the
one
interrupts can
fers version to version. It varies
from from 5 15.
interruptsINTOand
INT1. Each
function
of
register IE (Inter-
serial port, external
two from timers, two fromsetting/clearinga bit in the which disablesallthe interrupts.
special
individually
rupt be enabled/disabledby b contains a global disable bit,
Enable). The IE register also
 Each interrupt can also be programmed to one of the priority-level scheme by setting/|
Priority Register). Alow-priority interrupt
upted by ahigh-priority interrupt, but itcan not be interrupted by another be intbierts
can clearing
Ahigh-priority interrupt cannot be interrupted by a low-priority interrupt.
The 8051 microcontroller has five vectored interrupt sources namely, external
low-priority inter up.
through theinput pinINTO, externalinterrupt I through the input pin INT1, timer/ counter o
rupt, timer/counter 1interrupt and serial port interrupts. An interrupt for which 0inter-int er upt
hardware automatically transfers the program execution to aspecific memory location
vectored interrupt. The specic memory location corresponding to each microisckonownas
each vector interrupt has a ntrol er's
dress as shown in Talble 10.2. For each vectored interrupt there is an interrupt flag which is set ad-
microcontroller's hardware detects the occurrence of an interrupt. Corresponding to aboye n
tioned vectored interrupt sources,the 8051 has interrupt flags IE0, JE1, TFO, TF1, RI and TI
tively. Among these flags IE0, IE1 TFO and TFl are bits of the Timer/Counter Control Register TCO respec
as shown in Fig. 10.8. RI and TI are the bits of Serial Port ControlRegister SCON. RI is receive in
rupt flag and T1transmit interrupt flag. These are connected through an OR gate and hence any on
of Rlor Tl can send an interrupt signal to the microcontroller for the serial port. The other versin
of S051 series of microcontrollers have more number of interrupt sources for example 8052 contbi
6 interrupt sources, 8XL51 FA/FB/FC has 7interrupt sources and 8XC51 GB has 15. In 8052, Timer)
interrupt is generated by the logical OR of TF2 and EXF2. The flags TF2 and EXF2 are not clearedby
microcontroller's hardware when the service routine is vectored. The service routine determines
whether TF2 or EXF2 has generated interrupt and the flag is cleared by software. Table 102shos
interrups, flags,vector address and priority of interrupts within the same level.
Table 10.2 Details of Interrupts
Interrupt Flag Vector Address Priority within level
External Interrupt 0, INTO IEO 0003 Highest
Timer/Counter 0 Interrupt TFO 000B
External Interrupt1, INT1 IE1 0013
Timer/Counter1 Interrrupt TF1 001B
Serial Port, R1 or T1 R1 or T1 0023
Timer/Counter 2 Interrupt TF2 or EXF2 002B Lowest

The external interrupts INT0 and INT1 can be programmned to act as afalling edge triggeredor
low level triggered interrupt by setting and clearing the bits ITO and IT1 respectively inthe register
TCON. f an external interrupt is made edge triggered IEO or IE1, interrupt tlag is cleared by
microcontroller's hardware when the service routine is vectored. If the external interruptislevel
triggered, IEO or IE1 is controlled by external requesting source of interrupt. The externalinterrupt
source has to hold the interrupt request until the requested interrupt is actually generated.Thenit
has to deactivate the request before the interrupt service routine is completed. When the service
routine is vectored, the interrupt flag is cleared by the
Enabling of 8051 Interrupts. The 8051 contains external interrupt requestngs It:is a
special

function register (SFR). Each of interrupt sources canan be interrupt enable register /IE.
disabled
by set

individually enabled which

ting/clearing a bit in the interrupt enable
can disable all interrupts, if it is
EA
register IE. It also contains a global disable bit, Toenable
an interrupt, the bit EA and the bitmade equal to 0i.e. EA=0. It is a bit addressable register.
10.4:showsthe
details of bits of register IE. corresponding to the desired interrupt is set. Fig.
 MCROCO

6 5 2 1
7 Bit No.
X ET2 ES ET1 EX1 ETO ÉX0
EA Syrnbol
Fia. 10.4 Interrupt Enable Register IE (Bit Addressable)

It is for External
Interrupt 0(INTO). When EX0 = 1, INTOis enabled provided EA
BitNo.0 EXO. disabled.
-0.INTO is
When EX0-0,
ETO. It is for Timer 0 Overflow interrupt. If ETO=1, the Timer 0 Overflow interrupt is
BANo. provided EA =1. IfETO= 0., Timer 0 Overflow interrupt is disabled.
1,
ealbled,
EXI. It isfor External Interrupt 1(INT1). If EX1 =1, INT1is enabled, providedEA =1. If
No. 2, disabled.
BI
EN=0,INTIis for Timer 1Overflow interrupt.If ET1 =1, Timer 1 Overflow interrupt is enabled,
3,ET1.Itis
No. =0,Timer 1 Overflow interrupt is disabled.
dEA=1.lfETI
BI
provided
ES. It is for serial port interrupt. If ES =1,thesserial portinterrupt is enabled, provided EA
BitNo.4, port interrupt isdisabled.
CES = 0, the serial
interrupt. If ET2 = 1, the Timer 2 Overflow or
ET2. Itis,for Timer 2 Overflow or captureOverflow
5,
Bit No.
interruptis
enabled. If ET2 =0, the Timer 2 or capture interrupt is disabled.
capture
Reserved.
BitNo.6. disable bit..If EA =0,all interrupts are disabled. If EA =1, each interrupt
EA. It is a global
Bit No. 7, or clearing its enable bit.
re is individually enabled or disabled by setting
Priority. By setting or clearing a bit in the special function register IP, the user can
Interrupt level or low-priority level. Alow-priority
program each interrupt individually in either high-priority
interrupted by a high-priority interrupt, but it can not be interrupted by any other
interrupt carn be interrupt can not be interrupted by alow-priority interrupt.
low-priority interrupt. Ahigh-priority
of various interrupts of Intel 8051series of microcontrollers. If
two
Table 10.2 shows priority level and another interrupt of
(i.e. one interrupt of high-priority level
interrupts of different priority level
simultaneously, the interrupt of the higher-priority level will be served first.
low-priority level) occur occur simultaneously, an internal polling determines
priority level given in the Table 10.2
i two interruptsof the same level on the basis of the priority level
Wnuch interruptis of higher-priority
details of the bits of Interrupt Priority
Register, IP.
Fig. 10.5 shows the Bit No.
3 2 1
7 6 5 4
PX0
Symbol
PT1 PX1 PTO
X X PT2 PS

Priority Register
Fig. 10.5 Interrupt PX0= 0,
priority level. PX0 = 1, higher-priority.
Bit No. 0,PX0. It is for External Interrupt 0 (INTO)
higher-priority. PTO =0, lower-
lower-priority.
Bit No, 1,
PTO. It is for Timer 0Interrupt
priority level. PTO =1,
higher-priority. PX1 = 0,
priornNo.ity.2,
Bit PX1. It is for External Interrupt 1(INT1) prioritylevel. PX1 = 1,
lower-
higher-priority. PTl =0,
ower-priority .
Bit No. 3, priority level. PT1 =1, lower-priority.
PT1. It is for Timer 11Interrupt higher-priority. PS =0,
piority. level. PS=1,
BitNo.4,PS. It is for Serial PorttInterruptpriority