M.Sc.

PHYSICS - I YEAR
DKP13 : DIGITAL ELECTRONICS
SYLLABUS

UNIT I Number systems

Binary coded decimal number system, Grey code, Grey code to Binary
conversion, Binary to Grey code, Excess 3 code, Decimal to excess 3 code, ASCII
code.
Universal logic gates: NAND and NOR gates as universal logic gates –
Simplification of logic circuits – De Morgan’s laws – Boolean laws – Karnaugh
maps – three variable and four variable maps – max and min terms.

UNIT II Arithematic circuits

Half adder – Truth table and circuit – Full adder – Truth table and circuit – Four bit
adder – Half subtractor – Full subtractor – Multiplexer: Four input multiplexer –
Applications of Multiplexer – demultiplexer – Decoders 2 to 4 decoder – BCD to
seven segment decoder – encoders.

UNIT III Flipflops

Introduction – NAND LATCH, J K flipflop – J K Master – slave flipflop – D
flipflop and T flipflop – Registers and Counters: Shift registers – serial in –
parallelout, serial in – serial out, parallel in – serial out, parallel in – parallel
out shift registers – wave forms for the above – Counters – up counters, down
counters, decade counters, timing sequences, Mod – n counters.

UNIT IV MULTIVIBRATORS
Classification of multivibrators – Astable, monostable, bistable multivibrators
using operational amplifier.
D/A and A/D converters: Binary weighted register D/A converter using Op-Amp
– R-2R ladder D/A converter with Op-Amp – Analog to Digital converters (ADC) –
their characteristics.

UNIT V SEMICONDUCTOR MEMORIES

Memory cell unit – ROM, RAM – Their classifications – ROM, PROM,
EPROM, EEPROM, RAM,Static RAM, dynamic RAM, Memory read and
memory write operations – Flash memory - Charge coupled Device (CCD).

Books for Study and Reference:

1. Digital Electronics principles and applications – Soumitra Kumar Mandal -
Tata MCGraw Hill publications – New Delhi.
2.Integrated Electronics – Digital and Analog – V.Vijayendran (S.Viswanathan
printers and publications ) - 2005
3.Digital Electronics by Millman and Taub
4.Electronics Fundamentals and Applications- John D Ryder
Manonmaniam Sundaranar University, Directorate of Distance & Continuing Education, Tirunelveli.
1
 MS UNIYERSITY M.Sc., Physics Correspondence Course

Paper Title : DIGITAL ELECTRONICS

UNIT 1 NUMBER SYSTEM Binary coded decimal number system, Grey code, Grey
code to Binary conversion, Binary to Grey code, Excess 3 code, Decimal to excess 3
code, ASCII code. Universal logic gates: NAND and NOR gates as universal logic gates -
Simplification of logic circuits - De Morgan"s taws - Boolean taws - Karnaugh maps -
three variable and four variable maps - max and min terms.

Binary Coded number system

Binary codes are codes which are represented in binary system with modification from the original ones.
There are two types of binary codes: Weighted codes and Non-Weighted codes. BCD and the 2421
code are examples of weighted codes. In a weighted code, each bit position is assigned a weighting
factor in such a way that each digit ca n be evaluated by adding the weight of all the l's in the coded
combination.

o Weighted Binary Systems

./ 8421 code/BCD code

The BCD (Binary Coded Decimal) is a straight assignment of the binary equivalent. It is possible to
assign weights to the binary bits according to their positions. The weights in the BCD code are 8,4,?,1.

Example: The bit assignment 1001, can be seen by its weights to represent the decimal 9 because
1x8+0x4+0x2+lxl = 9

Weighted Code

- 8421 code
. Most common
. Default
' The corresponding decimal digit is determined by adding the weights associated with the ls in the
code group.
- 62310 = 01 t0 0010 001 1

- 2421, 542117 536, etc... codes

' The weights associated with the bits in each code group are given by the name of the code
Nonweighted Codes

- 2-out-of-5
Non Weighted codes are codes that are not positionally weighted. That is, each position within the
binary number is not assigned a fixed value.
. Actually weighted 74210 except for the digit 0
. Used by the post office for scanning bar codes for zip codes
. Has error detection properties
 2421 code

This is a weighted code; its weights are 2, 4, 2 and I. A decimal number is represented in 4-bit
form and the total four bits weight is 2 + 4 + 2 + I = 9. Hence the242l code represents the decimal
numbers from 0 to 9.

52L1 code

This is a weighted code; its weights we 5,2, 1 and 1. A decimal number is represented in 4-bit form and
thetotalfourbitsweightis5+2+l+l=9.Hencethe5211 coderepresentsthedecimalnumbersfrom
0to9.
{ Reflective code

A code is said to be reflective when code for 9 is complement for the code for 0, and so is for 8 and 1
codes, 7 and 2, 6 and 3, 5 and 4. Codes 2421,5211, and excess-3 are reflective, whereas the 8421 code is
not.

Sequential code

A code is said to be sequential when two subsequent codes, seen as numbers in binary representation,
differ by one. This greatly aids mathematical manipulation of data. The 8421 and Exbess-3 codes are
sequential, whereas the 2421and 5211 codes are not.

r' Excess-3 code

Excess-3 is a non weighted code used to express decimal numbers. The code derives its name from the
fact that each binary code is the corresponding 8421 code plus 0011(3).

Example: 1000 of 8421 = 1011 in Excess-3

'/ Gray code

The gray code belongs to a class of codes called minimum change codes, in which only one bit in the
code changes when moving from one code to the next. The Gray code is non-weightLd code, as the
position of bit does not contain any weight. In digital Gray code has got a special place.

Decimal Binary Code Gray Code

Number
0 0000 0000
1 0001 0001
2 0010 001 1
a
J 001 1 0010
4 0100 0110
5 0101 0111
6 0110 0101
7 0111 0100
8 1000 1 100
9 1001 1101
10 1010 111 1

11 1011 1110
t2 1100 1010
t3 1101 1011
t4 1110 1001
15 1111 1000
The gray code is a reflective digital code which has the special property that any two subsequent numbers
codes differ by only one bit. This is also called a unit-distance code.

Important when an
Talgg quantity must be converted to a digital representation. Only one bit changes
between two successive integers which are being coded.

{ Error Detecting and Correction Codes

o Error detecting codes

When data is transmitted from one point to another, like in wireless transmission, or it is just stored, like
in hard disks and memories, there are chances that data may get comrpted. To detect thessdata errors, we
use special codes, which are error detection codes.

o Error correcting code

Error-correcting codes not only detect errors, but also correct them. This is used normally in Satellite
communication, where turn-around delay is very high as is the probability of data getting co*upt.

o Hamming codes

Hamming code adds a minimum number of bits to the data transmitted in a noisy channel, to be able to
correct every possible one-bit error. It can detect (not correct) two-bit errors and cannot distinguish
between l-bit and 2-bits inconsistencies. It can't - in general - detect 3(or more)-bits errors.

o Parity codes

A parity bit is an extra bit included with a message to make the total number of 1.'s either even or
odd.In parity codes, every data byte, or nibble (according to how user wants to use it) is checked if they
have even number of ones or even number of zeros. Based on this information an additional bit is
appended to the original data. Thus if we consider 8-bit data adding the parity bit will make it 9 bit long.
At the receiver side,. once again parity is calculated and matched with the received parity (bit 9), and if
they match, data is ok, otherwise data is comrpt.

Two types of parity

'Even parity: Checks if there is an even number of ones; if so, parity bit is zero. When the number of
one's is odd then parity bit is set to t.

-Odd Parity: Checks if there is an odd number of ones; if so, parity bit is zero. When the number of
one's is even then parity bit is set to 1.

./ Alphanumeric codes
The binary codes that can be used to represent all the letters of the alphabet, numbers and mathematical
symbols, punctuation marks, are known as alphanumeric codes or character codes. These codes enable us
to interface the input-output devices like the keyboard, printers, video displays with the computer.

o ASCII codes

Codes to handle alphabetic and numeric information, special symbols, punctuation marks, and control
characters.

. ASCII (American Standard Code for Information Interchange) is the best known.
. Unicode - a 16-bit coding system provides for foreign languages, mathematical symbols, geometrical
shapes, dingbats, etc. It has become a world standard alphanumeric code for microcomputers and
7
computers. It is a 7-bit code representing 2 = 128 different characters. These characters represent 26
upper case letters (Ato2),26 lowercase letters (ato z),10 numbers (0 to 9), 33 special characters and
symbols and 33 control chmacters.

o EBCDIC codes

EBCDIC stands for Extended Binary Coded Decimal Interchange. It is mainly used with large computer
systems like mainframes. EBCDIC is an 8-bit code and thus accommodates up to 256 characters. An
EBCDIC code is divided into two portions: 4 zone bits (on the left) and 4 numeric bits (on the right).

Example L: Give the trinary, BCD, Excess-3, gray code representations of numbers: 5r8r14.

Decimal Number Binary code BCD code Excess-3 code Sray code
)101 )101 000 111

l 000 r000 011 100

14 110 )001 0100 )100 011 1 001

Example 2: Binary To Gray Code Conversion

1+ 0+ U+ 1+
liil
tI tBlfrlAf,Yl

ttlt r
+i + i
r 10 I r {coNvERTED6RAYCODE}

Example 3: Gray Code To Binary Code Conversion

 L.7 BOOLEAN ALGEBRA AND TIIEOREMS

Ref: 1) A.P Godse & D.A Godse "Digital Electronics", Technical publications, Pune, Revised third
edition, 2008. Pg.No:2.1-2.10
2) Morris Mano M. and Michael D. Ciletti, "Digital Design", IV Edition, Pearson Education,
2008.Pg.No:36-44.

In 1854, George Boole developed an algebraic system now called Boolean algebra. In 1938, C. E.
Shannon introduced a two-valued Boolean algebra called switching algebra that represented the
properties of bistable electrical switching circuits.

Boolean algebra is an algebraic structure defined by a set of elements B, together with two trinary
operators.'+' and'-', provided that the following (Huntington) postulates are satisfied;

Principle of Duality

It states that every algebraic expression is deducible from the postulates of Boolean algebra, and it
remains valid if the operators & identity elements are interchanged. If the inputs of a NOR gate are
inverted we get a AND equivalent circuit. Similarly when the inputs of a NAND gate are inverted, we
get a OR equivalent circuit.
1. Interchanging the OR and AND operations of the expression.
2. Interchanging the 0 and 1 elements of the expression.
3. Not changing the form of the variables.
Theorems of Boolean algebra:
The theorems of Boolean algebra can be used to simplify many a complex Boolean expression and also to
transform the given expression into a more useful and meaningful equivalent expression. The theorems are
presented as pairs, with the two theorems in a given pair being the dual of each other. These theorems can be
very easily verified by the method of 3erfect induction'. According to this method, the validity of the
expression is tested for all possible combinations of values of the variables involved. Also, since the validity
of the theorem is based on its being true for all possible combinations of values of variables, there is no
reason why a variable cannot be replaced with its complement, or vice versa, without disturbing the validity.
Another important point is that, if a given expression is valid, its dual will also be valid.

T1: Commutative Law

(a) A+B=B+A
(b) AB=BA
T2: Associative Law
(a)(A+B)+C=A+(B+C)
(b)(AB)C=A(BC)

T3: Distributive Law

(a)A(B+C)=AB+AC
(b)A+(BC)=(A+B)(A+C)
T4: Identity Law
(a) A+ A= A
(b) AA=A
T5: Negation Law.
- and

=O=
T6: Redundancy
(a) A+AB=A
(b) A(A+B)=A
T7: Operations with 60' & (1'
(a) 0+A=A
(b) lA=A
(c) I +A= I
(d) 0A=0
TL0: De Morgan's Theorem
o It States that complement of the sum of the variables is equal to the product of the complement of each
-The
variable This theorem may-pbeexpressed{by the following Boolean expression.
e It states that the of the product of variables is equal to the sum of complements of each individual
-Complement
variable. Boolean expression-for =this-theoremf is
Order of Precedence
NOT operations have the highest precedence, followed by AND operations, followed by OR operations.
Brackets can be used as with other forms of algebra.
e.g. X.Y + Z and X.(Y + Z) arc not the same function.
Truth Tables

Truth tables are a means of representing the results of a togic function using a table. They are constructed
by defining all possible combinations of the inputs to a function, and then calculating the output for each
combination in turn.

x Y t'(x,Y)
AND 0 0 )
0 1 )
1 0 )
1 1

NOT
x F(x)
0 1

1 0

OR x Y t'(x,Y)
0 0
0 1

1 0
1 1
Minterms and maxterms

A binary variable may appear either in its normal form (x) or in its complement form (x' ). Now consider
two binary variables x and y combined with an AND operation. Since each variable may appear in either
form, there are four possible combinations: x' y', x'y. xy ' , and -rry. Each of these four AND term s is called
a minterm, ot a standard product.

In a similar fashion, n variables forming g an OR terrn with each variable being primed or Unprimed
provide 2" possible combinations called maxterm. or standard sums.
r I minterm is the product of N distinct literals where each literal occurs exactly once.
r I maxterm is the sum of N distinct literals where each literal occurs exactly once.
For a two-variable expression, the minterms and maxterns are as follows

x Y Vlinterm Maxterm

0 0 K'.Y' K+Y
0 1 K'.Y K+Y'
1 0 K.Y' K'+Y
1 1 K.Y K'+Y'

For a three-variable expression, the minterms and maxterns are as follows

x Y Z Vlinterm Vlaxterm

0 0 0 K'.Y"2' Y.+Y+Z
 ) D K"Y'.2 K+Y+Z'
) K',Y.2' K+Y'+Z
) 1 K'.Y,2 K+Y'+Z'
1 K,Y',2' K'+Y+Z
1 1 K.Y',2 \'+Y+Z'
1 K,Y,Z' K'+Y'+Z
1 1 K,Y.Z K'+Y'+Z'

This allows us to represent expressions in either Sum of Products or Product of Sums forms

Sum Of Products (SOP): F(X, Y, ...) = Sum (at.mt), where at is 0 or 1 and mt is a minterm.
To derive the Sum of Products form from a truth table, OR together all of the minterms which give a
value of l.Consider the truth table as example,

x Y F Vlinterm
0 0 0 K"Y'
0 1 0 (,Y
1 0 1 (.Y'
I I 1 (.Y

Here SOP is f(X.Y) = X.Y'+ X.Y

Product Of Sum (POS): The Product of Sums form represents an expression as a product of
maxterms.F(X, Y, .......) - Product (bt + Mt), where bt is 0 or 1 and Mt is a maxterm. To derive
the Product of Sums form from a truth table, AND together all of the maxterms which give a value
of O.Consider the truth table from the previous example

x Y F Vlaxterm
0 0 1 (+Y
0 1 0 (+Y'
1 0 1 ('+Y
1 1 1 ('+Y'

Here POS is F(X,Y) = (X+Y')

,t
s fr {'
"4' r}
.x
,t
t
tr*] S*ur <rf F?md*<** {'b} frsdr**q *{S**x*

Conversion between POS and SOP: Conversion between the two forms is done by application
of DeMorgans Laws.
DIGITAL LOGIC GATES

A logic gate is an electronic circuit/device which makes the logical decisions. To arrive at this decisions,
the most common logic gates used are OR, AND, NOT, NAND, and NOR gates. The NAND and NOR
gates are called universal gates. The exclusive-OR gate is another logic gate which can be constructed
using AND, OR and NOT gate.

Logic gates have one or more inputs and only one output. The output is active only for certain input
combinations. Logic gates are the building blocks of any digital circuit. Logic gates are also called
switches. With the advent of integrated circuits, switches have been replaced by TTL (Transistor
Transistor Logic) circuits and CMOS circuits. Here I give example circuits on how to construct simples
gates.

.AND
.OR
.NOT
.BI-IF
.NAND
.NOR
.XOR
.XNOR

AND Gate

The AND gate performs logical multiplication, cornmonly known as AND function. The AND gate has
two or more inputs and single output. The output of AND gate is HIGH only when all its inputs are
HIGH (i.e. even if one input is LOW, Output will be LOW).
If X and Y are two inputs, then output F can be represented mathematically as F = X.Y, Here dot (.)
denotes the AND operation. Truth table and symbol of the AND gate is shown in the figure below.

{1.
Symbol Truth Table

x Y F(X,Y)
0 0

' lij 0
1

1
1

0
I
)
l
1
Two input AND gate using "diode-resistor" logic is shown in figure below, where X, Y are inputs and F
is the output.

s Yt"A"E

If X = 0 and Y = 0, then both diodes Dl and D2 are forward biased and thus both diodes conduct
and pull F low.
If X = 0 and Y = 1, D2 is reverse biased, thus does not conduct. But Dl is forward biased, thus
conducts and thus pulls F low.
If X = 1 and Y = 0, Dl is reverse biased, thus does not conduct. But D2 is forward biased, thus
conducts and thus pulls F low.
If X = t and Y = 1, then both diodes Dl and D2 are reverse biased and thus both the diodes are in
cut-off and thus there is no drop in voltage at F. Thus F is HIGH.

OR Gate

The OR gate performs logical addition, commonly known as OR function. The OR gate has two or more
inputs and single output. The output of OR gate is HIGH only when any one of its inputs are HIGH (i.e.
even if one input is HIGH, Output will be HIGH).
If X and Y are two inputs, then output F can be represented mathematically as F = X+Y. Here plus sign
(+) denotes the OR operation. Truth table and symbol of the OR gate is shown in the figure below.

Symbol Truth Table

x Y t'fi.Y)
0 0
0 1 I
1 0 I
1 1 1

Two input OR gate using "diode-resistor" logic is shown in figure below, where X, Y are inputs and F is
the output.
 *---. -
.--f,4

If X = 0 and Y = 0, then both diodes D1 and D2 are reverse biased and thus both the diodes are in
cut-off and thus F is low.
If X = 0 and Y = 1, Dl is reverse biased, thus does not conduct. But D2 is forward biased, thus
conducts and thus pulling Fto HIGH.
If X = 1 and Y = 0, D2 is reverse biased, thus does not conduct. But D1 is forward biased, thus
conducts and thus pulling F to HIGH.
If X = 1 and Y = 1, then both diodes D1 and D2 are forward biased and thus both the diodes
conduct and thus F is HIGH.

NOT Gate

The NOT gate performs the basic logical function called inversion or complementation. NOT gate is also
called inverter. The purpose of this gate is to convert one logic level into the opposite logic level. [t has
one input and one output. When a HIGH level is applied to an inverter, a LOW level appears on its output
and vice versa.

Symbol Truth Table

x F(x)
0 1

1 0

If X is the input, then output F can be represented mathematically as F = X', Here apostrophe (') denotes
the NOT (inversion) operation. There are a couple of other ways to represent inversion, F= !X, here !
represents inversion. Truth table and NOT gate symbol is shown in the figure below.

NOT gate using "transistor-resistor" logic is shown in the figure below, where X is the input and F is the
output.
 +\1frfr

When X = 1, The transistor input pin 1 is HIGH, this produces the forward bias across the emitter base
junction and so the transistor conducts. As the collector current flows, the voltage drop across RL
increases and hence F is LOW.
When X = 0, the transistor input pin 2 is LOW: this produces no bias voltage across the transistor base
emitter junction. Thus Voltage at F is HIGH.

BIIF Gate

Buffer or BUF is also a gate with the exception that it does not perform any logical operation on its input.
Buffers just pass input to output. Buffers are used to increase the drive strength or sometime just to
introduce delay. We will look at this in detail later.
If X is the input, then output F can be represented mathematically as F = X. Truth table and symbol of
the Buffer gate is shown in the figure below.

Symbol
Truth Table

x rG)
0 )
1

NAND Gate

NAND gate is a cascade of AND gate and NOT gate, as shown in the figure below. It has two or more
inputs and only one output. The output of NAND gate is HIGH when any one of its input is LOW (i.e.
even if one input is LOW, Output will be HIGH).

If X and Y are two inputs, then output F can be represented mathematically as F = (X.Y)', Here dot (.)
denotes the AND operation and (') denotes inversion. Truth table and symbol of the N AND gate is
shown in the figure below.
 Symbol Truth Table

x Y t'(x,Y)
r 0 o
rs{x&Yi'
0 t
1 o
I 1

NOR Gate

NOR gate is a cascade of OR gate and NOT gate, as shown in the figure below. It has two or more inputs
and only one output. The output of NOR gate is HIGH when any all its inputs are LOW (i.e. even if one
input is HIGH, output will be LOW).
Truth Table
Symbol

ffi
x Y F(X,Y)
0 0
0 1

1 0
1 1

XOR Gate

An Exclusive-OR (XOR) gate is gate with two or three or more inputs and one output. The output of a
two-input XOR gate assumes a HIGH state if one and only one input assumes a HIGH state. This is
equivalent to saying that the output is HIGH if either input X or input Y is HIGH exclusively, and LOW
when both are 1 or 0 simultaneously.

If X and Y are two inputs, then output F can be represented mathematically as F = X fY, Here I
denotes the XOR op.ruiio.r. X lY and is equivalent to X.Y' + X'.Y. Truth table and symbol of the XOR
gate is shown in the figure below.

Truth Table
Symbol
x Y F(X,Y)
0 ) 0
0 1

I l 1

1 0

XNOR Gate
An Exclusive-NOR (XNOR) gate is gate with two or three or more inputs and one output. The output of
a two-input XNOR gate assumes a HIGH state if all the inputs assumes same state. This is equivalent to

saying that the output is HIGH if both input X and input Y is HIGH exclusively or same as input X and
input Y is LOW exclusively, and LOW when both are not same.
If X andY aretwo inputs, thenoutputFcanberepresented mathematically as F= X OY, Here O
denotes the XNOR operation. X O Y and is equivalent to X.Y + X'.Y'. Truth table and symbol of the
XNOR gate is shown in the figure below.

Symbol Truth Table

x Y F(X,Y)
0 0
0 1

1 0
I 1 I

Universal Gates

Universal gates are the ones which can be used for implementing any gate like AND, OR and NOT, or
any combination of these basic gates; NAND and NOR gates are universal gates. But there are some
rules that need to be followed when implementing NAND or NOR based gates.

1.6 NANDand NOR implementation

Any logic function can be implemented using NAND gates. To achieve this, first the logic function has
to be written in Sum of Product (SOP) form. Once logic function is converted to SOP, then is very easy
to implement using NAND gate. [n other words any logic circuit with AND gates in lrst level and OR
gates in second level can be converted into a NAND-NAND gate circuit.

Consider the following SOP expression

F=W.X.Y +X.Y.Z+Y.Z.W

The above expression can be implemented with three AND gates in first stage and one OR gate in
second stage as shown in figure.
 \Y

,;

If bubbles are introducedat AND gates output and OR gates inputs (the same for NOR gates), the above
circuit becomes as shown in figure.

Y.J

y.

"\
Y

Now replace OR gate with input bubble with the NAND gate. Now we have circuit which is fully
implemented with just NAND gates.

r
?
/ Realization of logic gates using NAND gates

Implementing an inverter using NAND gate

Input Output Rule

(x.x)' =X' Idempotent

Implementing AND using NAND gates

Innut )utput Rule

((xY)'(xY)')' =
((XY)')' Idempotent
= (xY) Involution

Implementing OR using NAND gates

lnput )utput Rule

(xx)'(YY)' (x'Y')' dempotent

= X"+Y" )eMorgan
X+Y nvolution

Implementing NOR using NAND gates

nput )utput Rule

(xx)'(YY)' =(X'Y')' dempotent

=X"+Y" )eMorsan
;*;;ri+ylr F*h'!i.$ix+Y],
=X+Y nvolution
=(X+Y)' dempotent

Realization of logic function using NOR gates

Any logic function can be implemented using NOR gates. To achieve this, first the logic function has to
be written in Product of Sum (POS) form. Once it is converted to POS, then it's very easy to implement
using NOR gate. In other words any logic circuit with OR gates in first level and AND gates in second
level can be converted into a NOR-NOR gate circuit.

Consider the following POS expression

P=(X+Y).(Y+Z)
The above expression can be implemented with three OR gates in first stage and one AND gate in
second stage as shown in figure.

If bubble are introduced at the output of the OR gates and the inputs of AND gate, the above circuit
becomes as shown in figure.
Now replace AND gate with input bubble with the NOR gate. Now we have circuit which is fully
implemented with just NOR gates.

xrr

Implementing an inverter using NOR gate

nput Output Rule

(X+X)' =X' Idempotent

Implementing AND using NOR gates

lnput )utput Rule

(X+X)'+(Y+Y) =(X'*Y') dempotent
')'
x".Y" )eMorgan

= (x.Y) nvolution
Implementing OR using NOR gates

Input )utput Rule

f*;,Y t"Y
(X+Y)'+(X+Y)')' = ((X+Y)')' Idempotent
= X+Y Involution

Implementing NAND using NOR gates

Input Jutput Rule

((X+Y)'+(X+Y)')' =
((X+Y)')' dempotent
= X+Y lnvolution
= (X+Y)' dempotent

$:;lX YI
' !/ r ,

Minimization Technique

The primary objective of all simplification procedures is to obtain an expression that has the minimum
number of terms. Obtaining an expression with the minimum number of literals is usually the secondary
objective. If there is more than one possible solution with the same number of terms, the one having the
minimum number of literals is the choice.

There are several methods for simplification of Boolean logic expressions. The process is usually called
logic minimization and the goal is to form a result which is efficient. Two methods we will discuss are
algebraic minimization and Karnaugh maps. For very complicated problems the former method can be
done using special software analysis programs. Karnaugh maps are also limited to problems with up to 4
binary inputs. The Quine-McCluskey tabular method is used for more than 4 binary inputs.

I.6 KARNAUGH MAPS

Maurice Karnaugh, a telecommunications engineer, developed the Karnaugh map at Bell Labs in 1953
while designing digital logic based telephone switching circuits. Karnaugh maps reduce logic functions
more quickly and easily compared to Boolean algebra.
A Karnaugh map provides a pictorial method of grouping together expressions with common factors and
therefore eliminating unwanted variables. The Karnaugh map can also be described as a special
arrangement of a truth table.

Construction of a Karnaugh Map

containing a
-L' must be considered at least once, although it can be considered as
1. Each square
often as desired.
2. Tt,e objective should be to account for all the marked squares in the minimum number of groups.
3. The number of squares in a group must always be a power of 2, i.e. groups can have l, 2, 4_ 8, 16,
squares.
4. Each group should be as large as possible, which means that a square should not be accounted for by itself
if it can be accounted for by a group of two squares; a group of two squares should not be made if the
involved squares can be included in a group offour squares and so on.
5. care6 entries can be used in accounting for all of l-squares to make optimum $oups. They are
-Don't
marked in the corresponding squares. It is, however, not necessary to account for all _don.t care.
-X6
entries. Only such entries that can be used to advantage should be used.

The diagram below illustrates the correspondence between the Karnaugh map and the truth table for the
general case of a two variable problem.

The values inside the squares are copied from the output column of the truth table, therefore there is one
square in the map for every row in the truth table. Around the edge of the Karnaugh map are the values of
the two input variable. A is along the top and B is down the left hand side. The diagram below explains
this:
A
t1 I
E
00 U
0 0 I
01 I
10 I.+- I I I
II I

Truth Tatrle. F.

The values around the edge of the map ciln be thought of as coordinates. So as an example, the square on
the top right hand corner of the map in the above diagram has coordinates A=1 and B=0. Thii square
corresponds to the row in the truth table where A=t and B=0 and F=1. Note that the value in the F
column represents a particular function to which the Karnaugh map corresponds.
Two variable K-map

There are four minterms for two variables: hence, the map consists of four squares, one for each minterm.
In any K-Map, each square represents a minterm. Adjacent squares always differ by just one literal (So
that the unifying theorem may apply: X + X' = 1). For the 2-variable case (e.g.: variables X, y), the map
can be drawn as below. Two variable map is the one which has got only two variables as input.

?
.. .-3.
"i" Y
x \r-

I
xi
i
i.

Example- Carry and Sum of a half adder

In this example we have the truth table as input, and we have two output functions. Generally we may
have n output functions for m input variables. Since we have two output functions, we need to draw two
k-maps (i.e. one for each function). Truth table of 1 bit adder is shown below. Draw the k-map for Carry
and Sum as shown below.

p s
",{ I {
ql
C*rry*g'.Y $e"rm=XY + X'Y

Grouping/Circling K-maps

The power o^f K-m.apl is in mini_mizing the terms, K-maps can be minimized with the help of grouping
the terms to form single terms. When forming groups of s(uares, observe/consider the following:-

. Every square containing 1 must be considered at least once.

. A square containing 1 can be included in as many groups as desired.
. A group must be as large as possible.
' If a square containing 1 cannot be placed in a group, then leave it out to include in final expression.
. The number of squares in a group must be equal to 2 .i.e.2,4,8,.
' The, map is considered to be folded or spherical, therefore squares at the end of a row or column are
treated as adjacent squares.
: th^g simplified logic expression obtained from a K-map is not always unique. Groupings can be made
in different ways.
' Before drawing a K-map the logic expression must be in canonical form.
 ':]:'i.'.Lii.:;!r.

Example of invalid groups

,---.-./\,---*rr

,.(s- H
,"{ o gd
*-- *

Example (1)- X'Y+XY: In this example we have the equation as input, and we have one output function.
Draw the k-map for function F with marking 1 for X'Y and XY position. Now combine two I's as shown
in figure to form the single term. As you can see X and X' get canceled and only Y remains

F=Y
--**a

n6-r
{ I
}.*_-'+.*--*d
ilPI
Fxample (2)- X'Y+XY+XY' :In this example we have the equation as input, and we have one output
function. Draw the k-map for function F with marking 1 for X'Y, XY and XY position. Now combine
two 1's as shown in figure to form the two single terms.

F=X+Y
 i'f)
l
lr?r:
{ f) \J-,''
3-Variable K-Map
There are 8 minterms for 3 variables (X, Y, Z). T\erefore, there are 8 cells in a 3-variable K-map. One
important thing to note is that K-maps follow the gray code sequence, not the binary one. Each cell in a
3-variable K-map has 3 adjacent neighbours. In general, each cell in an n-variable K-map has n adjacent
neighbours.

r**-**t*,..a

ar* rc{ ttr3 {fi:d

..{il *ll4 rfi5 rY!? rlrS

\-9p*il

There is wrap-around in the K-map

. X'Y'Z' (m0) is adjacent toX'YZ'(m2)
. XY'Z' (m4) is adjacent to XYZ'(m6)

Example (4) F(X,Y,Z) = \1,3,4,5,6,7 )

Example (3) F = XYZ' +XYZ+X'YZ
F=X+Z
F=XY+YZ

l .f,
0s tll II Til
-;;*
l; I 'I', I

{t | \._-. ,-
,

f ;::;: -

I
lu* '
r h

"**{---*
4-Variable K-Map: There are t6 cells in a 4-variable (W, X, Y,Z); K-map as shown in the figure below

\ \,

tr#*\ 1@Y:\
{}il {"r} ll lti
fi t ft t LT&r ffilr i]"!r I11:

r j {H}

n\,
)
t
j iii
rl 3 tn ITi,+ t114 Xtlr
{.
{ +t {{ ttlr: ffii.t lHr: ,
t.L 13 l*+
JII {"}"1 ,
J
\
iL s la ItI
Lr* t}te ltk i11* r
ilXg6
r,
L,---*\y-J l**,ry*$
v

a.-t"*\
s*firil1*
sf
st

[,, ]

t,o

Example (6) F(W,X,Y,Z) = (4,5, 10, 1 1, 14,15)

T

f-..t-1
II T{}

MI

sl

Inn l
1'*
S-Yariable K-Map: There arc 32 cells in a 5-variable (V, W, X, Y, Z); K-map as shown in the figure
below.
:

i 1r ** {}l ll l{} {}l} {J} il t*

I&l Klt fl1: n\ ffiiri fr}t; trqc El*u
il* fi{}
1
fi,1 I11n 111.1 lxl- frh IF{ {}r tl\rr fi}:* m\.1 r11::
1
i{ rr tlll:
, ,IT
x
flll.l tfirs Il',lr r
J Jrr Ix':* ilh* tT131 H}. u {
J
t lil n& Ill* ffix fi}t* I rr: !Tl. "
Ilh-u r&: I?1;6

L* **_J t-"--=.*J
Y

a".'

1.7 QUNE. MCCLUSKEY METHOD

The tabular method which is also known as the Quine-McCluskey method is particularly useful when
minimising functions having a large number of variables, e.g. The six-variable functions. Computer
programs have been developed employing this algorithm. The method reduces a function in standard sum
of products form to a set of prime implicants from which as many variables are eliminated as possible.
These prime implicants are then examined to see if some are redundant.

The tabular method makes repeated use of the law A + G 1. Note that Binary notation is used for the
function, although decimal notation is also used for the functions. As usual a variable in true form is
denoted by 1, in inverted form by 0, and the abscence of a variable by a dash ( - ).

Rules of Tabular Method

1. The Boolean expression to be simplified is expanded if it is not in expanded form.

2. Different terms in the expression are divided into groups depending upon the number of ls they
have.

3. The terms of the first group are successively matched with those in the next adjacent higher order
group to look for any possible matching and consequent reduction. The terms are considered
matched when all literals except for one match. The pairs of matched terms are replaced with a single term where the position of the unmatched
literals- is replaced with a_ dash (1). Thesg new terms* formed as a result of the matching process find a place in the second table. The terms in the
frst table that do not find a match are called the prime implicants and are marked with ai''a-sterisk ( ). Thd matched terms ari ticied L)-

4. Terms in the second group are compared with those in the third group to look for a possible match.

Again, terms in the second group that do not find a match become the prime implicants.
 5. The process continues until we reach the last group. This completes the first round of matching.
The terms resulting from the matching in the first round are recorded in the second table.

6. The next step is to perform matching operations in the second table. While comparing the terms
for a match, it is important that a dash (-) is also treated like any other literal, that is, the dash
signs also need to match. The process continues on to the third table, the fourth tables and so on
until the terms become irreducible any further.

7. An optimum selection of prime implicants to account for all the original terms constitutes the
terms for the minimized expression. Although optional (also called _do 't care') ter s are
considered for matching, they do not have to be accounted for once pri-me implicants have been
identified.

Example L: Let us consider an example. Consider the following sum-of-products expression:

*;
E.s. c + X.n s +,q"T]"$+ *.E5+X,*"T. r"r

I* th* fir* *r*p" r*'e wrile {h* *xtrurxd<xl ver siru trf tlre girco *rpr*s.sixr" Il r*lr he rru"ritt*lr ils trl*'l}*;wr:

X,r"c:"m+?.$.c.TI+H.ff'E:.*+Xif,f"rr+,{.B"e r: + e.B T, r}+ A.s"f"F

+*.#.c"$+ d.s.c"t}

Th* l"*rn:ati*n tlf gsl${Ilrs. tlt* pktr,**l*nt *f ternrs in rlitl'rrenl Srmrps ;urd the fimt-rr:u*d rn*tching ar*
str{}wr} *s rc*}ss\,s;

r r
* [tt $s*t{ * I*"
{"} II sltlt{ {} : tll*r
*s * t)I*'
t, {!l s{itlt * ri ,{
G t* *t{ilt'' tlt
il II illt*{ : t) fl tr
i v *t t${i{{
; I $t| lI*il,t- $

I I {}} sttld * I

t[{i1./ I {}

t3 I 1-
I *l
T I ti

The second round of matching begins with the table shown on the previous page. Each term in the first
 group is compared with every term in the second group. For instance, the first term in the first group
00-L matches with the second term in the second group 01-1 to yield 0- -1, which is recorded in
the table shown below. The process continues until all terms have been compared for a possible match.
Since this new table has only one group, the terms contained therein are all prime implicants.

In the present example, the terms in the first and second tables have all found a match. But that is not
always the case.

AStr*

The next table is what is known as the prime implicant table. The prime implicant table contains all the
original terms in different columns and all the prime implicants recorded in different rows as shown below:

sfi]t &)l t t**{x} {itr}f {}lifi t}t I I t{.xlt t }rift t I*l

{,f {i- *t f -+ A.l}
$ { d - **I g --+ f',$
d.{"dC fit-- *-*3"*
.d '/ ,ro ,f *l&- g "--+ S"ff

Each prime implicant is identified by a letter. Each prime implicant is then examined one by one and the
terms it can account for are ticked as shown. The next step is to write a product-of-sums expression
using the prime implicants to account for all the terms. In the present illustration, it is given as follows.

(P + Qi.(f'). ( r{ +.$i. ( P + 0 + tr + S}.( fr}.( p + I{.r.( 8}.( S). ( 0+ SI

Obvious simplification reduces this expression to PQRS which can be interpreted to mean that all
prime implicants, that is, P, Q, R and S, are needed to account for all the original terms.

Therefore, the minimized expression - T'rrae'n+T'a+ r'T"

(E+ E+E+ E) "r3+ E +T+ t:t. lF +B' + {: +F} {A +E'+ f +trt. t.+ + E + c +E}
Example 2. "

lhe procgdure is similar to that described for the case of simplification of sum-of-products expressions.
The resulting tables leading to identification of prime implicants are as follows:
 "{"SS"$.{B{:& ."t*st)*#cJ}
#1#t$t $:}.tc'tr|-tcl*ts
$[*]
xl€*t* Ir{
tll{}l *t,c'
*rltl lllc^lt1,r"
Itl**
tllln
The prime implicant table is constructed after all prime implicants have been identified to look for the
optimum set of prime implicants needed to account for all the original terms. The prime implicant table
shows that both the prime implicants are the essential ones:

$l$t OllI Il{}l IllO Illl Prrnr*rruphcan{,"

.f ,r llt*
{ rr" '/- d -t-r
The mini'xiecd expressi*n = tE+Ef f:j"{B+E}.

Example 3:Consider the function f(A, B, C, D) = 10,1,2,3,5,7,8,10, 12,13,L5),note that this is in

decimal form.
40000,0001,0010,0011,0101,0111,1000,1010,1100,1101,1111) inbinary form.
(0,I,1,2,2,3,1,2,2,3,4) in the index form.
The prime implicants are: - +- +- +
The chart is used to remove redundant prime implicants. A grid is prepared having all the prime
implicants listed at the left and all the minterms of the function along the top. Each minterm covered by
a given prime implicant is marked in the appropriate position.

From the above chart, BD is an essential prime implicantJt is the only prime implicant that covers the
pinterm decimal 15 and it also includes 5, 7 and 13. Iro an essential prime implicant. It is the
only prime implicant that covers the minterm denoted by decimal 10 and it also includes the terms 0, 2
and 8. The other minterms of the function are 1, 3 and 12. Minterm 1 is present in I and ID.
Similarly minterm 3, Wecanthereforeuse either of theseprime implicants for these minterms.
-for
Minterm 12 is present in A andAB , so again either canbe used. -

+ + -+
Thus, one minimal solution is:

UNIT II
Arithematic circuits Half adder - Truth table and circuit - FuII adder -
Truth table and circuit - Four bit adder - Half subtractor - FulI subtractor -
Multiplexer: Four input multiplexer - Applications of Multiplexer - demultiplexer -
Decoders 2to 4 decoder - BCD to seven segment decoder - encoders.

Arithmetic circuits are the ones which perform arithmetic operations like addition, subtraction,
multiplication, division, parity calculation. Most of the time, designing these circuits is the same
as designing mux, encoders and decoders.

1. Adders

Adden are the basic building blocks of all arithmetic circuits; adders add two binary numbers
and give out sum and carry as output. Basically we have two types of adders.

. Half Adder.
. Full Adder.

Half Adder

A half-adder is an arithmetic circuit block that can be used to add two bits. Such a circuit thus has two
inputs that represent the two bits to be added and two outputs, with one producing the SUM output and
the other producing the CARRY.

Adding two single-bit binary values X, Y produces a sum S bit and a carry out C-out bit. This
operation is called half addition and thus the circuit to realize it is called a half adder.

Symbol
 Truth table

x Y iuM CARRY
Hmlf 0 0 )

&x$dmr 0 1 )
1 0
1 1

The expression for the sum and carry are,

I
Sum = XY+XY

Carry = XY

Circuit

*E$EffiY

Full Adder

A full adder circuit is an arithmetic circuit block that can be used to add three bits to produce a SUM
and a CARRY output. Such a building block becomes a necessity when it comes to adding binary
numbers with a large number of bits. The full adder circuit overcomes the limitation of the half-adder,
which can be used to add two bits only.

Full adder takes a three-bits input. Adding two single-bit binary values X, Y with a carry input bit C-
in produces a sum bit S and a caffy out C.
 Truth Table

x Y Z iU ]ARRY
VI
0 0 0
0 0 1

0 1 0
0 1 1

1 0 0
1 0 1

1 1 0
1 1 1

Y Yrj
f*____--/\*-\
a

s {T}
ffi
flT\

L.-=r**J
tr '{ l0! ffi
\-\r-------J
3
{ :1

Full Adder using AND-OR

The below implementation shows implementing the full adder with AND-OR gates, instead of
using XOR gates. The basis of the circuit below is from the above K-map

Circuit-SUM Circuit-CARRY
 Circuit-CARRY
FulI Adder wing AND-OR

Circuit-SUM

x lfl -"
Y*+il,*.-,r- ,i -
it
\rU
rt
-, ;ffi
I *l'
-,-'
Logic Implenentation of a full adder with Half Adders
r t!F."* I

Survr

& *-*-
.*"***"#*r,*t

r' n-bl Carry Ripple Adder

An n-bit addm used to add two n-bit binary numbers can be built by connecting n full adders in
series. Each fnll adder represents a bit position j (from 0 to n- 1).

Each carry orfi C-out from a full adder at position j is connected to the carry in C-in of the full adder
at higher posilion j+l. The output of a full adder at position j is given by:

Sj= Xj Yi q
Cj+l = xj . Yj + xj . Cj + Y. Cj
In the expression of the sum Cj must be generated by the full adder at lower position j. The
propagation delay in each full adder to produce the carry is equal to two gate delays = 2 D Since the
generation of the sum requires the propagation of the carry from the lowest position to the highest
position , the total propagation delay of the adder is approximately:

Total Propagation delay =2nD

4-bit Carry Ripple Adder

Adds two 4-bit numbem:

X=X3X2X1X0
Y=Y3Y2YlY0
Producing the sum S = 53 52 51 S0, C-out = C4 from the most significant position
j=3 Total Propagation delay = 2 nD = 8D or 8 gate delays

H*,Y3 X1 X* Y3 Y2 Y1 YO

f - r.'", .

Larger Adder

Example: 16-bit adderusing 4 4-bit adders. Adds two 16-bit inputs X (bits X0 to X15), Y (bits Y0 to
Y15) producing a 16-bit Sum S (bits S0 to S15) and a carry out C16 from the most significant position.
Propagation delay for 16-bit adder = 4 x propagation delay of4-bit adder
= 4 x 2 nD = { x 8D = 32 D or 32 gatedelays

{.} .$;l X i 3fi Y.} Y} Y, Y# n;1 r:;l Il .H+ ?1 Yf; Y1 T* E:{ ,(} t i ;{,i1,13 Y? Yl y*

i::_ii :_:r.r::r it:.l

Carry Look-Ahead Adder

The delay generated by an N-bit adder is proportional to the length N of the two numbers X and Y that
are added because the carry signals have to propagate from one full-adder to the next. For large values
of N, the delay becomes unacceptably large so that a special solution needs to be adopted to accelerate
the calculation of the carry bits. This solution involves a "look-ahead carry generator" which is a block
that simultaneously calculates all the carry bits involved. Once these bits are available to the rest of the
circuit, each individual three-bit addition (Xt+Yi+carry-ini) is implemented by a simple 3-input XOR
gate. The design of the look-ahead carry generator involves two Boolean functions named Generate and
Propagate. For each input bits pair these functions are defined as: Gi = Xi . Yi & Pi = Xi + Yi

The carry bit c-out(i) generated when adding two bits Xi and Yi is 'f if the corresponding function Gi is
'1' or if the c-out(i-1)='1'
and the function Pi = '1' simultaneously. In the first case, the carry bit is
activated by the local conditions (the values of Xi and Yi). In the second, the carry bit is received from
the less significant elementary addition and is propagated further to the more significant elementary
addition. Therefore, the carry_out bit corresponding to a pair of bits Xi and Yi is calculated according
to the equation:
carry-ou(i) = Gi + Pi.carry-in(i- 1 )

For a four-bit adder the carry-outs are calculated as follows

carry_out0 = G0 + P0 . carry_in0
carry_outl = Gl + Pl . carry_outO = G1 + PlG0 + PlP0 . carry_in0
carry_out2 =G2 + P2G1 + P2PlG0 + P2P1P0 . carry_in0
carry_out3 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1 . carry_in0

The set of equations above are implemented by the circuit below and a complete adder with a look-
ahead carry generator is next. The input signals need to propagate through a maximum of 4 logic gate in
such an adder as opposed to 8 and 12logic gates in its counterparts illustrated earlier.

carry*auh carry_ouL carry..outl carrv Out^v

,: i

fl
ry
j
1 '**r
&
,
,l

| fl8tlV
: .* lI}"u
",
1

rs
x* Ys xa Yr
Sums can be calculated from the following equations, where carry_out is taken from the carry
calculated in the above circuit.
sum_out0=X0Y0
carry_out0 sum_outl = X 1 Y1
carry_outl sum_out2 = X 2 Y2
carry_out2 sum_out3 = X 3 Y3
carry*out3

f:ilc+*rry*ifl S*AJ
fn:um ouro

41
AA
at**\ c,,*
r,':::-----:*11 ) $urn*oulr
^rrr
' n**.'y--lfu3l*l
surfl ouL4

Y_- sum CULJ

'" **xrrY*

,/ BCD Adder

BCD addition is the same as binary addition with a bit of variation: whenever a sum is greater than
1001, it is not a valid BCD number, so we add 0110 to it, to do the correction. This will produce a carry,
which is added to the next BCD position.

. Add the two 4-bit BCD code inputs.

. Determine if the sum of this addition is greater than 1001; if yes, then add 0110 to this sum
and generate a carry to the next decimal position

2. Subtractor

Subtractor circuits take two binary numbers as input and subtract one binary number input from the
other
binary number input. Similar to adders, it gives out two outputs, difference and borrow (carry-in the
case of Adder). The BORROW output here specifies whether a:1' has been borrowed to perform
the
subtraction.
There are two types of subtractors,

,/ Half Subtractor

The half-subtractor is a combinational circuit which is used to perform subtraction of two bits. It has
two inputs, X (minuend) and Y (subtrahend) and two outputs D (difference) and B (borrow). The logic
symbol and truth table are shown below.

Symbol Truth table

 x Y D B
0 0 0 0
Hmlt 0 1 1 1

$uhtrm*trr I 0 1 0
1 1 0 0

From the above table we can draw the K-map as shown below for "difference" and "borrow". The
Boolean expression for the difference and Borrow can be written.
!' Y
r-&^t r--Aa

s"
={
{
q
B*rr*w*X'.Y Difference=XY' + X'Y
From the equation we can draw the half-subtractor as shown in the figure below.
{ Full Subtractor

A full subtractor is a combinational circuit that performs subtraction involving three bits,
namely
minuend, subtrahend, and borrow-in. There are two outputs, namely the DIFFERENCE output D and
the BORROW output Bo. The BORROW output bit tells whether the minuend bit needs to-borrow a
:1,
from the next possible higher minuend bit. The logic symbol and truth table are shown below.
Symbol
Truth table

x Y Bin D Bout
Ful* 0 0 0 )
0 0 1 1

$uhtrm*t*r 0 1 1 1

0 1 0 1

1 0 1 )
1 0 0 )
1 1 0
1 1 1

Suhtrw*tor

Yfi!m YBin
x 0[ 01 t{ t0 x 00 01 1t '10

fi ff s 0
ffi ffi *

x
s ffi I t#
ffiiff*,r*s-l*#*X'Y"Bifi + X'Y*in'+ XY'Sin' *Unr*W*X'Bin + lq",y * '1.,t:::j)iI

+ XYBin

fr-9m lhe above.expression, we can draw the circuit below. If you look carefully, you will see that a
full-subtractor circuit is more or less same as a full-adder with siight modification.
 v

./ Parallel Binary Subtractor

Parallel binary subtractor can be implemented by cascading several full-subractors. Implementation

and associated problems are those of a parallel binary adder, seen before in parallel binary adder
section.

Below is the block level representation of a 4-bit parallel binary subtractor, which subtracts 4-bit
Y3Y2Y1Y0 from 4-bit X3X2X1X0. It has 4-bit difference output D3D2D1D0 with borrow output
Bout.
{ Serial Binary Subtracter

A serial subtracter can be obtained by converting the serial adder using the 2's complement system. The
subtrahend is stored in the Y register and must be 2's complemented before it is added to the minuend
stored in the X register. The circuit for a 4-bit serial subtracter using full-adder is shown in the figure
below.

:. $UM

full aduar
{m to|,ll

Comparators

It is a combinational circuit that compares two numbers and determine their relative magnitude. The
output of comparator is usually 3 binary variables indicating:
A<B, A=B, A>B

l-bit comparator: Let's begin with 1 bit comparator and from the name we can easily make out that
this circuit would be used to compare 1 bit binary numbers.

A B {,>B {.=B A<B

0 0 ) )
1 0 )
0 1 ) 1

1 1 )
For a 2-bit comparator we have four inputs A1A0 and B1B0 and three output E ( is 1 if two
numbersareequal)G(islwhenA>B)andL(islwhenA<B)IfweusetruthtableandK-map
the result is

e c
A>B
I
0 s s Equeilon ls A>B - AE
I I r
s^*<B
o t
0 fr t
Equaiion isA<B * A.B

t *

n {A=B} 1

0 1 p
Tha aquatlon lsfiA*Bi -[P+ 4"9
*AXNORB
I I 1

The comparison process of two positive numbers X and Y is performed in a birby-bit maffier starting
with the most significant bit:
If the most significant bits are Xn='1' and Yn='0' then number X is larger than Y.
o If Xn='O'and Yn='l'then number X is smaller than Y.
o If Xn=Yn then no decision can be taken about X and Y based only on these two bits.
I{ thg most significant bits are equal then the result of the comparison is determined by the less
significant bits Xn-l and Yn-l. If these bits are equal as well, the process continues with the next pair
of bits. If all bits are equal then the two numbers are equal.

4-bit comparator:

AO ct)
A1
.{2
A3
A>ff
:]
BO A-ff
BI
A <8
B3
E3
:]

2.5 CODE CONVERSION- Binary to Gray converter

Truth Table

S. No B3 92 B1 BO G3 ]2 G1 ]0
) ) l
1 ) 1

0 1

)
+ l c 1 )
1 1 1

1 ) ) 1 1

1 1 ) )
)
) 0 ) 1

) ) 1

10 ) 1

11 ) 1

t2 l ) 1 )
t3 )
t4 1 1 )
15 1 ) l
 K.MAP FOR G3:

BlBt]
E0 0't 11 10

E382
00 0 u E 0

01
0 0 0 0

1 1 1 1
11

1 1
10 t,
1

G3= 83

K.MAP FOR G2:

1B1Bo 6g 01 11

8382
00 0 0 0 0

E1 1 1 1

I
0 0
1l'I D 0

10 1 1 1
I
G2=83' 82 + 83 Fl2'= B3lgZ

K-MAP FOR Gl:

\BtB0 0E 81 "1.r

B,3B2
00 0 1
J
0'1
t'1
1 1 0 0
I

111 1 j n 0

u
1u ! il T I

G1= 81'82 + 81 B2'=B,tlgZ

 K.MAP FOR GO

ElEO 00 '11 10
01 tt
83B2

00 0 1 u

E
01 E 1
1 0

0
I 0
11 1

IE 0
t_l L] 0

G0= 8L' B0 + 81 B0'= Bl I nO

G3

cl

2.6 DECODERS

A decoder circuit can be used to implement AND-OR circuit SOP Boolean expression when decoder
active state output is 1 and inactive 0 .

. Number of binary inputs n

=
. Number of binary outputs = 2n = Maximum number of minterms, where n is the number of literals in F
. Its outputs reflect the Mini-terms with one term each at each of the output
 #d8 Sir S1 #; #1

I-trtr Iltl
fitls *Ll1
fr01 tfrt1
{}tit Ittlt
r]11 lrl$

{ai L{rni* diag*rnr {b} Trurh r*hk

Figure: 2-to-4line decoder with enable input

B&l}l tr'u$le af c IFlres-lc-fS,*rf-time Sesoelrr

. ._ lT$rI*_ Sutpxtx
*r $hs1&#lsasslr $y
tI*n rfifl0&ss$
fi*l sl{}il*0tli)
rlls {}{}t{}(}r}nt}
*lr #fi01t}{}o&
lfir) s**0trl{}*
I*t {}{}{}t}0t$s
tt{l fiso0$srtl
$lr *fi*(l{1r}ftt
 Il* * -t'"r,'t

Cla '* x'.''t

, "i_ 13, * x-y'r

Il* o "S.!",i

I!* * :g!";-

#r k :;.!'I

Fig: Circuit for 3-to{ line decoder

2.7 ENCODERS

An encoder is a circuit that converts the binary information from one form to another. Gives a unique
combination of outputs according to the information at a unique input at one-line (or at multiple lines).
Action of a one active line input encoder is opposite of that of a one active line output decoder. An
encoder, which has multi-lines as the active inputs, is also called'priority encoder'. Encoder can be
differentiated from decoder by greater number of inputs than outputs compared to the decoder. The
priority encoder includes a priority function.
4to3 Priority Encoder-The truth table of a 4-input priority encoder is as shown below. The input D3
has the highest priority, D2 has next highest priority, D0 has the lowest priority. This means output Y2
and Yl are 0 only when none of the inputs Dl, D2, D3 are high and only D0 is high. A 4 to 3 encoder
consists of four inputs and three outputs, truth table and symbols of which is shown below.
Truth Table

D3 D2 D1 DO Y2 r1 r0
) ) )

) )

)
)
0
I
1

x
x
x
I t,
1

1 x x x 1

K-map

i.::! ':l ]1i

* { t1

ffi 3
nt
x
u
(] t1
{1

ft

'd'**il3'. l"li * **',*{,r.*:' 1':-ij'*?, il,I'['

ft*
nt
tJt

m$
 2.8 Mt]LTIPLEXERS

Many tasks in communications, control, and computer systems can be performed by combinational
logic circuits. When a circuit has been designed to perform some task in one application, it often finds
use in a different application as well.

A multiplexer (MUX) is a digital switch which connects data from one of n sources to the output. A
number of select inputs determine which data source is connected to the output. The block diagram of
MUX with n data sources of b bits wide and s bits wide select line is shown in below figure.

$aloct gFt

Wrs$tipl*xer
**
1-I !
Sxta
tput

Bxample - 2x1 MUX

A2 to 1 line multiplexer is shown in figure below, each 2 input lines A to B is applied to one input of
an AND gate. Selection lines S are decoded to select a particular AND gate. The truth table for the 2:1
mux is given in the table below.

Truth table

S Y
0 A
1 B
Design of a I:1 Mux

To derive tle gate level implementation of 2:l mux we need to have truth table as shown in figure.
And once uc have the truth table, we can draw the K-map as shown in figure for all the cases when Y
is equal to '.1'.
Combiningthe two 1' as shown in figure, we can drive the output y as shown below

Y = A.S'+ B.S

Truth table K-map

B A t Y

ffi m
0 0 0
0 0 0
0 1 ) 1

0 1 0
1 0 ) 0
1 0 1 I
1 1 ) 1

1 1 1 1

Circuit
Example : 4:1MUX

A 4 to 1 line multiplexer is shown in figure below, each of 4 input lines I0 to 13 is applied to one input
of an AND gate. Selection lines S0 and S1 are decoded to select a particular AND gate. The truth table
for the 4:1 mux is given in the table below.

Truth table
{t
i0
fr -!
I
il
.Y
S1
) )
Y
IO
Ix i ' ) I I1
1 ) t2
f3 --,
1 I3

Circuit

2.9 DEMULTIPLEXERS

They are digital switches which connect data from one input source to one of n outputs. Usually
implemented by using n-to-2n binary decoders where the decoder enable line is used for data input of
the de-multiplexer.
The figure below shows a de-multiplexer block diagram which has got s-bits-wide select input, one b-
bits-wide data input and n b-bits-wide outputs.
 irr',rj i,:,

$fi

S*kst
*hik

Sg.
ffixitipl*x*n
B$

ET l**u *

b skt;
o*"o*

,i

Example: L -to-4 De-multiplexer

,,,,. F*
'1" F,l
*frldi"tx
,,,., Ff
,;==" F3

sr$*
Truth table

S1 i0 i,0 F1 F) r.3
l D
l D
1 D
1 ) D
Mux- nemux: Application Example

This eables sharing a single communication line among a number of devices. At any time, only
one souce and one destination can use the communication line.

C
*) *
L} ff*m*q:r"ri*"ati*n dtt
t-*

* ffi
s
{3
Example: Design a circuit to distinguish BCD digits > 5 from those < 5.

B
C
D
\BCD Minterm (A, B, C, D)
)000 0 p
)001 1

)010 2

)011 J

)100 4
)101 5

)1 10 6

)111 7

000 8

001 9

010 10

011 11

100 t2
101 13

110 t4
111 15

A
0l l1 l0

s0

01

l"
11

F l
I*
*-v** Ir-"-f-"-,

B B
{n} tuISOp (b) N.{POS
f(A,B,C,D) = A + BD+BC; f(A,B,C,D) - (A+ B)(A + C + D)
UNIT III
Flipflops Introduction - NAND LATCH, J K flipflop - J K Master - slave flipflop -
D flipflop and T flipflop - Registers and Counters: Shift registers - serial in -
parallelout, serial in - serial out, parallel in - serial out, parallel in - parallel out
shift registers - waye forms for the above - Counters - up counters, down counters,
decade counters, timing sequences, Mod - n counters.

Digital electronics is classified into combinational logic and sequential logic. Combinational logic
output depends on the inputs levels, whereas sequential logic output depends on stored levels and also
the present inputs.

M*rr:*ry fii**tent

The memory elements are devices capable of storing binary info. The binary info stored in the memory
elements at any given time defines the state of the sequential circuit. The input and the present state of
the memory element determine the output. Memory elements next state is also a function of external
inputs and present state. A sequential circuit is specified by a time sequence of inputs, outputs, and
internal states.
There are two types of sequential circuits. Their classification depends on the timing of their signals:

' Synchronous sequential circuits

' Asynchronoussequentialcircuits

,/ ASYNCHRONOUS SEQUENTIAL CIRCTIIT

This is a system whose outputs depend upon the order in which its input variables change and can be
affected at any instant of time. Gate-fype asynchronous systems are basically combinational circuits with
feedback paths. Because of the feedback among logic gates, the system may, at times, become unstable.
Consequently they are not often used.

{ SYNCHRONOUSSEQT]ENTIALCIRCUITS

This type of system uses storage elements called flip-flops that are employed to change their binary
value only at discrete instants of time. Synchronous sequential circuits use logic gates and flip-flop
storage devices. Sequential circuits have a clock signal as one of their inputs. All state transitions in
such circuits occur only when the clock value is either 0 or 1 or happen at the rising or falling edges of
the clock depending on the type of memory elements used in the circuit. Synchronization is achieved
by a timing device called a clock pulse generator. Clock pulses me distributed throughout the system
in such a way that the flip-flops are affected only with the arrival of the synchronization pulse.
Synchronous sequential circuits that use clock pulses in the inputs are called clocked-sequential
circuits. They are stable and their timing can easily be broken down into independent discrete steps,
each of which is considered separately.

it
edgas 1.-ig-gi:,$
"w
*yc$* Tirtls
A clock signal is a periodic square wave that indefinitely switches from 0 to 1 and from t to 0 at
fixed intervals. Clock cycle time or clock period: the time interval between two consecutive rising or
 falling edges of the clock.

Clock Frequency = I / clock cycle tine (measured in cycles per second or Hz)

Example: Clock cycle time = 10ns clock frequency = 100M

3.1 CONCEPT OF SEQUENIIAL LOGrC
A sequential circuit is a combinatimal logic with some feedback to maintain its current value, like a
memory cell. To understand the baiibs let's consider the basic feedback logic circuit below, which is a
simple NOT gate whose output is connected to its input. The effect is that output oscillates between
HIGH and LOW (i.e. 1 and 0). Osdlation frequency depends on gate delay and wire delay. Assuming
a wire delay of 0 and a gate delay d 10ns, then oscillation frequency would be (on time + off time =
20ns) 50Mhz.
propeg8tion delay
S-ffire d*xay + sat* delay)

The basic idea of having the feedba& is to store the value or hold the value, but in the above circuit,
output keeps toggling. We can ovtrcome this problem with the circuit below, which is basically
cascading two inverters, so that the ftedback is in-phase, thus avoids toggling. The equivalent circuit is
the same as having a buffer with its otput connected to its input.

The circuit below is the same as theinverters connected back to back with provision to set the state
of each gate (NOR is gate with bot& inputs shorted like a inverter). I am not going to explain the
operation, as it is clear from the truthtable. S is called set and R is called Reset.

t R 0 Q+
) 0 0 )
) 0 1 I
) 1 x )
0 x
1 X )

There still seems to be some problerxwith the above configuration, we cannot control when the input
should be sampled, in other words trere is no enable signal to control when the input is sampled.
Normally input enaHe signals can be of two types.
./ lrvel Sensitive s ( LATCH)
{ Edge Sensitive cr (Flip-Flop)

Level SensitiveThe circuit below is a modification ofthe above one to have level sensitive enable
input. Enable, when LOW, masks the input S and R. When HIGH, presents S and R to the
sequential logic input (the above circuit two NOR Gates). Thus Enable, when HIGH, transfers
input S and R b the sequential cell transparently, sr this kind of sequential circuits are called
transparent L*ch. The memory element we get is anRS Latch with active high Enable.

e J***a
I
fi- l***/
,JI
l--"

r-r
I
n-q
C*r- I
o {*i
Edge Sensifve: The circuit below is a cascade of *rvo level sensitive memory elements, with a
phase shift k the enable input between first memory element and second memory element. The
fust RS latcl (i.e. the tirst memory element) will b enabled when CLK input is HIGH and the
second RS lrtch will be enabled when CLK is L0$/. The net effect is input RS is moved to Q
and

Q' when G,K changes state from HIGH to LOW, this HIGH to LOW transition is called
falling edge So the Edge Sensitive element we geflis called negative edge RS flip-flop.
 3.2 LATCIMS AND FLIP.FLOPS

There are two types of sequential circuits.

o AsynchronousCircuits.
o SynchronousCircuits.
Latches and Flip-flops are one and the same with a slight variation: Latches have level sensitive control
signal input and Flip-flops have edge sensitive control signal input. Flip-flops and latches which use
this control signals are called synchronous circuits. So if they don't use clock inputs, then they are
called asynchronous circuits.

{ RS Latch

RS latch have two inputs, S and R. S is called set and R is called reset. The S input is used to produce

HIGH on Q ( i.e. store binary 1 in flip-flop). The R input is used to produce LOW on Q (i.e. store
binary 0 in flip-flop). Q' is Q complementary output, so it always holds the opposite value of Q. The
output of the S-R latch depends on current as well as previous inputs or state, and its state (value
stored) can change as soon as its inputs change. The circuit and the truth table of RS latch is shown
below.

n
S R 0 Q+
l 0 0 )
l 0 1 1

l 1 X )
1 0 X 1

,s 1 1 x )

The operation has to be analyzed with the 4 inputs combinations together with the 2 possible previous
states.
. WhenS=0andR=0:If we assumeQ= l andQ'=0asinitialcondition,thenoutputQafter
input is applied would be Q = (R + Q')' = 1 and Q' = (S + Q)' = 0. Assuming Q = 0 and Q' = I as
initial condition, then output Q after the input applied would be Q = (R + Q')'= 0 and Q' - (S +
Q)'
= 1. So it is clear that when both S and R inputs are LOW, the output is retained as before the
application of inputs. (i.e. there is no state change).
. WhenS= L andR=0: If we assumeQ= l andQ'=0 asinitialcondition, thenoutputQafter
inputisappliedwouldtreQ=(R+Q')'=1andQ'=(S+Q)'=0.AssumingQ=0andQ'=1as
initial condition, thenoutput Q afterthe input applied wouldbeQ - (R + Q')'= 1 and Q'= (S +
Q)'
 = 0. So in simple words when S is HIGH and R is LOW, ortput Q is HIGH.
WhenS=0andR=L:IfweassumeQ=1andQ'=0aninitialcondition,thenoutputQafter
input is applied would be Q = (R + Q')' = 0 and Q' = (S + 8)' = 1. Assuming Q = 0 and Q' = 1 as
initial condition, then output Q after the input applied wodd be Q - (R + Q')' = 0 and Q' = (S +
Q)'
= 1. So in simple words when S is LOW and R is HIGH, odput Q is LOW.
When S = 1. and R =1 : No matter what state Q and Q' am in, application of 1 at input of NOR
gate always results in 0 at output of NOR gate, which resuh in both Q and Q' set to LOW (i.e. Q
= Q').LOW in both the outputs basically is wrong, so this case is invalid.

The waveform below shows the operation of NOR gates based RSLatch.

It is possible to construct the RS latch using NAND gates. The circuit and Truth table of RS latch
using NAND is shown below.

l R 0 )+
1 1 0
1 1 1

) 1 X
1 0 x
) 0 x
RS Lat& with Clock

We have seen this circuit earlier with two posible input configurations: one with level sensitive input
and onewith edge sensitive input. The circuitbelow shows the level sensitive RS latch. Control signal
"Enable'E is used to gate the input S and R to the RS Latch. When Enable E is HIGH, both the AND
gates ac{ as buffers and thus R ard S appears at the RS latch input and it functions like a normal RS
latch. $&en Enable E is LOW, it drives LOWto both inputs of RS latch. As we saw in previous page,
when beh inputs of a NOR latch are low, valws are retained (i.e. the output does not change).

Setup ad Hold Time -For synctnonous flip-flops, we have special requirements for the inputs with
respect b clock signal input. They are,

Stup Time: Minimum tirne period duing which data must be stable before the clock makes a
ralid transition. For example, for a po dge triggered flip-flop, with a setup time of 2 ns, lnput
Ilata (i.e. R and S in the case of RS flip-flop) should be stable for at least 2 ns before clock
nakes transition from 0 to l.
Eold Time: Minimum time period duing which data must be stable after the clock has made a
ralid transition. For example, for a poredge triggered flip-flop, with a hold time of 1 ns. Input
Ihta (i.e. R and S in the cme of RS ffo-flop) should be stable for at least 1 ns after clock has
qade transition from 0 to 1.

If data rmkes transition within this setup win&w and before the hold window, then the flip-flop output
is not psdictable, and flip-flop enters what is tnown as meta stable state. In this state flip-flop output
oscillate* between 0 and 1. It takes some tirre for the flip-flop to settle down. The whole process is
called nrctastability.
The waveform below shows irput S (R is not shown), and CLK and output Q (Q' is not shown) for a SR
posedge flip-flop.

* I {*
hcld tirna
$trt!.ip t*::* $f

tlj
.I

{ D Latch

The RS latch seen earlier conuins ambiguous state; to eliminate this condition we can ensure that S and
R are never equal. This is dorr by connecting S and R together with an inverter. Thus we have D Latch:
the same as the RS latch, wittrthe only difference that there is only one input, instead of two (R and S).
This input is called D or Dm input. D latch is called D transparent latch for the reasons explained
earlier. Delay flip-flop or delry latch is another name used. Below is the truth table and circuit of D
latch. In real world designs (ASIC/FPGA Designs) only D latcheslFlip-Flops are used.

D ? ]+
1 K
0 K I

Below is the D latch waveforr4 which is similar to the RS latch one, but with R removed.

,.!J; 11
{.-. I l
1
 r' JKLEtch

The ambiguus state output in the RS latch was eliminated in the D latch by joining the inputs with an
inverter. But D latch has a single input. JK latch is similar to RS latch in that it has 2 inputs J and K
lilre
as shown figure below. The ambiguous state has been eliminated here: when both inputs are high,
output toggler. The only difference we see here is output feedback to inputs, which is not there in the RS
latch

J K 0
I 1 0
1 I 1

1 0 1

0 1 0

r' T L*ch

When the tua inputs of JK latch are shorted, a T Latch is formed. It is called T latch as, when input is
held HIGH, ortput toggles.

T o l+
1 0
1 1

0 1

0 0
 r' JK Master Slave Flip-Ftop

All sequential circuits that we have seen in the last few pages have a problem (All level sensitive
sequential circuits have this problem). Before the enable input changes state from HIGH to LOW
(assuming HIGH is ON and LOW is OFF state), if inputs changes, then another state transition occurs
for the same enable pulse. This sort of multiple transition problem is called racing.
If we make the sequential element sensitive to edges, instead of levels, we can overcome this problem,
as input is evaluated only during enable/clock edges.

CLH

In the figure above there are two latches, the flrst latch on the left is called master latch and the one on
the right is called slave latch. Master latch is positively clocked and slave latch is negatively clocked.

l
3.3 SEQTIENTAL CIRCUITS DESIGN

We saw in the conbinational circuits section how to dsign a combinational circuit from the given
problem. We conwrt the problem into a truth table, then draw K-map for the truth table, and then
finally draw the gde level circuit for the problem. Similuly we have a flow for the sequential circuit
design. The steps re given below.

. Draw state {iagram.

. Draw the sfite table (excitation table) for each outprt.
. Draw the K+nap for each output.
. Draw the cftcuit.

State Diagram -The state diagram is constructedasing all the states of the sequential circuit in
question. Itbuilds up the relationship between various states and also shows how inputs affect
the states.
Lct's consiler designing the 2 bit up counter Einary counter is one which counts a binary
sequence) uing the T flip-flop.

DESIGN

o State Tat& - The state table is the same as the o<citation table of a flip-flop, i.e. what inputs
need to beapplied to get the required output. In drer words this table gives the inputs required
to producethe specific outputs.

D1 l0 U+ )o+ T1 TO

0
 K-map -The K-map is the same as the combinational circuits K-map. Only difference: we draw
K-map for the inputs i.e. T1 and t0 in the above table. From the table we deduct that we don't
need to draw K-map for T0, as it b high for all the state combinations. But for T1 we need to
draw the K-map as shownbelow,using SOP.

s{
T1 ffi*
Circuit- There is nothing specid in drawing the circuit, it is the same as any circuit drawing
from K-map output. Below is thecircuit of 2-bit up counter using the T flip-flop.

"* i ",i

ry L+l
T,:,,:-f-----*1* --f-L,
{: i-1d.

1.4 SHIFT REGISTER

tegister:
A set of n flip-flops.
Sach flip-flop stores one bit.

Two basic functions: data storage and datamovement

flhift Register:
'f,. register that allows each of the flip-flogs to pass the stored information to its adjacent neighbor.

.Ashift register is a cascade of Flip flopt sharing the same clock, which has the output of any one but
fu last flip-flop connected to the "data" input of the next one in the chain, resulting in a circuit that
slifts by one position the one- dimensiond "bit array" stored in it, shi{-ting in the data present at its input
ad shifting out the last bit in the array, vhen enabled to do so by a transition of the clock input. More
gmerally, a shift register may be multidknensional, such that its "data in" input and stage outputs are
tbmselves bit arrays: this is implementod simply by running several shift registers of the same bit-
logth in parallel.

Types of shift register

Shift registers can have a combination of serial and parallel inputs and outputs, including serial-in,
parallel-out (SIPO) and parallel-in, serial-out (PISO) types. There are also types that have both serial
and parallel input and types with serial and parallel output. T&ere are also bi-directional shift registers
which allow you to vary the direction of the shift register. Theserial input and outputs of a register can
also be connected together to create a circular shift register. One could also create multi-dimensional
shift registers, which can perform more complex computation.

r' Serial-in,serial-out

Destructive readout- These are the simplest kind of shift regnter. The data string is presented at 'Data
In', and is shifted right one stage each time 'Data Advance' is Srought high. At each advance, the bit on
the far left (i.e. 'Data In') is shifted into the first flip-flop's outpt. The bit on the far right (i.e. 'Data Out')
is shifted out and lost.The data are stored after each flip-flop sr the 'Q' output, so there are four storage
'slots' available in this arrangement, hence it is a 4-Bit Registr. To give an idea of the shifting pattern,
imagine that the register holds 0000 (so all storage slots are erryty).

As'Data In'presents 1,1,0,1,0,0,0,0 (in that order, with a pulse at'Data Advance'each time. This is
called clocking or strobing) to the register, this is the result. The left hand column corresponds to the
left-most flip-flop's output pin, and so on.So the serial output of the entire register is 1 10 10000 O. As
you can see if we were to continue to input data, we would pt exactly what was put in, but offset by
four 'Data Advance' cycles. This arrangement is the hardwareequivalent of a queue. Also, at any time,
the whole register can be set to zero by bringing the reset @) pins high. This arrangement performs
destructive readout -each datum is lost once it been shifted outof the right-most bit.

Non-destructive readout- Non-destructive readout can be acheved using the configuration shown

below. Another input line is added - the Read/Write Control. When this is high (i.e. write) then the shift
register behaves as normal, advancing the input data one plare for every clock cycle, and data can be
lost from the end of the register. However, when the R./W codrol is set low (i.e. read), any data shifted
out of the register at the right becomes the next input at the let, and is kept in the system. Therefore, as
long as the R/W control is set low, no data can be lost from thesystem.

Example: Basic four-bit shift register

rrtr rr1 Fr3

Sat* i Sat* uutFut
The opaation of the circuit is as follows,

o Ehe register is first cleared, forcing all four outputs to zero.

o Ette input data is then applied sequentially to the D input of the first flip-flop on the left (FF0).
o During each clock pulse, one bit is transmitted from left to right. Assume a data word to be 1001.
o fhe least significant bit of the data has to be shifted through the register from FFO to FF3.

In orda to get the data out of the register, they must be shifted out serially. This can be done
destrucively or non-destructively. For destructive readout, the original data is lost and at the end of the
read cple, all flip-flops are reset to zero.

tr0 tF1 7F2 FF3

) 1001

The daa is loaded to the register when the control line is HIGH (ie WRITE). The data can be shifted out
of the egister when the control line is LOW (ie READ).

Clear FFO tF1 ]F2 iF3

001 ) )

Write
tr0 F'F1 7F2 tF3
) ) )000

Read
tr0 iF1 1F2 :-F3
) 001

{ Serial-in,parallel-out

This cmfigwation allows conversion from serial to parallel format. Data are input serially, as described
in the SISO section above. Once the data has been input, it may be either read off at each output
simultaeously, or it can be shifted out and replaced.

Itgut
In the table below, we can see how the four-bit binary number 1001 is shifted to the Q outputs of the
register.

Clear tF0 FF1 W2 iF3

1001 ) )
)
1 0
) I
)

/ Parallel-in,serial-out
This configuration has the data input on lines D1 through D4 in parallel format. To write the data to the
register, the Write/Shift control line must be held LOW. To shift the dara the WS control line is
brought HIGH and the registers are clocked. The arrangement now acts as a SISO shift register, with D1
as the Data Input. However, as long as the number of clock cycles is not more than the length of the
data-string, the Data Output, Q, will be the parallel data read off in order.

Exlmplel A four-bit parallel in - serial out shift register is shown below. The circuit uses D flip -flops
and NAND gates for entering data (ie writing) to the register.

D0, D1, D2 and D3 are the parallel inputs, where D0 is the most significant bit and D3 is the least
significant bit. To write data in, the mode control line is taken to LOW and the data is clocked in. The
data
can be shifted when the mode control line is HIGH as SHIFT is active high. The register performs right
shift operation on the application of a clock pulse, as shown in the table below.
 / Pardlel-in,parallel-out
This configwation allows conversion from parallel to parallel format. Data input are in parallel, as
described in the PISO section above. Once the data has been input, it may be either read off at each
output simuhneously, or it can be shifted out and replaced.

Q0 u c2 Q3
len ) )
Wrl€ 1 1

shift 1 1

1 )
1 1 ) 1

1 1 )01
1 1 001

The D's are *te parallel inputs and the Q's are the parallel outputs. Once the register is clocked, all the
data at the Dinputs appear at the corresponding Q outputs simultaneously

{ Unirersal shift register

A register cryable of shifting in one direction only is a unidirectional shift register .One that can shift

in both direcions is a bidirectional shift register. If the register has both shifts and parallel-loads, it is
referred as rniversal shift register. The circuit consists of four D flip-flops and four multiplexers. The
four multiplexers have two common selection inputs st and so.
 Figure: Block diagram of 4-bit universal shift register.

FornHeI o*rynrr$

{-f***.r

f.-f;#

$*rinl $ari;rl
lnput fre.* icrf{ri flrr
*t$ifl.risht *rr{i-left

Pordlel icpur*

Mode control Register

il. ;0 )peration
) ) {o change
) 1 ihift right
) ) ihift left
1 1 larallel load

Applications of shift registers

Shift registers can be found in many applications. Here is a list of a

few. 1. To produce time delay
The serial in -serial out shift register can be used as a time delay device. The amount of delay can be
controlled by:
1. The number of stages in the register
2. The clock frequency

3. To convert serial data to parallel data

4. To simplify combinational logic.

3.5 COI.]NTERS
 In digital logic and computing, a counter is a device which stores (and sometimes displays) the
number of times a particular event or process has occurred, often in relationship to a clock signal. In
practice, there are two types of counters:
. up counters which increase (increment) in value
o down counters which decrease (decrement) in value

Counters Types

In electronics, counters can be implemented quite easily using register-type circuits such as the flip-
flop, and a wide variety of designs exist,
/ Asynchronous (ripple) counters
/ Synchronous counters
/ Johnsoncounters
/ Decadecounters
r' Up-Do*n counters
/ Ring counters

Each is useful for different applications. Usually, counter circuits are digital in nature, and count in
binary, or sometimes binary coded decimal. Many types of counter circuit are available as digital
building blocks, for example a number of chips in the 4000 series implement different counters.

{ Asynchronous (ripple) counters

The simplest counter circuit is a single D+ype flip flop, with its D (data) input fed from its own
inverted output. This circuit can store one bit, and hence can count from zero to one before it overflows
(starts over from 0). This counter will increment once for every clock cycle and takes two clock cycles
to overflow, so every cycle it will alternate between a transition from 0 to 1 and a transition from 1 to 0.
Notice that this creates a new clock with a 507o duty cycle at exactly half the frequency of the input
clock. If this output is then used as the clock signal for a similarly arranged D flip flop (remembering to
invert the output to the input), you will get another 1 bit counter that counts half as fast. Putting them
together yields a two bit counter:

{ Synchronous counters

Where a stable count value is important across several bits, which is the case in most counter systems,
synchronous counters are used. These also use flip-flops, either the D-type or the more complex J-K
type, but here, each stage is clocked simultaneously by a common clock signal. Logic gates between
each stage of the circuit control data flow from stage to stage so that the desired count behavior is
realized. Synchronous counters can be designed to count up or down, or both according to a direction
input, and may be presetable via a set of parallel 'Jam" inputs. Most types of hardware-based counter
are of this type.

A simple way of implementing the logic for each bit of an ascending counter (which is what is shown in
the image to the right) is for each bit to toggle when all of the Iess significant bits are at a logic high
state. For example, bit 1 toggles when bit 0 is logic high; bit 2 toggles when both bit 1 and bit 0 are logic
high; bit 3 toggles when bit z,bit I and bit 0 are all high; and so on.

r' Johnson counters

A Johnson counter is a special case of shift register, where the output from the last stage is inverted and
fedback as input to the first stage. A pattern of bits equal in length to the shift register thus circulates

in&finitely. These counters are sometimes called "walking ring" counters, and find specialist
ap$ications, including those similar to the decade counter, digital to analogue conversion, etc.

Clcek PrS** $3 *3 *{ {}$

m * * n il
I} il il
I u & 1 t
3 u 1 1
I
+ 1 1 I
,|
J 1 1 il
& 1 il il
? 1 fi fi il

Thc apparent disadvantage of this counter is that the maximum available states are not fully utilized.
Or$ eight of the sixteen states are being used.

/ Decade counters

Derade counters are a kind of counter that counts in tens rather than having a binary representation.
Ea& output will go high in tum, starting over after ten outputs have occurred. This type of circuit finds
apf,ications in multiplexers and demultiplexers, or wherever a scanning type of behaviour is useful.
Sinilar counters with different numbers of outputs are also common.

{ Up-Down Counters

It ica combination of up counter and down counter, counting in straight binary sequence. There is an up-
dovn selector. If this value is kept high, counter increments binary value and if the value is low, then
counter starts decrementing the count. The Down counters am made by using the complemented
output to act as the clock for the next flip-flop in the case of Asynchronous counters. An Up counter
is constructed by linking the Q out of the J-K Flip flop and puttlrg it into a Negative Edge Triggered
Clock input. A Down Counter is constructed by taking the Q output and putting it into a Positive
Edge Triggered input

{ Ring Counters

A ring shift register in whidr the output of the most significant

counter is basically a circulating
stage is fed back to the input of the least significant stage. The following is a 4-bit ring counter
constructed from D flip-flops. The output of each stage is shifed into the next stage on the positive
edge of a clock pulse. If the CLEAR signal is high, all the flip -flops except the first one FFO are
reset to 0. FFO is preset to 1 instead.

Since the count sequence has 4 distinct states, the counter ca be considered as a mod-4 counter.
Only 4 of the maximum 16 states are used, making ring courtrers very inefficient in terms of state
usage. But the major advantage of a ring counter over a binaryeounter is that it is self-decoding. No
extra decoding circuit is needed to determine what state the cornter is in.

fiks* PnM &3 0fr ffit ffi

il il il I 1

il
t tr il I U
1
L il 1 fi fi
?
1 il fi r'!

Applications of counters:

. Watches
. Clocks
. Alarms
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T]NIT IV

Multivibrators Classification of multiuibrators - Astable, monostable, bistable

multivibrators using operational amflifier. D/A and A/I) converters: Binary
weighted register D/A converter using Op-Amp - R-2R ladder D/A converter
with Op-Amp - Analog to Digital convmters (ADC) - their characteristics.

lntroduction

Systems for generating and processing pulses make extensive use of multivibrators; these are
circuits which have two states. There are three types of multivibrator: astable (free-running),
monostable (one-shot), and bistable (flip-flop) There are many ways of implementing each type,
and many variants.

Note: All the circuits in this document operate by using positive feedback to drive the op-amp into
saturation, it is therefore not the case that the tvo inputs of the op-amp can be assumed to be at the
same potential. See the comments on Worksheetl0 regarding op-amps vs comparators.

Astable Multivibrator

The two states of circuit are only stable for a [mited time and the circuit switches between them
with the output (node 6) alternating between po*itive and negative saturation values +VS. Analysis
of this circuit starts with the assumption that at t*ne r = 0 the output has just switched to state 1 (V6
= *VS ), and the transition would have occurred ryhen

v2 = v6(state 0)
k
where v6 (state 0) = ys
In state 1, the voltage across the capacitor increases as a result of current flowing through R3 from

r-l
t

R1,R2 1KO R1,210K

R3 2K7 R3 2K2
R4 lKO
Cl 0p1 C1 0p1
CZ 10n
Astable Multivibrator Monostable Multivibrator
 I
its initial valueV2(t=0) = - Vs R2/(R1+R2)

until V2(t=0)=V3(state 1) = Vs R2(R1+R2)

when the outprt from the op-amp switches back to state 0. Then the capacitor discharges until, at
time = 0 , the output switches from state 0 back te state 1, and the whole sequence restarts. t is
straightforwad to show that

to= CrR:ln(1€Rz/Rr)

Monostable Mu ltivibrator

A diode con-rected in parallel with the timing capacitor of the astable circuit will prevent the
inverting inprrof the amplifier from going positive. The (permanently) stable state of
this circuit has
V6=Vs with node 2 clamped to il.6 Vby diode D 1, and node 3 at

V3(state l) = 0.6 V +

Vs Ry'(& + R+)

A sufficiertly large pulse at

node 3, generded by a negative-going edge at the trigger input (node 1), will switch the circuit into
its temporary $ate ( 6= S ) and, afteradelay

fi= CtR3tn i+ {1
fil
.l_l

t.l 1K0
R2 220
R3 100

C1 1ON

Circuit; B istable Multivibrator

while cl charges through R3, the circuit switches lack to its stable state.

Bistable Mu ltivibrator

The above circuit shows an op-amp configured a* a bistable multivibrator. The two stable states
arcV6 = *VSS and the circuit is switched betweenthese by a pulse of appropriate polarity applied
to the inverting terminal (node 2) of the op-amp.

D/A and A/D Converters

Introduction

The outputs from sensors and communications receivers are analogue signals that have
continuously varying amplitudes. In many systens it is convenient to record and/or process these

signals within a digital circuit, which may b within a programmable device such as a
microcontroller, microprocessor or a computer. h a digital circuit the signal will be represented
as a list of binary numbers, with each number representing the amplitude of the signal at a

specific time.

Decimal and Binary Numbers

Possibly because we have ten fingers vre have developed the decimal number system
based upon 10 and powers of 10. Although it is suitable for use by people the decimal number
system isn't particularly suitable for use by otherphysical sysrems. tn particular the digital logic
circuits are based upon devices that either conducr or don't conduct. This means that digital logic

circuits naturally have two states. This means tlat in digital logic circuits numbers have to be
represented using only two symbols, usually writen as 0 and 1. This means that digital circuits
use binary numbers.

A good starting point for understanding tinary numbers is the decimal numbers that we
use everyday. We have all used this decimal nwrber system for so long and so often that we
probably don't think about what numbers
this decimal sysbm actually represent. In this number system each position represents the
multiples of the gower of l0 associated with that position that form part of the number. To
represent these mmbers we need 10 symbols (0,1,2,3,4,5,6,7,8,9) to represent the number of
multiples. The dacimal 1206 then represents 1x103+2x102+0x101+6x100 (which is one thousand,
two hundred and rix).

The digitd circuits used in programmable devices have only two states and by convention
these two states re denoted using the symbols 0 and l. With only two states/symbols available
numbers have to te represented as powers of 2 rather than powers of 10. As in the decimal system
counting in binary starts with 0 and this is followed by 1. In the decimal system the next number
is representing h the symbol 2. However in binary there are only two symbols and so the next
number has to be represented by increasing the power of 2 and so when counting in binary 1 is
followed by 10 $following the example of decimal this is equivalent to the decimal number
1x2l+0x20;. Morc generally as in decimal numbers any binary number can be understood using
the associated pwers of 2. For example

1010 = 1 x 23+0 x22+l x2t+O x20

Converting each nf the powers of 2 to its decimal equivalent means that

Decimal equivalent of 1010 = 1x 23+0 x22+l x 2l+0 x20 = I x 8+0 x

4+1 x2+0xl=10
Emh symbol in a binary number is known as a bit and a binary number is therefore a list or string
ofbits. The first bit in a string is known as the most-significant bit and the last one is known as

the least significant bit. One convention is to label each bit with a subscript corresponding to the
eqivalent power of 2, so that for example the least significant bit (which represents the multiple
of20 within a binary number) is bs. In this convention a four bit number is therefore b: bz br bo
ad the equivalent number is

Decimal = b: x 23 + b2 x 22+ b1 x 21 + bs x 20

&e limitation of this simple representation is that an n-bit binary number can only represent 2 '
dtferent values.

lHa Converters

Cmversion from an analogue signal to a digital number is performed by an analogue-to-

d&ital converter (ADC). There are several different types of ADCs, some of which contain a
dftital-to-analogue converter (DAC) that converts a digital number to the equivalent
anlogue signal. When taken together with their independent role in creating analogue output
signals to drive parts such as heaters and motors, this makes DACs a critical part of many
sy*tems.

Itb therefore important to understand the operation of both DACs and ADCs.
Specification of D/A converters (DACs)

A
n
a
t
0
d
E
u
e

o
rl
t
p
lt
t

flofl $*I slCI 011 t00 Isl u0 Iu

DiEitrI Inpux

The ideal response of a 3-bit DAC, showing the analogue output voltage as a fraction

of the full scale output FS. Each bar represents the output for a particular input and the
dashed line shows the line connecting the ideal outputs.

A digital to analogue converter (DAC) converters a digital input represented as a binary

number to an analogue voltage (or current) that is proportional to the value of this input.
The ideal relationship between the analogue output and digital input for a 3-bit converter is
shown in Figure Qqr.

1
In this diagram 3 bits have been shown for clarity. However, in real instrumentation systems
DACs with 8, 10, 12 and 14 bits are often used.
D/A Converter Architectures (DAC Architectures)

The Sunming Amplifier

The ba$is operation required to create a DAC is the ability to add inputs that will eventually
correspnd to the contributions of the various bits of the digital input. In the voltage domain,
that is if the input signals are voltages, addition can be achieved using the inverting summing
ampliftr shown in Figure (35).

::
An inverting summing amplifier

To undbrstand how this circuit operates assume that the op-amp is ideal. Since the op-amp is

ideal H* : Ht, but, in this circuit I"* : ff and so the current flowing into this node
from tb two inputs is

,rn
.t{Vz
_ ,
J?r Jt,
Since so curent flows into the inverting input of the ideal op-amp all this current must

flow amund the feedback loop tkough resistor ftfh.

 This will only happen when the op-amp output voltage is

l'Lur : -J6" *14

which becomes

/ H1 ft1r, ki Jtf
yo*r_---ft;-
|
--ft;..-
a

- Now if we assume that

Jtft:,1?r=2ftr
then

!i*r: -(zl,i11,:)
This weighted combination of inputs is the principle behind the operation of
many digital-to-analogue csrverters.
D/A Conver*rs

The simplestway of convert a digital input word into a corresponding analogue voltage is to
an op-amp asa summing amplifier with a weightd resistor "ladder", as shown in Figure (36).
Aualosua str.itrhee

5l R:=rR

51 q{R.

=
A 4-bit DAC based upon summirg the current through weighted
resistors.

At the start d the conversion process, a 4-bit inpt code , BO -ff* i, applied to control the
correspondhg switche, 5h - Sr .gu"h switch Sr, the resistor ftr, to the voltage
"orrr".ts
Ii
source v frEF when the corresponding
Ui #* is high. ln contrast when Sn. i, low the resistor En is grounded. The other end of
each resistor is connected to the smming junction of the op-amp. For a four bit converter in
which the resistors are in the ratio
8:4:2: l, as shown in Figure (36), the total current flowing onto the inverting input of the op-

amp is
,
Bo, ,, D
r,n:?"nsr(*+*+*
ft '2R'.4R+*nJ
this current then flows through & ,o generate the output voltage and hence

lt*-# tr&rr(B* .+.+**t

The output voltage trln thereforerepresents a weighted sum of the input bits. If ft * ?.ffir tn.r,
the following relationship betwea digital inputs and the

analogue output voltage will be c*tained:

trigital inpu| y"

fi*0s 0
0s01 - 1/ 16 !'asr
fi010 -?/16 ltsr

1110 -14116 1&rr

1111 -15/16 \hsr
The circuit therrfore achieves the desired functions. However, there are two main
problems with tht circuit:

(i) the ou$ut voltage from the reference voltage source must stay constant even
when its odput current is changing, i.e. its source resistance must be zero.

(ii) the reristor values must be very accurate and in the correct ratio to one another.
Although *ris requirement can be achieved in an integrated circuit, the range of
values regired for, say, a 12-bit D/A converter (for example, 10 kO to 20.48 MO)
makes it irpractical.

For these reasons, a different type of resistor network is normally used, the "R-2R ladder",
which can be consructed, as its name indicates, out of two values of resistors. This network,
shown at the top of Figure (38), therefore avoids the need to create different resistance
values.
 fte two parallel resistors share the cr.rrent I
I
s =lr:

ZR-a parallel with 2R is eqrlvalent to R rl-r -:r0

The analysis of an R-2R ladder network

lhe trick to analysing the R-2R ldder network is to start from its right-hand end: As
*own in Figure (37) at this end of 6e system there are two 2R resistors acting in parallel
rhich combine to form an effectiveresistance R. This effective resistance then appears in
reries with another resistance R b form a resistance of 2R. However, this effective
rcsistance of 2R is in parallel wit another resistance 2R. Thus at each stage of the
eralysis of the ladder network, all ebments to the right of a particular node are equivalent
b a resistance of 2R.
 :
Ae R-2R ladder 4-bit D/A converter.

The analysis of the [adder network means that for the network in Figure (38) the
incoming current spBs into two at each node and thus
It*2I1:46
and

J:r * trhnr1?R - ZIa * 41i * 8Ic

As with the previous crtcuit, each bit S" of the digital code controls a switch

Srr. when F" * I, the switch '5n directs current J., towards the summing junction;
otherwise the current flows straight down to ground. The DAC output voltage is therefore
determined by a currefi that is proportional to the weighted sum of the input bits as required.

The other advantage of this architecture is that the inverting input of the op-amp is a
virtual eadh and herce one end of each the 2R resistors is always connected to 'earth'. This
means that the current flowing through each branch of the ladder network is independent

of the switch
conditicrs and hence the digital input. Thr significance of this is that it means that the
total curent supplied by the voltage sourre is constant and the circuit performance is
independent of the output impedance of thevoltage source.

One p@ntially useful modification to this baric architecture is to use a variable voltage source,

possibly formed by a second DAC, to create a variable reference voltage. The analogue output

signal i* then proportional to the product of &e variable reference voltage and the input binary
numbeq this type of device is usually known s a multiplying DAC or MDAC.
A/D converters (ADCs)

Analogue to Digital (A/D) conversion is the process whereby an analogue signal is

converted into a corresponding binary number, the digital output. The ideal relationship
between the analogue input and the digital output for a 3-bit A/D converter is shown in Figure
(39). The input analogue values are quantised by dividing the continuous analogue input
range into 8 discrete steps or code ranges.

1I"1
i
$ t
i IECI &a
I
C a
E a
i lgl {
t
it TBff -
x

o sil
+
a
I
& I
f

t sn$
a

p
s s&t +
t
s80
1J8 H4 3Jg lE 5lt8 3,,1+ 7/S

Input }'altagr {frattion of, maxirsuru inputl

The ideal response of a 3-bit ADC.

Since the ADC is unable to distinguish among different values in the same code range the

output can have an error as large as 1/2ISB. This quantisation errof is an intrinsic
limitation of representing a continuous input by afinite set of output numbers. The first approach

to minimising the effects of quantisation errsrs is to ensure that the maximum expected
amplitude of the input signal matches the inpat range of the ADC. This usually means that

amplifiers are needed between the signal sourceand the ADC. By using an active low-pass filter

this amplification function can be performed by &e anti-aliasing filter.

The other method of reducing quantisation errcf, is to increase the number of output bits. For

example 2r2 4096 and hence a l}-bit A/D conwrter can resolve a signal to 1 part in 4096, or

0.0247o of the maximum input.

The two types of A/D converter that we will discuss are: Parallel
converters
Successive-Approximation converters
The choice between the types of converter is made on the grounds of the cost, resolution and

speed required for a particular application.

Parallel ADCs

15
to
.t
liae .t-b.ir
de(odrr a'rrffua'
O-qn;

Corymatore

A schematic diagram of a flash A/D converter.

Parallel encoding (sometimes known as "flash" encoding) is the fastest (but also the most
expensive) method of A/D conversion. In this architecture, shown in Figure (40) an n-bit
conversion is achieved by simultaneously comparing the analogue input with 3t' - I
reference levels. These reference levels are usually generated by a chain of identical resistors

connected in series. Each of these references is compared to the input by

a circuit known as a comparator. This is a circuit uith a very high differential gain so
that the output raturates to a maximum value when the voltage on the non-inverting
input is higher than the voltage on the inverting inpd. Otherwise the comparator output
saturates to a mirimum value.

A comparator arny can therefore be designed so that dre outputs from all comparators whose

reference voltage ib below the common input saturate tsa maximum output value. The output of
all the other conparators will saturate at the minimus value whilst all those with references
above the input hare the minimum output voltage.

The maximum ortput voltage can then be interpreteGas a logical 1, whilst any low output

is interpreted asbgical0 so that the ?Tt - 1 outprrB represent the analogue input value
by the position d the transition between ones and leros. The position of the transition
between the onts and the zeros moves as the ardogue input voltage changes. This
representation istherefore often referred to as a thsmometer code. The final stage of the
conversion procees is to use a digital circuit, known s an encoder, to convert this unusual
representation of &e input to a more conventional binarynumber.

One advantage d the flash converter is that it is canceptually simple. However, its main
advantage is the ryeed at which conversion can be achiwed. Since the input is compared to all

the reference vahes simultaneously the time required to perform a conversion, a parameter
known as the conrersion time, is simply the response tiue for the comparators and
the encoder. This time is significantly shorter than the fastest altemative architectures. The flash

converter is therefore the fastest type of converter, the disadvantage of the flash converter
is the large number of comparators and resistors required. This means that these
converters will be expensive. Furthermore, as the number of comparators increases the voltage
difference between the reference inputs of two adjacent comparators reduces and the errors
between reference levels caused by variations between the values of individual resistors must
therefore be reduced. Since these variations are caused by slight differences in the sizes of
different resistors any reduction in errors will only be achieved by using larger area resistors.
Unfortunately, this simply further increases the cost of the final component.

Overall, flash converters are therefore fast, but, expensive.

Successive-Approxirnrtion ADCs

The successive-appruimation converter shown in Figure (41) operates by approximating

the analogue input slgnal with a binary code. This binary code is successively revising by
changing each bit in &he code until the best approximation is achieved. At each step in the
approximation, the pftsent estimate of the binary value corresponding to the analogue input
signal is saved in thr successive approximation register. The contents of this register are
converted to an analogre signal by a DAC so that a single comparator can determine whether the

approximation is largu'or smaller than the input signal.

As shown at the bottmr of Figure (41) the first approximation sets the most significant bit, the
MSB, of the successivc approximation register and resets all the other bits (i.e. makes them zero).
If the DAC output (u&ich is therefore equal, at this point, to half full-scale) is smaller than the
analogue input, the M$B is left on; if the DAC output is too large, then the MSB is turned off. ln
the next clock cycle, &e next most significant bit is set (i.e.'at the DAC output is now equal to
either 314 or ll4 of full-scale, depending on whether the most significant bit was left on or not)
and this new approxirnation is compared with the analogue input. Each successive bit is similarly
tested. After the least significant bit has been tested, the conversion is complete and the output
register contains the biaary code.
 C.1rI1palatilr

H
BrrTrsF

A schematic diagram of the architectwe of a successive-approximation ADC and the

irtemally generated analogue signal (sdid line) which is compared to the input (dashed
he).

If the accuracy of conversion is to equal the resolution of the converter, the input signal must
remah constant within the analogue valurof LI}LSB during the conversion time

To qtrantify the limitation this places on theftrput signals that can be converted accurately assume

that tb input signal is a sinusoidal wave of &equency/and peak-to-peak amplitud" l"nff-,i.".

tio t'ksp sin 2u"/f

For an n-bit converter, ll2 LSB (a simple estimate of the quantisation error) is equivalent to a

voltage of

* lknrlr"
The rate of change of the input signal is:

dtr;"
ffi a'"f I&xr cos ?n"J*
,f-
The maximum rate of change occurs when the input is zero and is given by:

I dx4"ldf l,*** * a'-f 1*#p

If the conversion time is **, then we must have:

this can be re-written as:

which is equivalent to a maximurn input frequency of

f1
Jrt.t.x. n f* Zn+t
For an 8-bit ADC with conversion time of 10 ps, this gives a maximum frequency of 62 Hz! This
is obviously much too low for most applications. The problem that limits the maximum frequency
that can be converted arises from the changes in the input signal during the conversion process.
These changes can be avoided by using a sample-and-hold circuit just before the ADC input. As
its name suggests this type of circuit samples the signal and then holds the sampled value until
the conversion process is completed and a new sample is acquired.
 $
oI{,

I
A sample-and-hold circuit.

The basic sample-and-hold circuit consists of an analogue switch and a storage capacitor, as
in the centre of Figure @2).T\e analogue switch is controlled by a signal, labelled Hold, which
allows the input signal to pass through to the capacitor during the aperture time and disconnects
}i'n
it during the hold time. The value of the input signat is therefore stored on the capacitor
during the hold time. The choice of a value for this capacitor is a compromise between the need
to minimise voltage changes caused by leakage currents during the hold interval (i.e. make C as
large as possible) and the need to follow high-frequency input signals without them being low-

pass filtered by the combination of the capacitor and the finite on-resistance of the switch (i.e.
make C as small as possible). In order to reduce leakage currents during the hold time, to
prevent voltage changes, the voltage on the capacitor is sensed using an op-amp configured
as a voltage follower. Similarly, the speed of the circuit is increased by detecting the input
signal via a second op-amp acting as unity gain buffer that
reduces the source impedance driving the capacitor during the aperture time.

With a sample-and-hold circuit on the input to a successive-approximation A./D converter the

maximum operating frequency of the converter is now given by

L/N"t*?o+r

where frr. is the aperture time which can be just a few tens of ns; hence input signals whose
frequency is several tens of kHz can now be converted to binary format with this type of A/D
converter.
Summary

The outputs fron sensors and communications receivers are analogue signals that have
continuously varyng amplitudes. In many systems it is convenient to record and/or process these

signals within a dfrital circuit, which may be a microcontroller, microprocessor or a computer. [n

a digital circuit &e signal will be represented as a list of binary numbers, with each number
representing the anplitude of the signal at a specific time.

In the digital circuits used in microcontrollers, microprocessors and computers numbers are
represented as a series of bits. Each bit can only have a value of either zero or one which means
that the number isin base 2.

Conversion from an analogue signal to a digital number is performed by an analogue-to-

digital converter {ADC). A digital to analogue converter (DAC) converters a digital input
represented as a hnary number to an analogue voltage (or current) that is proportional to the

value of this inpul

A DAC can be crated using an R-2R ladder and an op-amp.

Analogue to Dig*al (A/D) conversion (ADC) is the process whereby an analogue signal is
converted into a corresponding binary number, the digital output. The input analogue
values are quantked by dividing the continuous analogue input range into 2N discrete steps or
code ranges. Thisrounding error gives rise to quantisation noise, which can be estimated using

its maximum valte V**/2N*1

In a fhsh ADC the input voltage is compared in parallel with many different reference
voltagm. The resulting system is conceptually simple, fast but expensive.

A sucaessive-approximation converter operates by approximating the analogue input signal with

a binary code. This binary code is successively revising by changing each bit in the code until the
best ryproximation is achieved- The result is only valid if the input remains approximately
constet during the conversion time. This means that the maximum input frequency has to be
very snall or a sample and hold circuit is used to sample the input voltage before it is converted.
 I]NIT V
- Semiconductor Memories memory cell unit - ROM, RAM - Their classifications - ROM,
- PROM, EPROM, EEPROM, RAM,Static RAM, dynamir RAM, Memory read and
- memory write operations - Flash memory - Charge coupled Ihvice (CCD).

Read only memory devices are a special case of memory where, in normrl system operation, the memory
is read but not changed. Read only memories are non-volatile, that is, stored informa-tion is retained
when the power is removed. The main read only memory devices are listed below:

ROM (Mask Programmable ROM-also called "MROMs")

EPROM (UV Erasable Programmable ROM)

OTP (OneTime Programmable EPROM)

EEPROM {Electrically Erasable and Programmable ROM)

Flash Memory - This device is covered in Section 10.

HOW THE DEVICE WORKS

The ead only memory cell usually
consis of a single transistor (ROM
and IPROM cells consist of one
transhtor, EEPROM cells consist of
one, sne-and-a-half, or two transis-
tors). The threshold voltage of the
transi*or determines whether it is a
"1" gr "0." During the read cycle, a
voltagr is placed on the gate of the
cell. Ilepending on the programmed
threshold voltage, the transistor will or
will pt drive a current. The sense
ampliler will transform this current, or
lack dcurrent, into a "1" or "0." Figure
9-1 stows the basic principle of how a

ReadXInly Memory works.

Column

Row

To Output Bufler

Figure Read Only Memory Schematic

MASK PROGRAMMAELE ROMs

Mask programmable read-only aemories (ROMs) are the least expensive type of solid state memory.
They are primarily used for storiry video game software and fixed data for electronic equipment, such as
fonts for laser printers, dictiorary data in word processors, and sound data in electronic musical
instruments.

ROM programming is performedduring lC fabrication. Several process methods can be used to program a
ROM. These include

. Metal contact to conned a transistor to the bit line.

. Channel implant to creats either an enhancement-mode transistor or a depletion-mode

transistor.

. Thin or thick gate oxide,which creates either a standard transistor or a high threshold
transistor, respectively.

The choice of these is a trade-offbetween process complexity, chip size, and manufacturing cycle time. A
ROM programmed at the metd, contact level will have the shortest manufacturing cycle time, as
metallization is one of the last prmess steps. However, the size of the cell will be larger.

Figure 2 shows a ROM array propmmed by channel implant. The transistor cell will have either a normal

threshold (enhancement-mode 6rice) or a very high threshold (higher than VCC to assure the transistor

will always be off). The cell arra6 architecture is NOR. The different types of ROM architectures (NOR,
NAND, etc.) are detailed in the flarh memory section (Section 10) as they use the same principle.
Figure 3 shrws an array of storage cells (NAND architcture). This array consists of single tran-sistors
noted as derices 1 through 8 and 11 through 18 that t programmed with either a normal threshold

{enhancemmt-mode device) or a negative threshold (det'etion-mode device).

ROM Cell Sie and Die Size

The cell sie for the ROM is potentially the smallest d any type olmemoV device, as it is a single
transistor. *typical SMbit ROM would have a cell size ofabout 4.5pm for a 0.7pm feature size process,
2
and a chipre_a of aboutT6mm . An announced 64MbirROM, manufactured with a 0.6Fmfeature size,

has
22
a 1.23p cell on a 200mm die.

The ROM Focess is the simplest of all memory processs, usually requiring only one layer of polysilicon
and one lryr of metal. There are no special film depsition or etch requirements, so yields are the
highest among all the guivalent-density memory chips
Ground Diffusion

Selective

lmplant

To Raise

vT

ROW 1 (Polysilicon)

T:I

t4

Drain Diffusion

ROW 2 (Polysilicon)

-lni-
II Metal Columns

Figure OM Programmed by Channel lmdant

 woRD 6/16

woRD a/18

CONTROL UNE>.

SELECT LINE

BIT LINE

Souh: De,'Memory 1gg7' ' 1 9050

Figure . Memory Cell Schematic

Xultimedia Card

k 1996, Siemens announced the introductlonof a new solid-state memory chip technology that enables
fie creation of a multimedia card that is sized3Tmm x 45mm x 1.4mm, or roughly 40 per-cent the size of
rcredit card. lt is offered with either 15Mbit c 64Mbit of ROM.

PROM

PROM (UV Erasable Programmable Read Ody Memory) is a special type of ROM that is pro-grammed
dectrically and yet is erasable under UV light.

Ehe EPROM device is programmed by forcingan electrical charge on a small piece of polysilicon material
ftalled the floating gate) located in the memrry cell. When this charge is present on this gate, the cell is
"programmed," usually a logic "0," and whenthis charge is not present, it is a logic "1." Figure 9-4 shows
lhe cell used in a typical EPROM. The floatingpte is where the electrical charge is stored.

First-Level

Polysilicon +VG Second-Level

(Floating) Polysilicon

Figure. Double-Poly Stucture (EPROM/Flash MemoryCell)

Prior to being programtrcd, an EPROM has to be the EPROM, it is exposed to an
erased. To erase
ultraviolet light for appro<imately 20 minutes through a quartz window in its ceramic package. After
erasure, new informationcan be programmed to the EPROM. After writing the data to the EPROM, an
opaque label has to be phced over the quartz window to prevent accidental erasure.

Programming is accomp&hed through a phenomenon called hot electron injection. High voltages are
applied to the select gateand drain connections of the cell transistor. The select gate of the transistor is
pulsed "on" causing a laqe drain current to flow. The large bias voltage on the gate connection attracts
electrons that penetrate tte thin gate oxide and are stored on the floating gate.
EPROMf,oating Gate Transistor Characteristic Theory

The folloruing explanation of EPROM floating gate transistor characteristic theory also applies to EEPROM
and flas*devices. Figures 9-5 (a) and (b) show the cross section of a conventional MOS transistor and a

floatingpte transistor, respectively. The upper gate in Figure 9-5 (b) is the con-trol gate and the lower
gate, conpletely isolated within the gate oxide, is the floating gate.

Control

Gate
G oorong

\
Gate G

(a) Conventional lrOS (b) Floating-Gate MOS

 Figure 9-5. Cross Section of a Conventional MOS Transistor and a Floating-Gate MOS Transistor

Cp6 and Cp5 are the capacitances between the floating gate and the control gate and substrate,

respectively. VG and Vp are the voltages of the control gate and the floating gate, respectively. -QF is the
charge in the floating gate. (As electrons have a negative charge, a negative sign was added). ln an
equilibrium state, the sum of the charges equals zero.

(vo -v, ) cro + (o -v, ) crs- e =o

CA
('n)'

r r" c +c
FG Fs
Ice6+ce5/

VTg is the threshold voltage of the conventional transistor, and V166 is the threshold voltage of the
floati ng gate transistor.

C a
('n)'
V=
TCG
Lv
,.C
--

\ cru + c6l 'n+ Crs

q
F

V_V
TCG TO

C6

C
('o)

where uro =l-l'* andG =C66+Cp5

ICrc+Crs/
The threshold voltage of the floating gate transistor (VTCG) will be V16 (around 1V) plus a term
depending on the charge trapped in the floating gate. lf no electrons are in the floating gate, then VTCG

= VTO (around 1V). lf electrons have been trapped in the floating gate, then VTCG = VTO -Op/C6
(around 8V for a 5V part). This voltage is process and design dependent. Figure 9-6 shows the threshold
voltage shift of an EPROM cell before and after programming.

Programmed
 I
I I
' -OF Select Gate

V V
To sense ro;A vonase

Threshold

fuurce: lCE,'Memory 1997'

Figure; Electrical Characteristics of an EPROM

The programming (write cycle) of an EPROM takes several hurdred milliseconds. Usually a byte-eight
bits-is addressed with each write cycle. The read time is comprable to that of fast ROMs and DRAMs
(i.e., several tens of nanoseconds). ln those applications wheregrograms are stored in EPROMs, the CPU
can run at normal speeds.

Field programmability is the EPROM's main advantage over th ROM. lt allows the user to buy mass-
produced devices and program each device for a specific need.Ehis characteristic also makes the EPROM
ideal for small-volume applications, as the devices are usually pgrammed in very small quantities. Also,
the systems supplier can program any last minute upgrades to te program just before shipment. EPROM
cells may be configured in the NAND structure shown prevbusly, or, more commonly, in the NOR
configuration shown in Figure 9-7.

WORD WOBD WORD

(atrr

(etrz

?
r'
Select Gate L I

\o
"-Jl
/

Floating Gate

Figure. NOR EPROM Configuntion

BROMs were created in the 1970s and have long been the cornerstone of the non-volatile memory
rarket. But the development of flash memory devices (see Section 10) will lead to a loss of EPROM

narketshare. EPROM uses a mature technology and design and is on the decline part of its lifecycle. For
fris reason there is not a lot of R&D expenditure made for EPROM devices. Figure 9-8 shows a cross
sction of a lMbit EPROM cell from two different manufacturers. The main difference between the
Focesses is the polysilicon gate. One manufacturer uses a polycide to improve the speed.

FROM Cell Size and Die Size

Ihe cell size of the EPROM is also relatively small. The EPROM requires one additional polysili-con layer,
md will usually have slightly lower yields due to the requirement for nearly perfect (and thin) gate
.o<ides.
 Figure; Typical lMbit EPROM Cells

These factors, plus the fact that an EPROM is encased in a ceramic pachge with a quartz window, make

the EPROM average selling price three to five times the price of the aask ROM. Figure 9-9 shows the
main feature sizes of lMbit EPROM analyzed by lCEOs laboratory.

Cdl Size Die ths Min. Gate

Manufacturer Density Oate Code

(*m2) t.rl Length (*m)

Atmel lMbit 9428 4.tlo 14.6 0.6

AMD lMbit 9634 5.52 1s-g 0.7

ST lMbir 95't4 3.60 't 1.5 0.5

ISSI lMbir 94/95 6.80 18.0 0.7

Source: lCE, 'Memory 1997'

Figure; EPROM Feature Sizes

OTPpne Time Programmable) EPROM

ln nsst applications, EPROMs are programmed orrtime and will never have to be erased. To reduce the
costbr these applications, EPROMs may be manubctured in opaque plastic packages since the standard
ceranic package of an EPROM is expensive. EPRGMs that are programmed one time for a specific use
and rannot be erased are referred to as One Time frogrammable (OTp) devices.

EEPPM

EEPPM (Electrically Erasable Programmable ROt$ offer users excellent capabilities and per-formance.
Only one external power supply is required sir.se the high voltage for program/erase is internally
genrated. Write and erase operations are perforned on a byte per byte basis.

The EPROM uses the same principle as the UV-EfROM. Electrons trapped in a floating gate will modify
the daracteristics of the cell, and so a logic "0" or !logic "L" will be stored.

The IEPROM is the memory device that implenents the fewest standards in cell design. The more
comr{on cell is composed of two transistors. Thestorage transistor has a floating gate (sim-ilar to the
EPRCIVI storage transistor) that will trap electrom. ln addition, there is an access tran-sistor, which is
requted for operations. Figure 9-10 shows the vohges applied on the memory cell to program/erase a
cell. Iote that an EPROM cell is erased when elechns are removed from the floating gate and that the
EEPffiM cell is erased when the electrons are trapped in the float-ing cell. To have products electrically
comptible, the logic path of both types of pro&rct will give a "L" for erase state and a "0" for a
prognmmed state. Figure 9-11 shows the electricaldifferences between EPROM and EEPROM cells.
ParallelEEPROM

There are two distinct EEPROM families: serial and parallel access. The serial access represents 90
percent of the overall EEPROM market, and parallel EEPROMs about 10 percent. Parallel devices are
available in higherdensities (>255Kbit), aregenerallyfaster, offerhigh endurance and reliability, and are
found mostly in the military market. They are pin compatible with EPROMs and flash memory devices.
Figure 9-12 shows feature sizes of three lMbit parallel EEPROM from different manufacturers, analyzed
by ICE's laboratory. Figures 9-13 to 9-15 show photographs and schematics of the respective cells. lt is
interesting to see the wide differences in these cells.

SerialEEPROM

Serial EEPROMs are less dense (typically from 255 bit to 256Kbit) and are slower than parallel devices.
They are much cheaper and used in more "commodity" applications.
c
L

2ovo

CG 0v

s S

Erase Program

CL

S
G

S(F V
=rase
PP

."-1il
-r4
Source: lCE,'Memory 1 997'

Figure ;. EEPROM Cell Program/Erase

EPROM programming: Hot electron

. High VPP Current

. High ISUB
. VPP must be an external supply
. No VBB generator

EEPROM programming: Tunneling

. VPP is generated by an internal pump.

bur@: lCE, "Memoty 1997' 17556

Figure;. Vpp EPROM Versus Vpp EEPROM

 Cell Size Die Size Min Gate
Man6cturer Density Date Code

(*m2) (.,n2) Length (*m)

Wi6ond lMbit 9432 7.8 22.6 0.9

Xi.[ lMbit 944t 21.0 51.0 1.3

HiEhi lMbir 9,1[E 22.s s1.0 0.6

Souce: loE"'Memory 1 997'

Figure ; lMbit Paralld EEPROM Feabe Sizes

ni
 Figure; Wtubond lMbit EEPROM Cell

Serial access EEPROMs feature low pin count.Typically they are packaged in an 8-pin package. As
illustrated in Figure 9-16, XicorOs 128Kbit serbl EEPROM uses the 8 pins in the following manner:

Y VCC and V55 for supply voltage

Y SCL (Serial Clock) to clockthe data

Y SDA (Serial Data) is a bi-directional pinused to transfer data into and out of the device

Y S0,Sl,52areselectinputsusedtoset&refirstthreebitsofthe8-bitslaveaddress

Y WP (Write Protection) controls Write Fotection features.

Serial EEPROMs use data transfer interface pmtocols for embedded control applications. These protocols
222
include the Microwave bus, the I C bus, theXl C (Extended I C) or the SPI (Serial Peripheral lnterface)
bus interfaces.

There continues to be an ongoing effort to rduce the size of serial EEPROMs. Microchip Technology, for
example, introduced a 128bit serial EEPROM h a five-lead SOT-23 package.
 }OLY 1

PNOGRAiN L1NE
--Jl

Figure. Xicor lMbit EEPROM Cell

 Silicon tlitride

Source: lCE, "Memory 1997

Figure. HitactdlMbit EEPROM Cell

Figue 9-17 shows feature sizes of three serial EEPIOMs from different manufacturers that were analyzed
by EE6s laboratory. Note that larger cell sizes acompany low-density EEPROM devices. When building
an EPROM chip that contains sense amplifiers, cotrollers, and other peripheral circuitry, cell size is not
as Ereat a factor at low (1Kbit, 2Kbit) densities. .*t larger den-sities, the size of the cell array is more
critkal. lt becomes a larger portion of the chip. Thgefore, greater consideration must be given to the size
of tle cell.
 H.V. Geneation
$art Cycle

Timing and

Control
v
cc

v
SS

Write Protect
SDA Start

Register and
Stop

Logic
Logic

Control

Logic

Slave Address

Register

EEPROU
+Comparator
 Figure. Xicorl23Kbit Serial EEPROM Functional Diagram

Cell Size Die Size Min cate

Manufacturer Density Date Code

.2.
t*r1 (mm ) Length (-m)

Microchip 16K 9540 60.5 6.0 2.O

Xicor 2K 9432 100.0 4.0 2.O

ST 1K 9618 286.0 2.6 1.2

So urce : I CE,'Mefr,o{y t 997'

Figure. EPROM Serial Configuration Feature Sizes

This size impact is illustrated in Figure using a lKbit serial EEPROM example from SGS-Thomson. The cell
array represents only 11 percent of thetotal surface of the chip.

Figures show additional EEPROM celhAs noted, there is no design standard forthis type of cell. ln laying
out the EEPROM cell, the designer mtst take into consideration the ele-ments of size, performance, and
process complexity.
 CIL AFIEAY

Pil\ 1

Figure. SGS-Thmrson lKbit Serial EEPROM

 -l
--ll

Qure; Microchip 16Kbit Serial EEPH)M Cell

Multi-Level Analog Storage EEPROM

The goal of multi-level cell (lvtlc) is to store more than one bit of information in a
single cell. Much work has already beeq done regarding MLC as applied to flash
memory devices. The typ-ical developmed for digital flash memories is to store four
different levels in the same cell, and thus d.ivide the number of cells by two (four data are
given by two bits : 00, 01, 10, and 11).

However, for several yea.rs now, lnformatbn Storage Devices (ISD), a San Jose based
company, has proposed multi-level analog storage EEPROMs for analog storage. ISD
presented a 480Kbit EEPROM at the 19% ISSCC conference. The multi-level storage
cell is able to store 256 different levels of charge between 0V and 2V. This means the
cell needs to have a 7.5mV resolution. The 256 different levels in one cell corresponds to
eight bits of information. A comparablc digital implementation requires 3.84Mbit
memory elements to store the same amoufit of information. The information stored will
not be 100 percent accurate but is good mough for audio applications, which allows
some errors.
Course Material Prepared by
Dr. S. MEENAKSHI SUNDARAM
HOD of Physics, Sri Paramakalyani College
Alwarkurichi - 627 412.

Manonmaniam Sundaranar University, Directorate of Distance & Continuing Education, Tirunelveli.