National Central University 111 Spring Fundamentals of Electronics II

PH Wang

Fundamentals of Electronics II
基礎電學2
2023 Spring
Section 22
Instructor: Assistant Professor Pei-Hsun Wang
王培勳 助理教授
Department of Optics and Photonics

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National Central University 111 Spring Fundamentals of Electronics II
PH Wang

Latch & Flip-Flops

• Combinational: Output is a function of the present inputs
only.
• Sequential : Output is function both the present and
the past sequence of inputs.
• Circuit “remembers” previous history
• → Latches : with no clock input (on clock level)
• → Flip Flop (F/F): with clock input (on clock edge)

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 National Central University 111 Spring Fundamentals of Electronics II
PH Wang

Gate Delay and Timing Diagrams (Review)

• Inverter (NOT)
X
X X’
t Delay may be very small
X’
but still exist.
t

dτ dτ Delay by NOT
• AND
X
X Z t
Y 1 μs delay
Y
Delay by circuit t
1 μs 1 μs
Z
t
dτ Delay by AND
dτ dτ
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National Central University 111 Spring Fundamentals of Electronics II
PH Wang

Timing in Feedback Networks

• One inverter with feedback (a switching circuit with
memory): Oscillation at output (Not stable)
X
X X’ t

• Two inverters
Stable

1 0 1 0 1 0

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National Central University 111 Spring Fundamentals of Electronics II
PH Wang

Set-Reset Latch (SR latch)

• Feedback into a NOR-gate circuit:

Q Q
P P
S 1 0 S 1 0
R Q
0 R 0 R
0 1
R
Q Q Q’
P P S
0 1 S 1 0
S
1 R 0 R
0 0
R Q
Q
P SR latch
S 0 1
0 R S Q’
0
5

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National Central University 111 Spring Fundamentals of Electronics II
PH Wang

Set-Reset Latch (SR latch)

• SR latch operation:
Time sequence

0 S t
R 0->1
Q
1->0
R R
t
S Q’
1->0
0->1 Q
t
0->1 1->0
R Q
Gate delay ε Gate delay ε
R
1->0
S Q’
0->1
0 6

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 National Central University 111 Spring Fundamentals of Electronics II
PH Wang

Set-Reset Latch (SR latch)

• R and S can not be 1 simultaneously.
• If R, S 1->0 simultaneously, Q=Q’=0->1 (not allowed) or
Q=1 first or Q’=1 first (undetermined)
• Q+=S+R’Q + S R Q Q (t+ε) RQ\S 0 1
0 0 0 0
1->0 R 0->1->0->1 00 0 1
Q 0 0 1 1
0 1 0 0
R 01 1 1
0->1->0->1 0 1 1 0
1->0 S Q’
1 0 0 1
11 0 X
1 0 1 1
1 1 0 - (input not allowed) 10 0 X
1 1 1 - (input not allowed)
7

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National Central University 111 Spring Fundamentals of Electronics II
PH Wang

Set-Reset Latch (SR latch)

• Characteristic equation: Q+=S+R’Q

RQ\S 0 1 S R Qn+1

00 0 1 0 0 Qn Qn: present state

Qn+1: next state

01 1 1 0 1 0

11 0 X 1 0 1

10 0 X 1 1 -

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National Central University 111 Spring Fundamentals of Electronics II
PH Wang

Set-Reset Latch (SR latch)

• Alternative form using NAND gates

1 S’ R’ Qn+1
S’ Q
0/1 Qn: present state
R 1 1 Qn
Qn+1: next state
R’ Q’
1 1/0 1 0 0

S’ S 0 1 1
Q
SR latch
0 0 -
R’ R Q’

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National Central University 111 Spring Fundamentals of Electronics II
PH Wang

Set-Reset Latch (SR latch)

• Debouncing with an SR latch

Fundamentals of Logic Design, 7th

Edition, Roth/Kinney
10

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National Central University 111 Spring Fundamentals of Electronics II
PH Wang

Gated D Latch
• Transparent latch: G = 1, Q = D
• Q+=G’Q+GD Time sequence
D G t
S
Q
D t
G SR latch
R Q’ Q t

D Q
L Q\GD 00 01 11 10
0 0 0 1 0
G Q’
1 1 1 1 0

11

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National Central University 111 Spring Fundamentals of Electronics II
PH Wang

Unreliable Gated D Latch

• D=xQ’+x’Q
Q\x 0 1
x D Q
0 0 1
1 1 0 L

Clock G Q’
• If x=1 and Clock is high:
• D=Q’ => Q=Q’ (unreliable)

12

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