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CV Akansha 1

This document contains the resume of Akansha Lal, an MTech student pursuing VLSI System Design specialization from Delhi Technological University. She is currently interning at Intel Corporation as a Client SoC Validation Engineer where she has executed automated and manual test cases for eSPI IP. Her academic qualifications include a BTech in Electronics and Communication Engineering. Her technical skills include design and simulation tools like Virtuoso, LTSPICE, and Xilinx Vivado. Some of her academic projects include designing a sense amplifier, MIPS32 processor and various types of D flip-flops. She has also participated in extracurricular activities like cultural events and sports.

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shweta bhagat
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95 views1 page

CV Akansha 1

This document contains the resume of Akansha Lal, an MTech student pursuing VLSI System Design specialization from Delhi Technological University. She is currently interning at Intel Corporation as a Client SoC Validation Engineer where she has executed automated and manual test cases for eSPI IP. Her academic qualifications include a BTech in Electronics and Communication Engineering. Her technical skills include design and simulation tools like Virtuoso, LTSPICE, and Xilinx Vivado. Some of her academic projects include designing a sense amplifier, MIPS32 processor and various types of D flip-flops. She has also participated in extracurricular activities like cultural events and sports.

Uploaded by

shweta bhagat
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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AKANSHA LAL

+91-8873991388 • in/akansha-lal • [email protected]

OBJECTIVE
MTech Electronics Engineering student with VLSI System Design Specialization, looking forward to work in pragmatic way in an organization
where I can contribute and enhance my skills to meet company goals and objectives with full integrity and zest.

INTERNSHIP
INTEL Corporation (Client SoC Validation Engineer) Aug 2022 – Ongoing
• Executed Automated Testlines for eSPI in Intel Gen 13.
• Manual execution of Testcases for eSPI in Intel Gen 12.
• Contributed for creating Test Case Scenario for eSPI IP.

EDUCATION
Master of Technology in VLSI Design and Embedded Systems 8.54 Aug 2021 - Pursuing
Delhi Technological University, Delhi,
Bachelor of Technology in Electronics and Communication Engineering 8.5 Aug 2016 - May 2020
UCET, Hazaribag,Jharkhand,
Intermediate Degree 86.8% Mar 2014 - May 2015
Surendranath Centenary School,Jharkhand,
High School Degree 95% Mar 2012 - May 2013
Surendranath Centenary School,Jharkhand,

TECHNICAL SKILLS & RELEVANT COURSES


Design & Simulation Software: Virtuoso, LTSPICE, Xilinx Vivado.
Tools: Oscilloscope, LA
Courses: Digital IC Design, Low Power Digital CMOS Design, Digital Hardware Design, Computer Architecture.
Programming & Hardware Languages: C, Verilog, Python
OS: Windows, Linux

PROFESSIONAL COURSES
ASIC Design Flow
Physical Design Flow
Static Timing Analysis

ACADEMIC PROJECTS
Design of Sense Amplifier Mar 2022 - May 2022
• Differential input D latch SA
• Increases the speed of SRAM
Design of MIPS32 processor using Verilog Nov 2021 – Dec 2021
• Design of the Data Path, consisting of Registers, Multiplexes, Bus, Adders, Counters and other functional blocks.
• Design of the Control Path, consisting of Finite State Machine and control signals to the data path in proper order.

Design of Static and Dynamic D Flip Flop Feb 2021 - Mar 2021
• Transmission Gate based Static Master-Slave D-Flip flop and Dynamic Transmission Gate Edge Triggered D-Flip flop.
• C2MOS D-Flip flop and True Single Phase Clocked (TSPC) D-Flip flop.

Design of Serial Peripheral Interface (SPI) Mar 2022 - May 2022


• Goal of the project is to understand the functioning and working of SPI protocol.
• Some design changes were also made to increase the efficiency.

EXTRA CURRICULAR ACTIVITIES AND ACHIEVEMENTS


• Winner of Badminton tournament in inter hostel competition
• Organized cultural fest in B.Tech
• Active participant of NSS
• Volunteered international seminar at VBU
DECLARATION
I hereby declare that the details furnished above are true and correct to the best of my knowledge and belief.

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