Module 3 : Processor Organization and Architecture

CPU Architecture- Central Processing Unit

Central Processing Unit (CPU) consists of the following features −

•CPU is considered as the brain of the computer.

•CPU performs all types of data processing operations.

•It stores data, intermediate results, and instructions (program).

•It controls the operation of all parts of the computer.

CPU consists of 3 major units, which are:

1.Memory or Storage Unit
2.Control Unit
3.ALU(Arithmetic Logic Unit)

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1. Memory or Storage Unit
• This unit can store instructions, data, and intermediate results.
• This unit supplies information to other units of the computer when needed.
• It is also known as internal storage unit or the main memory or the primary storage or Random Access Memory
(RAM).
• Primary memory and secondary memory are two types of memories in the computer.
• Functions of the memory unit are −
• It stores all the data and the instructions required for processing.
• It stores intermediate results of processing.
• It stores the final results of processing before these results are released to an output device.
• All inputs and outputs are transmitted through the main memory.

2. Control Unit
This unit controls the operations of all parts of the computer
Functions of this unit are −
• It is responsible for controlling the transfer of data and instructions among other units of a computer.
• It manages and coordinates all the units of the computer.
• It communicates with Input/Output devices for transfer of data or results from storage.
• It does not process or store data.

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3. ALU (Arithmetic Logic Unit)
This unit consists of two subsections namely,
•Arithmetic Section
•Logic Section

Arithmetic Section
Function of arithmetic section
• To perform arithmetic operations like addition, subtraction, multiplication, and division.

Logic Section
Function of logic section is to perform logic operations such as comparing, selecting, matching, and merging of data.

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CPU Architecture
• execute the program as well as controls the functioning of other system component

• Directly or indirectly control I/O operation

• Also support the interrupt facility by which external devices can request the CPU services.

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Major Function of CPU through Flowchart

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CPU Organization

Register
Accumulator(AC) – Used to store the result of
operation performed in ALU
Program Counter(PC)- 1. Address of next instruction
2. provides the track of program to
the CPU
Instruction Register (IR) – Current Instruction for
execution
Instruction Decoder(ID) - decode the instruction which
fetched by IR
Address Register (AR) - Store address for temporary
purpose
Data Register (DR) - Store data for temporary
purpose

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 Register Organization
What is Register?

• Registers are the smaller and the fastest accessible memory units in the central processing unit (CPU).
• The registers used by the central unit are also called as processor Registers Description
registers.
• A register can hold the instruction, address location, or operands. MAR (Memory Address Register) This register holds the memory
location of the data that needs
to be accessed.

MDR (Memory Data Register) This register holds the data that
• Register organization is the arrangement of the registers in is being transferred to or from
memory.
the processor.
• The processor designers decide the organization of the registers in AC (Accumulator) This register holds the
a processor. intermediate arithmetic and
• Different processors may have different register organization. logic results.

PC (Program Counter) This register contains the

address of the next instruction to
be executed.

CIR (Current Instruction This register contains the current

Register) instruction during processing.
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General purpose registers in 8086 microprocessor

• The general-purpose registers are used to store temporary data in the time of different
operations in microprocessor.

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Register Function

AX This is the accumulator. It is 16-bit registers, but it is divided into two 8-bit registers. These registers are AH
and AL. AX generally used for arithmetic or logical instructions, but it is not mandatory in 8086.
BX BX is another register pair consisting of BH and BL. This register is used to store the offset values.

CX CX is generally used as control register. It has two parts CH and CL. For different looping and counting
purposes these are used.
DX DX is data register. The two parts are DH and DL. This register can be used in Multiplication, Input/output
addressing etc.
SP This is the stack pointer. The stack pointer points the top most element of the stack.

BP BP is another 16-bit register. This is base pointer register. This register is primary used in accessing the
parameters passed by the stack. It’s offset address relatives to stack segment.
SI This is Source Index register. This is used to point the source in some string related operations. Its offset is
relative to data segment.
DI This is destination index register. This is used to point destination in some string related operations. Its offset
is relative to extra segment.

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Instruction formats

Computer Consists Three Basics Components:

1. CPU
2. Memory
3. I/O Devices

Fig: Basic Components of the Computer and the CPU

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1. Zero Address Instructions –
• A stack-based computer does not use the address field in the instruction.
• To evaluate an expression first it is converted to reverse Polish Notation i.e. Postfix Notation.

PUSH A TOP = A

PUSH B TOP = B

ADD TOP = A+B

PUSH C TOP = C

PUSH D TOP = D

ADD TOP = C+D

Expression: X = (A+B)*(C+D)
MUL TOP = (C+D)*(A+B)
Postfixed : X = AB+CD+*
TOP means top of stack POP X M[X] = TOP
M[X] is any memory location
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2 .One Address Instructions –

• This uses an implied ACCUMULATOR register for data manipulation.

• One operand is in the accumulator and the other is in the register or memory location.
• Implied means that the CPU already knows that one operand is in the accumulator so
there is no need to specify it.

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2 .One Address Instructions –

LOAD A AC = M[A]

Expression: X = (A+B)*(C+D) ADD B AC = AC + M[B]

AC is accumulator
M[] is any memory location STORE T M[T] = AC
M[T] is temporary location
LOAD C AC = M[C]

ADD D AC = AC + M[D]

MUL T AC = AC * M[T]

STORE X M[X] = AC

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3.Two Address Instructions –

• This is common in commercial computers.

• Here two addresses can be specified in the instruction.
• Unlike earlier in one address instruction, the result was stored in the
accumulator, here the result can be stored at different locations
rather than just accumulators, but require more number of bit to
represent address.

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3.Two Address Instructions –

Here destination address can also contain operand.

Expression: X = (A+B)*(C+D) R1, R2 are registers M[] is any memory location

MOV R1, A R1 = M[A]

ADD R1, B R1 = R1 + M[B]

MOV R2, C R2 = C

ADD R2, D R2 = R2 + D

MUL R1, R2 R1 = R1 * R2

MOV X, R1 M[X] = R1

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4.Three Address Instructions –
• This has three address field to specify a register or a memory location.
• Program created are much short in size but number of bits per instruction increase.
• These instructions make creation of program much easier but it does not mean that program will run
much faster because now instruction only contain more information but each micro operation (changing
content of register, loading address in address bus etc.) will be performed in one cycle only.

ADD R1, A, B R1 = M[A] + M[B]

Expression: X = (A+B)*(C+D)
R1, R2 are registers ADD R2, C, D R2 = M[C] + M[D]
M[] is any memory location
MUL X, R1, R2 M[X] = R1 * R2

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Page 18
Basic instruction cycle

• A program that exists inside a computer's memory unit consists of a series of

instructions.
• The processor executes these instructions through a cycle for each instruction.
• In a basic computer, each instruction cycle consists of the following phases:
• Instruction fetch: fetch instruction from memory
• Decode the instruction: what operation to be performed.
• Read the effective address from memory Execute the instruction

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Basic instruction cycle
• The instruction cycle is a representation of the states that the computer or the microprocessor performs
when executing an instruction.
In the basic computer, each instruction cycle includes the following procedures −
•It can fetch instruction from memory.
•It is used to decode the instruction.
•It can read the effective address from memory if the instruction has an indirect address.
•It can execute the instruction.

Figure: Complete Basic instruction cycle Page 20

The processing involved in the execution of a single instruction is termed as Instruction Cycle. This processing is done
in two steps i.e. fetch and execute. To execute an instruction the processor first reads an instruction from the memory
which is called fetching and then the fetched instruction is executed.

If we discuss the basic structure it includes the following two cycles:

Fetch cycle: In this cycle, the processor reads the instruction that is to be executed from the memory.
Execute cycle: In this cycle, the processor interprets the opcode of the fetched instruction and performs the
operations accordingly.
The figure below shows you the processing of the basic instruction cycle. In the beginning, to start the execution of a
program, the processor runs the fetch cycle and fetches the first instruction from the memory. The execution cycle
interprets the operation and performs the operations specified in the instruction accordingly.

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Registers Involved In Each Instruction Cycle:

• Memory address registers(MAR) : It is connected to System Bus address lines. It specifies the
address of a read or write operation in memory.
• Memory Buffer Register(MBR) : It is connected to the data lines of the system bus. : It is
connected to the system bus Data Lines. It holds the memory value to be stored, or the last value
read from the memory.
• Program Counter(PC) : Holds the address of the next instruction to be fetched.
• Instruction Register(IR) : Holds the last instruction fetched.

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Fetch cycle

• The address of the next instruction to execute is in the Program Counter(PC) at the beginning of
the fetch cycle.
• Step 1: The address in the program counter is transferred to the Memory Address Register(MAR),
as this is the only register that is connected to the system bus address lines.
• Step 2: The address in MAR is put on the address bus, now a Read order is provided by the control
unit on the control bus, and the result appears on the data bus and is then copied into the
memory buffer register. Program counter is incremented by one, to get ready for the next
instruction. These two acts can be carried out concurrently to save time.
• Step 3: The content of the MBR is moved to the instruction register(IR).
• Instruction fetch cycle consist of four micro operation:
Microoperations take place:
T1: MAR<-PC
T2: MBR<-memory
PC<-PC + stepsize or length of instruction
T3: IR<- MBR

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Decode instruction cycle
• The next move is to fetch source operands once an instruction is fetched. Indirect
addressing (it can be obtained by any addressing mode, here it is done by indirect
addressing) is obtained by Source Operand.
• You don't need to fetch register-based operands.
• If the opcode is executed, it will require a similar process to store the result in main
memory.
• Microoperations take place:
T1: MAR<-IR(address)
T2: MBR<- Memory
T3: IR(address)<- (MBR(Address))

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Decode instruction cycle

• Step 1: The instruction address field is passed to the MAR. This is used to fetch
the operand 's address.
• Step 2: The address field of the IR is updated from the MBR.
• Step 3: The IR is now in the state. Now IR is ready for the execute cycle.

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Execute instruction Cycle
• The initial three cycles (Fetch, Indirect, and Interrupt) are predictable and quick.
• Each requires simple , small, and fixed micro-operation sequences. The same micro-
operation is repeated every time around in each event.
• Execute instruction cycle is different from them. Like, there is N different series of
micro-operations that can occur for a computer with different N opcodes.
• Example
ADD R , X
T1: MAR<- (IR(address))
T2: MBR<-Memory
T3: R<-(R) + (MBR)

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Execute instruction Cycle

• Step 1: The address portion of IR is loaded into the MAR.

• Step 2: The address field of the IR is updated from the MBR, so the reference memory location is
read.
• Step 3: Now, the contents of R and MBR are added by the ALU

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Basic instruction cycle

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• Instruction Address Calculation − The address of the next instruction is computed.
• Instruction Fetch − The instruction is read from its specific memory location to the
processor.
• Instruction Operation Decoding − The instruction is interpreted and the type of
operation to be implemented and the operand(s) to be used are decided.
• Operand Address Calculation − The address of the operand is evaluated if it has a
reference to an operand in memory or is applicable through the Input/Output.
• Operand Fetch − The operand is read from the memory or the I/O.
• Data Operation − The actual operation that the instruction contains is executed.
• Store Operands − It can store the result acquired in the memory or transfer it to
the I/O.

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Overview of 80x86 families
• 8086 Microprocessor is an enhanced version of 8085 Microprocessor that was designed by Intel in
1976.
• It is a 16-bit Microprocessor having 20 address lines and 16 data lines that provides up to 1MB
storage.
• It consists of powerful instruction set, which provides operations like multiplication and division
easily.
• It supports two modes of operation, i.e. Maximum mode and Minimum mode.
• Maximum mode is suitable for system having multiple processors and Minimum mode is suitable for
system having a single processor.

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Comparison between 8085 & 8086 Microprocessor

• Size − 8085 is 8-bit microprocessor, whereas 8086 is 16-bit microprocessor.

• Address Bus − 8085 has 16-bit address bus while 8086 has 20-bit address bus.
• Memory − 8085 can access up to 64Kb, whereas 8086 can access up to 1 Mb of memory.
• Instruction − 8085 doesn’t have an instruction queue, whereas 8086 has an instruction queue.
• Pipelining − 8085 doesn’t support a pipelined architecture while 8086 supports a pipelined
architecture.
• I/O − 8085 can address 2^8 = 256 I/O's, whereas 8086 can access 2^16 = 65,536 I/O's.
• Cost − The cost of 8085 is low whereas that of 8086 is high.

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Architecture of 8086

•Data Segment Register

(DS) – It is used to point
to the base address of
the data register.

•Code Segment Register

(CS) – It is used to point
to the base address of
the code register.

•Extra Segment Register

(ES) – It holds the base
address of the extra
memory segment.

•Stack Segment Register

(SS) – It holds the base
address of the stack
memory segment.
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Microprocessor - 8086 Functional Units

• 8086 Microprocessor is divided into two functional units, i.e., EU (Execution Unit)
and BIU (Bus Interface Unit).
• EU (Execution Unit)
• Execution unit gives instructions to BIU stating from where to fetch the data and then decode
and execute those instructions.
• Its function is to control operations on data using the instruction decoder & ALU.
• EU has no direct connection with system buses as shown in the above figure, it performs
operations over data through BIU.
• ALU
• It handles all arithmetic and logical operations, like +, −, ×, /, OR, AND, NOT operations.

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Microprocessor - 8086 Functional Units
• Flag Register
• It is a 16-bit register that behaves like a flip-flop, i.e. it changes its status according to the result stored in the
accumulator. It has 9 flags and they are divided into 2 groups − Conditional Flags and Control Flags.
• Conditional Flags
• It represents the result of the last arithmetic or logical instruction executed. Following is the list of
conditional flags −
• Carry flag − This flag indicates an overflow condition for arithmetic operations.
• Auxiliary flag − When an operation is performed at ALU, it results in a carry/barrow from lower nibble (i.e.
D0 – D3) to upper nibble (i.e. D4 – D7), then this flag is set, i.e. carry given by D3 bit to D4 is AF flag. The
processor uses this flag to perform binary to BCD conversion.
• Parity flag − This flag is used to indicate the parity of the result, i.e. when the lower order 8-bits of the result
contains even number of 1’s, then the Parity Flag is set. For odd number of 1’s, the Parity Flag is reset.
• Zero flag − This flag is set to 1 when the result of arithmetic or logical operation is zero else it is set to 0.
• Sign flag − This flag holds the sign of the result, i.e. when the result of the operation is negative, then the
sign flag is set to 1 else set to 0.
• Overflow flag − This flag represents the result when the system capacity is exceeded.

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 Microprocessor - 8086 Functional Units

• Control Flags
• Control flags controls the operations of the execution unit. Following is the list
of control flags −
• Trap flag − It is used for single step control and allows the user to execute one
instruction at a time for debugging. If it is set, then the program can be run in
a single step mode.
• Interrupt flag − It is an interrupt enable/disable flag, i.e. used to
allow/prohibit the interruption of a program. It is set to 1 for interrupt
enabled condition and set to 0 for interrupt disabled condition.
• Direction flag − It is used in string operation. As the name suggests when it is
set then string bytes are accessed from the higher memory address to the
lower memory address and vice-a-versa.

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Microprocessor - 8086 Functional Units
• General purpose register
• There are 8 general purpose registers, i.e., AH, AL, BH, BL, CH, CL, DH, and DL.
These registers can be used individually to store 8-bit data and can be used in pairs
to store 16bit data.
• The valid register pairs are AH and AL, BH and BL, CH and CL, and DH and DL. It is
referred to the AX, BX, CX, and DX respectively.
• AX register − It is also known as accumulator register. It is used to store operands for arithmetic
operations.
• BX register − It is used as a base register. It is used to store the starting base address of the
memory area within the data segment.
• CX register − It is referred to as counter. It is used in loop instruction to store the loop counter.
• DX register − This register is used to hold I/O port address for I/O instruction.

• Stack pointer register

• It is a 16-bit register, which holds the address from the start of the segment to the
memory location, where a word was most recently stored on the stack.
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Microprocessor - 8086 Functional Units
• BIU (Bus Interface Unit)
• BIU takes care of all data and addresses transfers on the buses for the EU like sending addresses,
fetching instructions from the memory, reading data from the ports and the memory as well as
writing data to the ports and the memory.
• EU has no direction connection with System Buses so this is possible with the BIU. EU and BIU are
connected with the Internal Bus.
• It has the following functional parts −
• Instruction queue − BIU contains the instruction queue.
• BIU gets upto 6 bytes of next instructions and stores them in the instruction queue.
• When EU executes instructions and is ready for its next instruction, then it simply reads the instruction
from this instruction queue resulting in increased execution speed.

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Microprocessor - 8086 Functional Units
• Fetching the next instruction while the current instruction executes is called pipelining.
• Segment register − BIU has 4 segment buses, i.e. CS, DS, SS& ES. It holds the addresses of instructions
and data in memory, which are used by the processor to access memory locations. It also contains 1
pointer register IP, which holds the address of the next instruction to executed by the EU.
• CS − It stands for Code Segment. It is used for addressing a memory location in the code segment of the
memory, where the executable program is stored.
• DS − It stands for Data Segment. It consists of data used by the program andis accessed in the data segment
by an offset address or the content of other register that holds the offset address.
• SS − It stands for Stack Segment. It handles memory to store data and addresses during execution.
• ES − It stands for Extra Segment. ES is additional data segment, which is used by the string to hold the extra
destination data.
• Instruction pointer − It is a 16-bit register used to hold the address of the next instruction to be
executed

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Addressing modes
• The Different ways in which source operand is denoted in an instruction is known as addressing mode.
• There are eight addressing modes in 8086 MPU.
• Immediate Addressing Mode
• Register Addressing Mode
• Direct Addressing Mode
• Register Indirect Addressing Mode
• Based Addressing Mode
• Indexed Addressing Mode
• Based-Index Addressing Mode
• Based-Index with displacement addressing mode

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1. Immediate Addressing

• The addressing mode in which the data operand is a part of the instruction itself is known
as immediate addressing mode.

MOV CX, 4929 H,

MOV AL, FFH
ADD AX, 2387 H,

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2. Register Addressing
• It means that the register is the source of an operand for an instruction.
• The name of register specified in instructions.

MOV CX, AX;

copies the contents of the 16-bit AX register into; the 16-bit CX register

ADD BX, AX

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3. Direct Addressing

• The addressing mode in which the effective address of the memory location is written directly in
the instruction.

MOV AL, [0300H]

MOV AX, [1592H]

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4. Register Indirect Addressing

• This addressing mode allows data to be addressed at any memory location through an offset address held in
any of the following registers: BP, BX, DI & SI.

MOV AX, [BX];

Suppose the register BX contains 4895H, then the contents;
4895H are moved to AX

ADD CX, {BX}

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5. Based Addressing

• In this addressing mode, the offset address of the operand is given by the sum of contents of the
BX/BP registers and 8-bit/16-bit displacement.

MOV DX, [BX+04],

ADD CL, [BX+08]

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6. Indexed Addressing

• In this addressing mode, the operands offset address is found by

adding the contents of SI or DI register and 8-bit/16-bit
displacements.

MOV BX, [SI+16],

ADD AL, [DI+16]

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7. Based Index Addressing

• In this addressing mode, the offset address of the operand is computed by summing the base
register to the contents of an Index register.

ADD CX, [AX+SI], MOV AX, [AX+DI]

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8. Based Index with Displacement Addressing

• In this addressing mode, the operands offset is computed by adding the base register contents.
An Index registers contents and 8 or 16-bit displacement.

MOV AX, [BX+DI+08], ADD CX, [BX+SI+16]

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Functions of the Control Unit –

• It coordinates the sequence of data movements into, out of, and between a processor’s many
sub-units.
• It interprets instructions.
• It controls data flow inside the processor.
• It receives external instructions or commands to which it converts to sequence of control signals.
• It controls many execution units(i.e. ALU, data buffers and registers) contained within a CPU.
• It also handles multiple tasks, such as fetching, decoding, execution handling and storing results.

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Hardwired Control Unit –
• In the Hardwired control unit, the control signals that are important for instruction execution control are
generated by specially designed hardware logical circuits, in which we can not modify the signal generation
method without physical change of the circuit structure.
• The operation code of an instruction contains the basic data for control signal generation. In the instruction
decoder, the operation code is decoded.
• The instruction decoder constitutes a set of many decoders that decode different fields of the instruction opcode.
• As a result, few output lines going out from the instruction decoder obtains active signal values.
• These output lines are connected to the inputs of the matrix that generates control signals for executive units of
the computer.
• This matrix implements logical combinations of the decoded signals from the instruction opcode with the outputs
from the matrix that generates signals representing consecutive control unit states and with signals coming from
the outside of the processor, e.g. interrupt signals.
• The matrices are built in a similar way as a programmable logic arrays.
• Fixed logic circuits that correspond directly to the Boolean expressions are used to generate the control signals.
• Hardwired control is faster than micro-programmed control.
• A controller that uses this approach can operate at high speed.
• RISC architecture is based on hardwired control unit
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Hardwired Control Unit Design

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Advantages and Disadvantages of Hardwired Control Unit

Advantages of Hardwired Control Unit

1. Faster
2. Performance is high

DisAdvantages of Hardwired Control Unit

1. Control signal required by CPU more complex
2. Modifications very difficult

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Designing of Hardwired Control Unit

Designing of Hardwired Control Unit

The following are some of the ways for constructing hardwired control logic that have been proposed:

State Table Method − The standard algorithmic approach to designing the Notes controller utilising the classical
state table method is used in this method.

Delay Element Method – For creating the sequence of control signals, this method relies on the usage of timed
delay elements.

Sequence Counter Method − It is the most practical way to design a somewhat complex controller.

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State Table Method

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State Table Method
•Here the behavior of control unit is represented in the form of a table, which is known as the state table.
•Here, each row represents the T-states and the columns represent the instructions.
•Every intersection of the specific column to each row indicates which control signal will be produced in the
corresponding T- state of an instruction.
•Here the hardware circuitry is designed for each column(i.e. for a specific instruction) for producing control signals
in different T-states.

Advantage –
•It is the simplest method.
•This method is mainly used for small instruction set processors(i.e. in RISC processors).

•Drawback –
•In modern processors ,there is a very large number of instruction set. Therefore, the circuit becomes complicated to
design, difficult to debug, and if we make any modifications to the state table then the large parts of the circuit need
to be changed.
•Therefore ,this is not widely used for these kinds of processors.

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Delay Element Method

Delay Element Method - Control signals follow a proper sequence.

There is a specific time delay between two groups of control signals. D
flip flops are controlled by a standard clock signal to ensure
synchronisation. Sequence Counter Method - It uses counter for timing
purposes.

Advantage –
This method has a logical approach ,therefore it helps to
reduce the circuit complexity.
For the common control signals which need to be generated in
every instruction, for them only one circuitry can be designed .

Drawback –
As the number of instructions increases , the number of D FF
for generating delay is increased, so overall circuit complexity
and cost increases.

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Sequence Counter Method

•This is the most popular and most commonly used method for
generating delays between every consecutive control signal.
It’s main advantage is that it uses the logical approach of
flowchart and doesn’t use the unnecessary number of D FF.

Advantages :
Less number of flip-flops are used.
Disadvantages of hardwired control unit :
In modern processors ,there is a very large number of
instruction set. Therefore, the circuit becomes complicated to
design, difficult to debug, and if we make any modifications
then a large part of the circuit needs to be changed. Therefore,
it is suited for RISC processors.

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Microprogrammed control unit

• The fundamental difference between these unit structures and the structure of the hardwired
control unit is the existence of the control store that is used for storing words containing encoded
control signals mandatory for instruction execution.
• In microprogrammed control units, subsequent instruction words are fetched into the instruction
register in a normal way.
• However, the operation code of each instruction is not directly decoded to enable immediate
control signal generation but it comprises the initial address of a microprogram contained in the
control store.
• The control signals associated with operations are stored in special memory units inaccessible by
the programmer as Control Words.
• Control signals are generated by a program are similar to machine language programs.
• Micro-programmed control unit is slower in speed because of the time it takes to fetch
microinstructions from the control memory.

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Soft wired (Microprogrammed) Control Unit

A control unit whose binary control values are saved as words in memory is called a microprogrammed control
unit.

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Advantages and Disadvantages of Microprogrammed Control
Unit

Advantages of Microprogrammed Control Unit

It is simpler to debug and change.

It can make the design of the control unit much simpler. Hence, it is inexpensive
It can orderly and systematic design process.
It is used to control functions implemented in software and not hardware.
It is more flexible.
It is used to complex function is carried out easily.

Disadvantages of Microprogrammed Control Unit

It is slower than a hardwired control unit.

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Difference between Hardwired control and Microprogrammed

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CISC and RISC

• Reduced Instruction Set Architecture (RISC) –

• The main idea behind is to make hardware simpler by using an instruction set
composed of a few basic steps for loading, evaluating, and storing operations
just like a load command will load data, store command will store the data.
• Complex Instruction Set Architecture (CISC) –
• The main idea is that a single instruction will do all loading, evaluating, and
storing operations just like a multiplication command will do stuff like loading
data, evaluating, and storing it, hence it’s complex.

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CISC and RISC

• Both approaches try to increase the CPU performance

• RISC: Reduce the cycles per instruction at the cost of the number of
instructions per program.

• CISC: The CISC approach attempts to minimize the number of

instructions per program but at the cost of increase in number of
cycles per instruction.

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Complex Instruction Set Computer
• It stands for Complex Instruction Set Computer.
• These processors offer the users, hundreds of instructions of variable sizes.
• These instructions interact with memory by using complex addressing modes.
• CISC processors reduce the program size and hence lesser number of memory cycles are required
to execute the programs.
• This increases the overall speed of execution.
• Examples: Intel architecture, AMD

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Characteristic of CISC –

• Complex instruction, hence complex instruction decoding.

• Instructions are larger than one-word size.
• Instruction may take more than a single clock cycle to get executed.
• Less number of general-purpose registers
• Complex Addressing Modes.
• More Data types.

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Reduced Instruction Set Computer

• It stands for Reduced Instruction Set Computer.

• It is a type of microprocessor architecture that uses a small set of instructions of uniform length.
• These are simple instructions which are generally executed in one clock cycle.
• RISC chips are relatively simple to design and inexpensive.
• Examples: POWER PC etc.

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Characteristic of RISC –
• Simpler instruction, hence simple instruction decoding.
• Instruction comes undersize of one word.
• Instruction takes a single clock cycle to get executed.
• More general-purpose registers.
• Simple Addressing Modes.
• Less Data types.
• Pipeline can be achieved.

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CISC vs RISC
RISC CISC

Focus on software Focus on hardware

Uses only Hardwired control unit Uses both hardwired and micro programmed control unit

Transistors are used for storing complex

Transistors are used for more registers
Instructions

Fixed sized instructions Variable sized instructions

Can perform only Register to Register Arithmetic operations Can perform REG to REG or REG to MEM or MEM to MEM

Requires more number of registers Requires less number of registers

Code size is large Code size is small

An instruction execute in a single clock cycle Instruction takes more than one clock cycle

An instruction fit in one word Instructions are larger than the size of one word

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Important Questions

1. Write short note on Instruction Formats.

2. Explain single address, two address and three address instructions
3. Draw CPU organization and explain.
4. Explain Instruction cycle with interrupt execution.
5. What is meant by Fetch cycle, decode instruction cycle, Execute instruction cycle .
6. Explain Control Unit.
7. Explain Hardwired Control Unit with design methods.
8. Explain Soft wired (Micro programmed) Control Unit
9. Write note on CISC and RISC.
10. Compare CISC and RISC.
11. Explain addressing modes in details.
12. Compare Hardwired control and Microprogrammed

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