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6 - B - II - Hamming Encoder

This document describes an experiment on implementing Hamming code for error detection and correction using VHDL and a Nexys 4 DDR FPGA board. Hamming code is a block code that can detect up to two simultaneous bit errors and correct single-bit errors by inserting redundant bits. The VHDL code for a Hamming encoder is provided, along with the simulation results showing it functioning properly. Implementation on the FPGA board is also verified using LED outputs. Questions are provided at the end to test the understanding of Hamming code concepts.

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Aman Goyal
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24 views4 pages

6 - B - II - Hamming Encoder

This document describes an experiment on implementing Hamming code for error detection and correction using VHDL and a Nexys 4 DDR FPGA board. Hamming code is a block code that can detect up to two simultaneous bit errors and correct single-bit errors by inserting redundant bits. The VHDL code for a Hamming encoder is provided, along with the simulation results showing it functioning properly. Implementation on the FPGA board is also verified using LED outputs. Questions are provided at the end to test the understanding of Hamming code concepts.

Uploaded by

Aman Goyal
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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COMPUTER NETWORK LAB MANUAL

SKIT/ECE/VI SEM/CN LAB


EXPERIMENT No.-6(D)
AIM:

Software and hardware realization of the Hamming code Error control schemes.

SOFTWARE/HARDWARE USED:

Xilinx ISE, NEXYS4 DDR

THEORY:

Hamming code is a set of error-correction codes that can be used to detect and correct the
errors that can occur when the data is moved or stored from the sender to the receiver.
Hamming code is a block code that is capable of detecting up to two simultaneous bit errors
and correcting single-bit errors. In this coding method, the source encodes the message by
inserting redundant bits within the message. These redundant bits are extra bits that are
generated and inserted at specific positions in the message itself to enable error detection and
correction. When the destination receives this message, it performs recalculations to detect
errors and find the bit position that has error.

VHDL CODE FOR HAMMING CODING FOR ERROR CONTROL SCHEME-


library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity hammi is

Port ( d : in STD_LOGIC_VECTOR (7 downto 1);

m : out STD_LOGIC_VECTOR (11 downto 1));

end hammi;

architecture Behavioral of hammi is

signal p:STD_LOGIC_vector(11 downto 1);

begin

p(11 downto 9)<=d(7 downto 5);

p(7 downto 5)<=d(4 downto 2);

p(3)<=d(1);

p(1)<=p(3) xor p(5) xor p(7) xor p(9) xor p(11);


COMPUTER NETWORK LAB MANUAL

SKIT/ECE/VI SEM/CN LAB


p(2)<= p(3) xor p(6) xor p(7) xor p(10) xor p(11);

p(4)<= p(5) xor p(6) xor p(7);

p(8)<= p(9) xor p(10) xor p(11);

m<=p;

end Behavioral;

.ucf file

NET "d[7]" IOSTANDARD = LVCMOS33;

NET "d[6]" IOSTANDARD = LVCMOS33;

NET "d[5]" IOSTANDARD = LVCMOS33;

NET "d[4]" IOSTANDARD = LVCMOS33;

NET "d[3]" IOSTANDARD = LVCMOS33;

NET "d[2]" IOSTANDARD = LVCMOS33;

NET "d[1]" IOSTANDARD = LVCMOS33;

NET "m[11]" IOSTANDARD = LVCMOS33;

NET "m[10]" IOSTANDARD = LVCMOS33;

NET "m[9]" IOSTANDARD = LVCMOS33;

NET "m[8]" IOSTANDARD = LVCMOS33;

NET "m[7]" IOSTANDARD = LVCMOS33;

NET "m[6]" IOSTANDARD = LVCMOS33;

NET "m[5]" IOSTANDARD = LVCMOS33;

NET "m[4]" IOSTANDARD = LVCMOS33;

NET "m[3]" IOSTANDARD = LVCMOS33;

NET "m[2]" IOSTANDARD = LVCMOS33;

NET "m[1]" IOSTANDARD = LVCMOS33;


COMPUTER NETWORK LAB MANUAL

SKIT/ECE/VI SEM/CN LAB


# PlanAhead Generated physical constraints

NET "d[7]" LOC = U18;

NET "d[6]" LOC = T18;

NET "d[5]" LOC = R17;

NET "d[4]" LOC = R15;

NET "d[3]" LOC = M13;

NET "d[2]" LOC = L16;

NET "d[1]" LOC = J15;

NET "m[11]" LOC = U14;

NET "m[10]" LOC = T15;

NET "m[9]" LOC = V16;

NET "m[8]" LOC = U16;

NET "m[7]" LOC = U17;

NET "m[6]" LOC = V17;

NET "m[5]" LOC = R18;

NET "m[4]" LOC = N14;

NET "m[3]" LOC = J13;

NET "m[2]" LOC = K15;

NET "m[1]" LOC = H17;

OUTPUT:
COMPUTER NETWORK LAB MANUAL

SKIT/ECE/VI SEM/CN LAB

Fig.1: Simulation result of hamming encoder


CONCLUSION:

Hamming code is a block code that is capable of detecting up to two simultaneous bit errors
and correcting single-bit errors. For this Software and Hardware realisation is done through
Xilinx ISE and NEXYS 4DDR. VHDL code Simulation results are shown in the form of
waveforms. Values are forced through user. Functionality of Hamming Code is verified
through simulation result. Simulation result is verified on hardware (NEXYS 4DDR kit),
where output show in form of LED after applying particular input on button on NEXYS
4DDR.

DISCUSSION:

Q.1 What is the most common hamming codes version of?


Q.2 For hamming distance dmin and number of errors D, the condition for receiving invalid
codeword.
Q.3 What is the role of redundant bit in hamming code?
Q.4 What is the role of even and odd parity in hamming code.

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