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Analog to digital
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0% found this document useful (0 votes)
43 views12 pagesAD7578
Analog to digital
Uploaded by
aminulah jamaludinCopyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF or read online on Scribd
/ 12
ANALOG
) DEVICES
cmos
12-Bit Successive Approximation ADC
AD7578
FEATURES
12.Bit Successive Approximation ADC
No Missed Codes Over Full Temperature Range
Low Total Unadjusted Error + 1LSB max
High Impedance Analog Input
‘Autozero Cycle for Low Offset Voltage
Low Power, 75mW typ
‘Small Size: 0.3", 24-Pin Package
Conversion Time of 100us
GENERAL DESCRIPTION
‘The AD7578 is « medium speed, monolithic 12-bit CMOS A/D
converter which uses the successive approximation technique to
provide a conversion time of 100us. An auto-zero cycle occurs
at the start of each conversion resulting in very low system
offset voltages, typically less than 100V. The device is designed
{or easy microprocessor interfacing using standard control signals;
GS (devoded device address), RD (READ) and WR (WRITE).
Conversion results are available in two bytes, SLSBs and 4MSBs,
over an 8-bit three state output bus. Bither byte can be read
first. Two converter busy flags are available to facilitate polling
of the converter’s status
‘The analog input voltage range is OV to +5V when using a
reference voltage of + SV.
REV. B
Information furnishes by Analog Devices is belived to be accurate and
feliablo. However, no responsibilty is assumed by Analog Davices forks
Use, nor for any Infringement of patonts or other ghte of third portes
‘ich may result from it use. No leense Is granteu by Implication oF
‘otherwise undar any patant or patent rights of Anslog Devices.
FUNCTIONAL BLOCK DIAGRAM,
ox@lge |e
g
® “4
PRODUCT HIGHLIGHTS
1. The AD7S78 is a complete 12-bit A/D converter in « 24-pin
package requiring only a few passive components and a voltage
reference.
2, Autozero cycle realizes very low offset voltages, typically
100nV.
3. Standard microprocessor control signals to allow easy inter-
{facing to most popular 8- and 16-bit microprocessors.
4. Monolithic construction for increased reliability and small
0.3", 2&pin package
One Technology Way. P.O, Box $106, Norwood, MA 02062-9106, U.S.A
Tel: 617/529-4700 Fax: 617/326-9703 AD7578 SPECIFICATION (Wop = +15V, Veg = +5V, Ves = —SV, Veer = +5.0V fey = 140KHz external,
a all specifications Tyyy 10 Tyae unless otherwise noted.)
Parameter KVersion' | BVersion' | TVersion' | Units Conditions/Comments: »
‘ACCURACY )
elton R R 2 Biss
‘Total Unadjusted Error® a1 +1 41 LSBmax
Diteential Nowlin a a UsBmax | Nominingcadesguarantesd
Pleo Gain on? fia | Sia | eve | Esmee | Pauseae tcp ppc
Offset Error* +14 +04 24 ‘LSB max, Offset Error TCis typically Ippm/C_
ANALOGINFOT
"Ansiog npr Range ow+s owes owes |v Vaer= +5.0¥
Cane np Capactance 3 3 : Pp
Tans lapat eae aren AIN;0.0 #5
se » 0 0 Am
Teat0Tom to» 100 too Amen
REFERENCE INPOT
Vasr(ForSpectedPerormnce) | +5 + + v 25%
Vir Range r40+6 | stors | s4wse |v Degraded ranferacarcy
Vhartnpat Reference Curcet te te to mamax_| Vega 50V
POWERSUPPLY REJECTION
Vo0On sin {cis | cs | uspup | Yoon +1428V00 +1879 c
Vss= 5 90
VssOnly s |= |= | uspyp | Vo~—a75vm-s28v
Voo=+18V
TosrenPoTS
RD (Pin 16), CS (Pin 17), WR (Pin 18)
BYSL in19)
Virlapt Lom Vliage sos | sos | sos | vmx | Voom ¥5v-29%
Vulnpat igh Voltage rea fae faze | Vin
Tova Curent
oe 4“ a a wamax | vi=010Vec
Tin © Tyas +10 +10 +10 wAmax C )
Cyn: Input Capacitance® 10 10 10 pF max Y
con rina
Vis lnpat Low Voge os | 208 | 208 | vmx | Voce ¥5v-25%
Vi apa igh Votage By | |p = oR
Itinpu: Low Current fo | Zio] Fo | amex
Ts tapa igh Caren ais [ais | Sas | ke
Tosicourruts
‘DBO-DB7 (Pins 8-15), BUSY (Pin 20)*
ou, Ourpu Low Voge my lee fey = {it
Yon OutputHighVotase wo | S40 | ko | vin :
Floating State Leakage Current oO
(Pins 8-15) zl +1 +1 vA max, ba
PoatngStteOuiparCaraciane | 15. 5 fa pres
CONVERSION TIME™
‘Wit Exel eck 100 10 1 ee
Wihtnerm Gack, ty= +25 | sateo | sono | sono | usminmax | ting recommended cock componens
shown n Fiat
FOWERREQUIREMENTS
Veo 45 sis | 4s | vwcom | = setorspeeieapetrmance
vs *S i 3 NOM | 25% forepciedperormance
ve ss 3 s Nom | 29 frspciedperormance
be i 13 is mama | Typkaly tnd ie poe SV
i a5 13 7 mama | typi Sma witVore —3¥
Ie to too too agp | Vows VaorVan
to 10 10 mame
Power Dissipation 75 15 75 mW typ WR-RD-= CS= BUSY = Logic HIGH
—
"TemperatureRangeas follows: K,B Versions, ~40°Ct0 + 85°C
TWerskan,~ SC 19+ 125
*ncludes Full Seale Error, Offer Error and Relative Accurcy
Guaranteed by design, not production ested,
‘gyn for BUSY (pin 2) is Omiiamp.
2 Conversion ime includes autoero yee ine
“Power supply curentismeasued when AD7S7S sinactiveie., WR =RB ~CS ~ BUSY = Logic HIGH,
Sposfcaionssubjectto change without notice. (
AD7578
TIMING SPECIFICATIONS! yg = +151, ¥52= +5... —9t Ve +90
Limitat +25°C ] Limitat Tans Ts | Limit at Tiny Fae
Parameter | (AllGrades) | (K&BGrades)” | (Trade) Units Conditions/Comments
u ° 0 ° msmin | CS:0WR Setup Time
cant? 200 240 280 nsmin | WRPulse Width (Imernal Clock Operation)
EXT? io 0 10 usmin | WR Pulse Width External lock Operation)
& ° ° ° nsmin | Ct WRHold Time
4 130 160 200 asp
200 250 300 asmax | WRto BUSY Propagation Delay
% ° ° ° asmin | BUSYwCSSeupTime
° ° ° nsmin | CStoRDSeupTime
© 200 240 280 asmin | RDPulse Width
% ° ° o asmin | CStoRD Hold Time
& so 50 50 nsmin | BYSLtoRDSctupTime
Wo, ° ° 0 nsmin | BYSLtoRDHold Time
a? 130 180 200 astyp _
200 240 280 asmax | RDto Valid Data(Bus Access Time)
ut 20 20 20 nsmin | RDtoThree State Output
130 150 150 nsmax | (BusRelinguish Time)
NOTES:
"Timing Speciscationsare guaranteed by design, not production ested Alinputcontl gaa ate
specified witht, =~ 20a 10% to90% af + SV) and timed frm volage veo + 1 6V. Data timed from
Mow Vou
2 When asingan external clock source the WR pulsewidth must be extended tprovie the minimum
gutozeocycl tine of 1h, See "External lock Operation”
‘sinned wth thelead euitsof Figure sand define asthe time required for an output tocrss0,8V or 24.
“tiisdefined asthe time equre forthe data linea change SV when loaded with tects Figute 4
Speiiations subject to change without nose.
eomin
Figure 1. Start Cycle Timing
iE
2. High-Z t0 Vow b. High-Z to Vou
Figure 3. Load Circuits for Access Time Test (ts)
REV. B
Figure 2. Read Cycle Timing
pple
y
Sone
a Vow to High-Z D. Vox t0 High-Z
Figure 4. Load Circuits for Output Float Delay Test (t,2) AD7578
ABSOLUTE MAXIMUM RATINGS*
(Ty = +25°Cunles otherwise sated)
Vpp to DGND . =03V, +17V
Vos to DGND . . « +0.3V, -7V.
AGND to DGND =0.3V, Vier +0.3V.
Voc to DGND . . =03V, Vop +03V
Varr to AGND . =0.3V, Vp +0.3V
AIN to AGND : -0.3V, Vpp +0.3V
Digital Input Voltage to DGND
(Pins 16-19, 21) . -03V, Vpp +0.3V
Digital Ourput Voltage to DGND
‘Pins 8-15, 20) :
. -03V, Vpp +03
Operating Temperature Range
‘Commercial (K Version) = 40°C to +85°C
Industrial (B Version) . 40°C 10 485°C
Extended (T Version) . -55C w +125
CAUTION
ESD (electrostatic discharge) sensitive device, Electrostatic charges as high as 4000 V, which readily
accumulate on the human body and on test equipment, can discharge without detection. Although
these devices feature proprietary ESD protection circuitry, permanent damage may still occur on.
these devices if they are subjected to high energy electrostatic discharges. Therefore, proper
precautions are recommended to avoid any performance degradation of loss of functionality
Storage Temperature 65°C 10 + 150°C
Junction Temperature +150°C
DIP Package, Power Dissipation 875mW
6a Thermal Impedance g 1oscw
Lead Temperature, Soldering (10sec) = + 260°C
Cerdip Package, Power Dissipation . = 1000mW
ja Thermal Impedance orcw
Lead Temperature, Soldering (10secs) + 300°C
*sureiser above those Usted under “Absolute Maximum Ratings” may
‘cause permanent damage to the device, This is a sues rating only and
functional operation of the device at these or any other conditions above
those indicated in the operitional sections of this specifation is not
limplids Exponure to abeoite maximum rating conditions for extended
etiodemay aflet device eabily
Te Cc
ll ae
ORDERING GUIDE
Total
Unadjusted
Temperature | Error Package
Model! | Range Tyuy ~Tmax| Option?
ADISTERN | °C +8C [=ILSB [N24
‘AD7S78BQ | -40°Cro +85°C | =11SB | Q24
AD7S78TQ | -S5°Ct0-+125°C| +ILSB_ | Q24
NOTES
"To order MIL-STD-483 Class B procesed parts, add 8838 to part
umber. Contet leases ofc for
2No= Pastic DIP; Q'= Cee.
ralitary data sheet
DIPPIN CONFIGURATION
cx [7] 6 [v=
ow GI lve
ve [zl we
vee Le] Falax
sore CE] gyray EEE
wore LE] ty fel vse
ve | Ea] we
ow Le] Es
owe [a Fw
0 fon
ons [| ioe
REV. B
oO 0
AD7578
PIN FUNCTION DESCRIPTION
1
2
3
4
5
6
7
sas
19
20
a
2
2
a
REV. B
MNEMONIC
Az
AIN
NIC
Vrer
AGND
DGND
Voc
NIC
ss.
Von
DESCRIPTION
‘Autozero Capacitor Input. Connect other side of capacitor to AGND.
Analog Input
NoConnect pin
Voltage reference input. The AD7578 is specified with Vasr= +5.0V.
Analog Ground
Digital Ground
Logic Supply. For Voc= + SV digital inputs and outputs are TTL compatible.
‘Three state data outputs. They become active when CS & RD are brought low. Individual pin function
is dependent upon the Byte Select (BYSL) input.
DATA BUS OUTPUT, CS & RD = LOW
BYSL = HIGH | BYSL = LOW
Ping | BUSY" DB7
Pind | Low? DBS
Pinto | LOW? DBs
Pint | Low? DB
Pini2 | DBII(MSB) DB3
Pini3 | DBIO pz
Pinl4 | DB9 DBI
Pints | DBS DBO(LSB)
"BUSY Pin8)is converte status fag andis HIGH durig aconverson.
Pin] utputalogic LOW when BYSL is HIGH.
DBII-DBOarethe12-bi¢conversion results, DBLL isthe MSB.
READ input. This active LOW signa, in combination with CS, isused to enable the output datathree-
state drivers
CHIP SELECT Input, Decoded device address, active LOW. Used in combination with ther RD or
WR for control.
WRITE Input. This active LOW signa, in combination with CS, is used to start a new conversion
When the AD7S78 internal clock is used, the minimum WR pulse width is 2 (INT). When an
external clock source is used, the minimum WR pulse width must be extended to inchde the
futozero cycle time. For extemal clock operation, the minimum WR pulse width is 2 (EXT).
BYTE SELECT. This control input determines whether the high or low byte of data is placed on
the ovtput data bus during a data READ operation (CS & RD LOW). See description of pins 8-
15.
BUSY indicates converter status. BUSY is LOW during conversion, otherwise BUSY is held at a
logic HIGH.
CLOCK Input for internallexternal clock operation.
Internal : Connect Re: x and Cer x1/Cer.x2 timing components. Sec Figure 6 and Figure 7.
External : Connect external 74HC compatible clock source as shown in Figure8.
Noconnectpin.
Negativesupply, ~SV.
Positivesupply, + 15V. AD7578
Operating Information
OPERATIONAL DIAGRAM
‘An operational diagram for the AD7S78 is shown in Figure 5.
The only passive components required are the autozero capacitor
Caz and timing components Rex Ccuxs & Cen for the
internal clock oscillator. If the AD7578 is to be used with an
external clock source, then only Cyz is required. Individual pin
functions are described in detail on the previous page.
Figure 5, AD7578 Operational Diagram
INTERNAL CLOCK OPERATION
‘The clock circuitry for internal clock operation is shown in
Figure 6 and the AD7578 operating waveforms are shown in
Figure 7.
Voow
Figure 6. Circuitry Required for Internal Clock Operation
-wee TTT
sea espa eee
Figure 7. Operating Waveforms ~ Internal Clock
Between conversions (BUSY = HIGH) the AD7S78 is in the
autozero cycle. When WR goes LOW (with CS LOW) to start a
[eae
‘new conversion, the autozero capacitor Cay, charges to AIN —
Vos where Vos is the input offset voltage of the autozero
‘comparator,
A minimum time of 10s is required for this autezero cycle. In
applications using the internal clock oscillator, itis not necessary
for WR to remain LOW for this period of time since itis auto-
‘matielly provided by the AD7S78, This is achieved by switching
a constant current load across the clock capacitors, Cer and
Cotas causing the voltage at the CLK input pin to slowly
decay from Voc. This occurs after WR returns HIGH. The
Schmit trigger circuit monitoring the voltage on the CLK input
ends the autozero cycle when its LOW input trigger level is
reached. At this point, the constant current load across the
‘lock capacitors is removed allowing them to charge towards
Voc via Ror. When the voltage at the CLK input reaches the
HIGH trigger level, the constant current load is replaced across
Cer and Coxx2- The MSB decision is made when the LOW
trigger level is reached. This cycle repeats itself 12 times to
provide 12 clock pulses for the conversion cycle. The circuit
arrangement of Figure 6 provides the relatively slow autozero
cycle time at the beginning of a conversion while allowing the
clock oscillator to speed up once the autozero cycle is complete.
EXTERNAL CLOCK OPERATION
For external clock operation Rexx, Cex: and Cx are discarded,
and the CLK input is driven from a 74HC compatible clock
source. The mark/space rato of the external clock can vary
from 40/60 to 60/40. The AD7378 WR pulse width must now
’be extended to provide the minimum autozero cycle time of
10s since this is no longer provided automatically by the AD7S78.
Referring to the operating waveforms of Figure 9, the minimum
WR pulse width when using an external clock source ist: (EXT).
‘The CS input must now remain valid for the extended WR
pulse width. One approach to stretching the available uP signals
is shown in the general 8-bit uP interface circuit of Figure 20.
tis not necessary to synchronize the external clock source with
the extended WR pulse width, the MSB decision being made on
the second falling edge of the clock input after the WR input
returns HIGH.
gy ax
- = son
Figure 8. External Clock Operation
- Foon
ana arate
Figure 9. Operating Waveforms ~ External Clock
REV. B
oy
oO J
AD7578
READING DATA
‘The 12-bit conversion data plus a converter status flag are available
over an 8-bit wide data bus. Data is transferred from the AD7S78
in right-justified format (ie., the LSB is the most right-hand bit
in a 16-bit word). Two READ operations are required, the Byte
Select (BYSL) input determining which byte-8 least significant
bits or 4 most significant bits plus status flag-is to be read first
Since the AD7578 uses the successive approximation register
(SAR) to hold conversion results (refer to Functional Diggram),
it is necessary to wait until a conversion is finished before reading
valid 12-bit data. Executing a READ instruction (HIGH or
LOW byte) to the AD7578 while a conversion is in progress
‘will place the existing contents of the SAR onto the data bus.
‘Three different approaches can ensure valid 12-bit data is available
for reading
1, Insert a software delay greater than the ADC conversion time
‘between the conversion start instruction and the data read
instructions.
2. At user-defined intervals after a conversion stact instruction,
poll the internal converter status flag, BUSY. This signal is
available on pin 8 during a HIGH byte READ instruction
and is the most left-hand bitin a 16-bit right-justified word,
‘The status bit can be shifted into a microprocessor’s ac-
cumulator-carry positon for testing (BUSY is HIGH during
3. Use the externally available BUSY (pin 20) signal as an interrupt
to the microprocessor. This signal is LOW during a conversion,
and returns HIGH at conversion end.
Executing a WRITE instruction to the AD7578 while a conversion
is in progress will restart the conversion.
REV. B
COMPONENT SELECTION
1. Autozero Capacitor, Caz
‘The autozero capacitor must be a low leakage, low dielectric
absorption type such as polystyrene, polypropylene or teflon
‘To minimize noise connect the outside fol of Cxz to AGND
(pin 5), the analog system ground. Caz should be 2,200pF.
2. Clock Oscillator Components, Rerxs Coux: and Coix2
Clock pulses are generated by the action of series connected
capacitors, Cozxi and Coxe charging through an external
resistor Rcix and discharging through an internal switch.
‘Nominal conversion time versus temperature for the ecom-
mended Rezx and Couxi/Ccx2 combination is shown in
Figure 10. Due to process variations, the actual operating
frequency for this Rex and Cox xy/Gct xe combination can
vary from device to device by up t0 20%, For this reason,
Analog Devices recommends using an external lock in the
following situations:
4. Applications requiring a conversion time which is within
20% of 100js, the maximum conversion time for specified
accuracy (a 140kHz clock frequency gives a 1001s con-
version time).
i. Applications which cannot accommodate conversion time
dilferences which may occur duc to unit clock frequency
variations ot temperature variations.
It is possible to replace the fixed Rex resistor with a
50k potentiometer in series with a fixed 22K0) resistor to
allow individval adjustment of internal clock frequency.
Reducing the value of Rex from 56k to 47k decreases
the conversion time by typically 12ps.
5
3
‘CONVERSION MME — 8
Figure 10. Typical Conversion Time vs. Temperature Using
Internal Clock AD7578
APPLYING THE AD7578
‘The high input impedance of the analog input, AIN, allows
simple analog interfacing. Zero to +5V signal sources can be
‘connected directly to the analog input without additional buffering
for source impedances up to Sk0 (see Figure 11). The inpuv/ourput
transfer characteristic and transition points for this input signal
range are shown in Figure 12 and Table I respectively. The
‘designed transition points on the AD7578 transfer characteristic
‘occur on integer multiples of ILSB. The output code is Natural
Binary with ILSB = (F.S,) (1/4096) = (5/4096) = 1.22mV,
abe
Figure 11. Unipolar 0 to +5V Operation
=f rt
Figure 12. Ideal Inpuv/Output Transfer Characteristic for
Unipolar Circuit of Figure 11
Table |. Transition Points for Unipolar to + 5V Operation
‘Analog Input, Volts Digital Output
0.00122 (000 001
0.00244 000 010
2.49878 ou
2.50000, 100 000
2.50122 100 001
4.99756 T in uo
4.99878 mm
Signal ranges other than 0 to +5V are easily accommodated by
using resistor divider newworks to produce 0 to +5V signal
ranges at the AD7578 input pins. Figure 13 shows a divider
network to allow an input signal range of 0 to +10V. The input
resistors must be selected to match within 0.01% and should be
the same type and from the same manufacturer so that their
temperature coefficients match. Note that since the source im-
pedance has not been included in the resistor divider ratio, it
‘ust now be as low as possible. For Figure 13 with a source
{impedance of 0.50 the maximum error across the network is
approximately 0.SLSB. The LSB size is (F.S.\14096) =
(204096)V = 2.44mV.
v
Figure 13. Unipolar 0 t0 + 10V Operation
Bipolar signal ranges of ~SV to +5V are accommodated by
referencing the resistor divider network t0 Var as shown in
Figure 14. With the resistor values shown, the signal source
‘must be capable of sinking 0.5mA. The inpuvoutput transfer
characteristic and transition points for this = SV signal range are
shown in Figure 15 and Table II respectively. ‘The output code
is Offset Binary with an LSB size of (F.S.)(1/4096) = (104096)
2.44mV.
‘With an analog input (Vs) of ~1.22mV, the input offset voltage
of Al should be adjusted until the ADC output flickers between
O11 1111 1111 and 1000 0000 0000. Alternatively the ~1/2LSB
signal offset can be included in the signal conditioning
electronics
Figure 14. Bipolar ~5V to +5V Operation
7 —
ao
Figure 15. Ideal Input/Output Transfer Characteristic for
Bipolar Circuit of Figure 14
Tablell. Transition Points for Bipolar — 5V to +5V Operation
‘Analog Input, Volts Digital Output
~4.99878 (000 001
1 -4.99634 000 010 4
0.00122 100 000
+0,00122 100 001
+4.99389 1 110
+4,99634 mi
REV. B ¢
AD7578
Applications
Power Supply Decoupling: All power supplies to the AD578,
should be bypassed with ether 10uF tantulum or electrolytic
capacitors. To ensure good high frequency performance, each
capacitor should be bypassed with an 0.01uF dise ceramic
capacitor. All capacitors should be placed as close as possible to
the AD7578.
Reference Circuit: Figure 16 shows how to configure an
ADS84LH to produce a reference voltage of 5.00V. R2 provides
a typical adjustment range of +75mV. The ADSS4LH will
contribute less than ILSB of gain error over the commercial
temperature range
(sare
Figure 16. ADSBALH as Reference Generator
Transient currents flow at the Var input during a conversion,
To avoid dynamic errors place a 0.01yF dise ceramic capacitor
from the Vr pin to AGND.
Microprocessor Interfacing
MICROPROCESSOR INTERFACING
When the AD7S7S is used with its own internal clock oscillator,
microprocessor interfacing is straightforward and requires at
most afew external gates (se Figures 17 through 19, 21 and
22), When the AD7S78 is used with an external clock source,
additional circuitry is required wo extend the pP contol signals
(see Figure 20,
'MC6800, MC6809 and 6502 MICROPROCESSORS
A typical interface to the AD7578 with any of the above micro-
processors is shown in Figure 17. The decoder can be enabled
high using VMA in 6800 systems or enabled low by NOR’ing
‘bo and 2 in 6502 systems or by NOR’ing E and Q in 6809
systems. Address line A2 of the 6800 has been tied to BYSL of
the AD7578. Assuming the AD7S78 is assigned a memory block
starting at address 8000H, a write instruction to any address in
this block will start a conversion. To read the conversion results,
REV. B
Proper Layout: Layout fora printed circuit board should ensure
‘that digital and analog signal lines are separated as much as
possible. In particular, care should be taken not to run any
digital track alongside an analog signal track ot close to the
autozero capacitor. The analog inputs, the reference input and
the autozero input should be screened by AGND.
[A single point analog ground separate from the logic sytem
ground should be established at pin 5 (AGND) of as close as
possible to the AD7S78. This single point analog ground should
be connected tothe digital system ground, to which pn 6 (DGND)
is connected, at one point only and a close to the ADTS78 as
possible. The autozero capacitor, bypass capacitors for the refer-
ence input and the analog supplies, AIN common and eny input
signal screening should be returned tothe analog ground point.
‘Low impedance analog and digital power supply common returns
ae essential to low noise operation of the ADC and the foil
width for these tracks should be as wide as posible.
Noise: Input signal leads to AIN and signal return leads from
AGND (pin 5) should be Kept as short as posible to minimize
input noise coupling. In applications where this is not possible,
8 shiclded cable berween source and ADC is recommended.
‘Aso since any potential difference in grounds between the signal
souree and ADC appears as an error voltage in series with the
input signal, attention should be paid to reducing the ground
circuit impedances as much as posible
In applications where the AD7S78 data outputs are connected to
2 continuously busy (and noisy) microprocessor bus it is possible
to get LSB errors in conversion resuls. These errors are due to
feedthrough from the microprocessor bus to the autozero com-
parator. The problem exists only for ceramie package versions
of the AD7S78.
‘Stopping bus activity during a conversion eliminates this problem,
Alternatively the AD7578 can be isolated from the microprocessor
bus by means of three-state buffers.
it is necessary only to bring control inputs CS and RD low. The
[BYSL input (tied to A2 of the uP) determines whether the data
hhigh or low bytes placed onto the 8-bit data bus. A read instruction
toaddress 8000H will result in the low byte of data being transferred
to the uP (BYSL = Low). Similarly a read instruction to any
address having A2 HIGH and within the assigned memory
block, e.g., 8004H, transfers the high byte of data to the nP.
The converter status flag BUSY can be polled at intervals to
check whether the present conversion has finished and valid
12-bit data is available. This is accomplished by the following
instructions on the 6800:
LDA A $8004 Load Flag from AD7578
ASL A ‘Shift Flag into Carry
BCC FETCH —BranchtoDataFetch
Subroutine if BUSY is LOW AD7578
MOVE. W Do som
starts a conversion. When the conversion is complete the pP ))
aotuites the result by reading frm the ADTS78, Le, “
MOVEP. W $000(A2), DO
‘This instruction plaes the conversion data in the DO register of
the uP. Address register A2 should contain an odd-order adres
thaving Al high) forthe AD7S78,e-, SCO.
‘SSNS Sra oe BERRA l|-pe+
Figure 17, AD7578 - MC6800, 6809, 6502 interface om F~
‘085A, 280 MICROPROCESSORS
‘Apia interface to eter ofthese microprocessors is showa in
‘Figure 18, Not shown in the figure is the 8-bit latch required to
demultiplex the 8085A common address/data bus. This interface
‘uses slightly different low-level address decoding than the previous
Inteace, Address line AO ofthe pP has ben ed to BYSL of
the ADYS7 This allows the Let data move instrecions on
buh the 8OSSA and the Z80 tobe used when reading conversion
‘als, Aatnig the AD7S7S is oan sogned a memeey
‘lock stating at adress S000H, write instruction to any address
inthis Mock will sara conversion, The I2-bit conversion
results can be read (low byte first then high byte) by a single PRICROPROCESSOR INTEREACE 50 20
as tena chock o
Figure 20 shows te ional uit geerly required to
‘On the 80854. interface an 8-bit wP to the AD7578 operating from an external
LHLD $000 tlock source: During writs operation, the 74121 monosable
a : (ones) triggered to atch the low ttl onthe CS input
eee into the 7477, a 4-bit bistable latch. The monostable timing
‘On the 280 ‘components (not shown in Figure 20) should be chosen to provide
LD BC, (2000 tn euput pulse width corresponding tot (EXT), the minimum
tunzerooletime.Toavoid ty poabiy of sprius igering,
the moncoable sould be enable by aval memory aren
signal. During a data read eyee, the 7477 atch is transparent «= (_)
tod data ig eed normally. Not thatthe uP write and read
yee times we unafeted bythe interface uit,
alle
