VHDL Data Types

Advanced Digital Electronics

Lecture 2
 Outlines
 Pre-defined data types
 User-defined data types
 Subtypes
 Arrays
 Port Array
 Records
 Signed and Unsigned Data Types
 Data Conversion
 Examples
Introduction
In order to write VHDL code efficiently, it is essential to
know what data types are allowed, and how to specify and
use them. In this lecture, all fundamental data types are
described, with special emphasis on those that are
synthesizable.
VHDL is a strongly typed language, which means that
an object must have a data type and only the defined values
and operations can be applied to the object.
Pre-defined data types
VHDL contains a series of pre-defined data types, specified
through the IEEE 1076 and IEEE 1164 standards. More
specifically, such data type definitions can be found
in the following packages / libraries:
 Package standard of library std: Defines BIT, BOOLEAN,
INTEGER, and REAL data types.
 Package std_logic_1164 of library ieee: Defines STD_LOGIC
and STD_ULOGIC data types.
 Package std_logic_arith of library ieee: Defines SIGNED and
UNSIGNED data types, plus several data conversion
functions
 Packages std_logic_signed and std_logic_unsigned of library
ieee: Contain functions that allow operations with
STD_LOGIC_VECTOR data if the data SIGNED or UNSIGNED.
Pre-defined data types
 BIT (and BIT_VECTOR): 2-level logic (‘0’, ‘1’). Examples:
Pre-defined data types
 STD_LOGIC (and STD_LOGIC_VECTOR): 8-valued logic system
introduced in the IEEE 1164 standard.
 Pre-defined data types
 BOOLEAN: True, False.
 INTEGER:32-bit integers (from -2,147,483,647 to +2,147,483,647).
 NATURAL: Non-negative integers (from 0 to +2,147,483,647).
 REAL: Real numbers ranging from -1.0E38 to +1.0E38. Not
synthesizable.
 Physical literals: Used to inform physical quantities, like time,
voltage, etc. Useful in simulations. Not synthesizable.
 Character literals: Single ASCII character or a string of such
characters. Not synthesizable.
 SIGNED and UNSIGNED: data types defined in the std_logic_arith
package of the ieee library. They have the appearance of
STD_LOGIC_VECTOR, but accept arithmetic operations, which are
typical of INTEGER data types (SIGNED and UNSIGNED).
Pre-defined data types
Pre-defined data types
User-defined data types
VHDL also allows the user to define his/her own data
types. Two categories of user defined data types are shown
below: integer and enumerated.
 User-defined integer types:
User-defined data types
 User-defined enumerated types:
User-defined data types
The encoding of enumerated types is done
sequentially and automatically (unless specified otherwise
by a user-defined attribute.
For example, for the type color above, two bits are
necessary (there are four states), being ‘‘00’’ assigned to the
first state (red), ‘‘01’’ to the second (green), ‘‘10’’ to the next
(blue), and finally ‘‘11’’ to the last state (white).
Subtypes
A SUBTYPE is a TYPE with a constraint. The main reason
for using a subtype rather than specifying a new type is that,
though operations between data of different types are not
allowed, they are allowed between a subtype and its
corresponding base type. Examples:
Subtypes
Example:
Legal and illegal operations between types and subtypes.
Arrays
Arrays are collections of objects of the same type. They
can be one-dimensional (1D), two-dimensional (2D), or one-
dimensional-by-one-dimensional (1Dx1D). They can also be of
higher dimensions, but then they are generally not
synthesizable.

the pre-defined VHDL data types include only the

scalar (single bit) and vector (one-dimensional array of bits)
categories..
Arrays
The predefined synthesizable types in each of these
categories are the following:

There are no pre-defined 2D or 1Dx1D arrays, which,

when necessary, must be first defined by the user using type,
then the new signal, variable, or constant can be declared
using that data type.

To make use of the new array type:

Example: 1Dx1D Array
If we want to build an array containing four vectors, each of
size eight bits. This is then an 1Dx1D array. Let us call each
vector by row, and the complete array by matrix.
Additionally, say that we want the leftmost bit of each vector
to be its MSB (most significant bit), and that we want the top
row to be row 0. Then the array implementation would be
the following (notice that a signal, called x, of type matrix,
was declared as an example):

Another way of constructing the 1Dx1D array:

Example: : 2D array
The array below is truly two-dimensional. Notice that
its construction is not based on vectors, but rather entirely on
scalars.

Array initialization Example :

... :="0001"; -- for 1D array
... :=('0','0','0','1') -- for 1D array
... :=(('0','1','1','1'), ('1','1','1','0')); -- for 1Dx1D or 2D array
Example: : Legal and illegal array assignments
The assignments in this example are based on the following
type definitions and signal declarations:
Example: : Legal and illegal array assignments
Example: : Legal and illegal array assignments
 Port Array
Sometimes we might need to specify the ports as arrays
of vectors. Since TYPE declarations are not allowed in an ENTITY,
we must use a PACKAGE, which will then be visible to the whole
design (thus including the ENTITY). An example is shown below.
 Port Array
Another option for the previous PACKAGE shown below, where a
CONSTANT declaration is included:
Records
Records are similar to arrays, with the only difference that
they contain objects of different types.
Example:
Signed and Unsigned Data Types
These types are defined in the std_logic_arith package
of the ieee library. Their syntax is illustrated in the examples
below:

Their syntax is similar to that of STD_LOGIC_VECTOR,

not like that of an INTEGER, as one might have expected.
An UNSIGNED value is a number never lower than zero. For
example, ‘‘0101’’ represents the decimal 5, while ‘‘1101’’
signifies 13.
Signed and Unsigned Data Types
If type SIGNED is used instead, the value can be
positive or negative (in two’s complement format). Therefore,
‘‘0101’’ would represent the decimal 5, while ‘‘1101’’ would
mean -3. To use SIGNED or UNSIGNED data types, the
std_logic_arith package, of the ieee library, must be declared.
Despite their syntax, SIGNED and UNSIGNED data
types are intended mainly for arithmetic operations, that is,
contrary to STD_LOGIC_VECTOR, they accept arithmetic
operations. On the other hand, logical operations are not
allowed. With respect to relational (comparison) operations,
there are no restrictions.
Signed and Unsigned Data Types
Legal and illegal operations with signed/unsigned data types:
Signed and Unsigned Data Types
Legal and illegal operations with std_logic_vector:
Signed and Unsigned Data Types
There is a simple way of allowing data of type
STD_LOGIC_VECTOR to participate directly in arithmetic
operations, using two packages, std_logic_signed and
std_logic_unsigned.
Example: Arithmetic operations with std_logic_vector.
Data Conversion
VHDL does not allow direct operations (arithmetic,
logical, etc.) between data of different types. Therefore, it is
often necessary to convert data from one type to another. This
can be done in basically two ways: or we write a piece of VHDL
code for that, or we invoke a FUNCTION from a pre-defined
PACKAGE which is capable of doing it for us.
If the data are closely related (that is, both operands
have the same base type, despite being declared as belonging
to two different type classes), then the std_logic_1164 of the
ieee library provides straightforward conversion functions. An
example is shown in the next slide.
Data Conversion
Legal and illegal operations with subsets.
Data Conversion
Several data conversion functions can be found in the
std_logic_arith package of the ieee library. They are:
 conv_integer(p) : Converts a parameter p of type INTEGER,
UNSIGNED, SIGNED, or STD_ULOGIC to an INTEGER value.
Notice that STD_LOGIC_VECTOR is not included.
 conv_unsigned(p, b): Converts a parameter p of type
INTEGER, UNSIGNED, SIGNED, or STD_ULOGIC to an
UNSIGNED value with size b bits.
 conv_signed(p, b): Converts a parameter p of type INTEGER,
UNSIGNED, SIGNED, or STD_ULOGIC to a SIGNED value with
size b bits.
 conv_std_logic_vector(p, b): Converts a parameter p of type
INTEGER, UNSIGNED, SIGNED, or STD_LOGIC to a
STD_LOGIC_VECTOR value with size b bits.
Data Conversion

Another functions are available using the std_logic_signed or

the std_logic_unsigned package from the ieee library. Besides
the data conversion functions described above, several others
are often offered by synthesis tool vendors.
Data Types
The fundamental synthesizable VHDL data types are
summarized in table below:
Example 1: Dealing with Data Types
Example 1: Dealing with Data Types
Example 1: Dealing with Data Types
Example 1: Dealing with Data Types
Example 2: Single Bit Versus Bit Vector
This example illustrates the difference between a single bit
assignment and a bit vector assignment.
Two VHDL codes are presented. Both perform the AND operation
between the input signals and assign the result to the output
signal. The only difference between them is the number of bits in
the input and output ports (1 bit in the first, 4 bits in the second).
The circuits inferred from these codes are shown in next slides.
Example 2: Single Bit Versus Bit Vector
Example 3: Adder
The 4-bit adder shown below has two inputs (a, b) and one
output (sum).
The first solutions, all signals are of type SIGNED, while in the
second the output is of type INTEGER.
Notice in solution 2 that a conversion function was used in line
13, for the type of a b does not match that of sum. Notice also
the inclusion of the std_logic_arith package (line 4 of each
solution), which specifies the SIGNED data type. Recall that a
SIGNED value is represented like a vector; that is, similar to
STD_LOGIC_VECTOR, not like an INTEGER.
Example 3: Adder
Example 3: Adder
Home work:
The problems below are based on the following TYPE
definitions and SIGNAL declarations:

Determine the dimensionality (scalar, 1D, 2D, or 1Dx1D) of the

signals given. Also, write down a numeric example for each
signal.
QUESTIONS?