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Vlsi Lab 2

Vlsi Lab manual

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Md Badhon
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35 views4 pages

Vlsi Lab 2

Vlsi Lab manual

Uploaded by

Md Badhon
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Bangladesh University of Business & Technology

BUBT

Lab Report
Course Title: VLSI Circuits I Lab
Course Code: EEE 330
Exp. No: 02
Name of the Exp: Schematic and Layout of Inverter using equal rise and
fall resistance.

Submitted by: Submitted To:


Md. Raju Sheikh Rubayat Chowdhury
Id: 19201108011
Intake: 28 Lecturer
Section: 01 Department of EEE
BUBT
CMOS Inverter: CMOS inverter stands for Complementary Metal oxide
semiconductor inverter.

Layout:

Truth Table of CMOS Inverter:


A Y

1 0

0 1
Voltage vs Time waveform:

3d View of Layout:
Discussion: One of the main problems with CMOS inverter layout in Microwind
software is high power consumption. This can be caused by using transistors that
are too large, which increases the current flow and power consumption in the
circuit. To solve this problem, we can reduce the size of the transistors and
optimize the layout to reduce power consumption. The simulation may not
converge or give accurate results due to poor initial conditions or poor step sizes.
To solve this problem, we can use better initial conditions and smaller step sizes
for the simulation. Another problem that can arise with CMOS inverter layout in
Microwind software is a low noise margin. This can be caused by the poor spacing
of the transistors and/or high parasitic capacitances and resistances in the
interconnects. To solve this problem, we can increase the spacing between the
transistors, reduce the width of the interconnects, and use shielding or shielding
materials to reduce the parasitic capacitances and resistances.
It's also a good idea to validate the simulation by comparing the simulation results
with the experimental measurements to ensure the accuracy of the simulation.

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