8086 SYST! The 8086 Microprocessor is a 16-bit CPU available in 3 clock rates, ive. 5, 8 and 10MHz, packaged in a 40 pin CERDIP or plastic package. The 8086 Microprocessor operates in single processor or multiprocessor configurations to achieve high performance. The pin configuration is as shown in figl. Some of the pins serve a particular function in minimum, mode (single processor mode) and others function in maximum mode (multiprocessor mode) configuration, The 8086 signals can be categorized in three groups. The first are the signals having common functions in minimum as well as maximum mode, the second are the signals which have special functions in minimum mode and third are the signals having special functions for maximum mode 2.1 8086 signals Maximum mode Minimum mode ono 4 40) vee ADs] 2 29) ADs ADL 3 38 Aig/Sa ADs (4 87) AS AD, 8 36) AwSs AD! | 6 35] Ale ADs |_|? 34 BHEIS, Ap, 8 33] Mnaax ao, 8 32) AD ADs [10 08s a1 |] RaGT, (HOLD) ADs Ltt 20 |) raver, (HLOA) Ady (| 12 23] LOCK (wr) ADs |_| 49 2 &, (mo) ADs [14 as ov) ap, 15 267] & (EN) ADy (1 25) as (ALE) ni 47 24 |) as; (INTA) INTR (| 18 23) TEST cu 49 22) READY eno [20 at] RESET Fig.2.1 Bus signals [Source: Advanced Microprocessors and Microcontrollers by A.K Ray & K.M. Bhurchandi]‘The following signal description are common for both the minimum and maximum modes. AD1S-ADO: These are the time multiplexed memory I/O address and data lines. Address remains on the lines during T1 state, while the data is available on the data bus during T2, T3, TW and T4. Here T1, T2, T3, T4 and TW are the clock states of a machine cycle. TW a wait state. These lines ate active high and float to a tristate during interrupt acknowledge and local bus hold acknowledge cycles. A19/S6, A18/S5, A17/S4, A16/S3: These are the time multiplexed address and status lines. During T1, these are the most significant address lines or memory operations. During I/O operations, these lines are low. During memory or I/O operations, status information is, available on those lines for T2, T3, TW and T4 .The status of the interrupt enable flag bit(displayed on $5) is updated at the beginning of each clock cycle. The $4 and $3 combinedly indicate which segment register is presently being used for memory accesses as shown in Table 2.1 These lines float to tri-state off (tristated) during the local bus hold acknowledge. The status line $6 is always low (logical). The address bits are separated from the status bits using latches controlled by the ALE signal. Table 2.1. Bus High Enable / status [Source: Advanced Microprocessors and Microcontrollers by A.K Ray & K.M. Bhurchandi] [s¢ Indication 0 ‘| Alternate Data | fo | Stack | 1 | Code or none T BHE/S7-Bus High Enable/Status: The bus high enable signal is used to indicate the transfer of data over the higher order (D15-D8) data bus as shown in Table 2.1, It goes low for the data transfers over D15-D8 and is used to derive chip selects of odd address memory bank or peripherals. BHE is low during T1 for read, write and interrupt acknowledge cycles, when- ever a byte is to be transferred on the higher byte of the data bus. The status information is available during T2, T3 and T4. The signal is active low and is tristated during ‘hold’ It is low during T1 for the first pulse of the interrupt acknowledge cycle. Table 2.2 Bus high enable status [Souree: Advanced Microprocessors and Microcontrollers by A.K Ray & K.M. Bhurchandi] \BHE Mo Indication fo fo ~ | Whole Word fo Upper byte from or to odd address ir “formers nomesioncnalicn i [None E 0 7 RD-Read: Read signal, when low, indicates the peripherals that the processor is performing a memory or I/O read operation. RD is active low and shows the state for T2, T3, TW of any read cycle. The signal remains tristated during the 'holdacknowledge’. READY: This is the acknowledgement from the slow devices or memory that they have completed the data transfer. The signal made available by the devices is synchronized by the 8284A clock generator to provide ready input to the 8086. The signal is active high. INTR- Interrupt Request: This is a level triggered input. This is sampled during the last clockcycle of each instruction to determine the availability of the request. If any interrupt request is pending, the processor enters the interrupt acknowledge cycle. This can be internally masked by resetting the interrupt enable flag. This signal is active high and internally synchronized. TEST: This input is examined by a ‘WAIT’ instruction. If the TEST input goes low, execution will continue, else, the processor remains in an idle state. The input is synchronized internally during cach clock cycle on leading edge of clock. NME-Non-maskable Interrupt: This is an edge-triggered input which causes a Type2 interrupt. The NMI is not maskable internally by software. A transition from low to high initiates the interrupt response at the end of the current instruction. This input is internally synchronized. RESET: This input causes the processor to terminate the current activity and start execution from FFFFOH. The signal is active high and must be active for at least four clock cycles. It restarts execution when the RESET returns low. RESET is also internally synchronized. CLK -Clock Input: The clock input provides the basic timing for processor operation and bus, control activity. Its an asymmetric square wave with 33% duty cycle. The range of frequency for different 8086 versions is from SMHz to 10MHz. VCC: +5V power supply for the operation of the internal circuit. GND ground for the internal circuit MN/MX: The logic level at this pin decides whether the processor is to operate in either minimum (single processor) or maximum (multiprocessor) mode. The following pin functions are for the minimum mode operation of 8086, M/IO - Memory/IO: This is a status line logically equivalent to $2 in maximum mode. When it is low, it indicates the CPU is having an I/O operation, and when it is high, it indicates that the CPU is having a memory operation. This line becomes active in the previous T4 and remains active till final T4 of the current cycle. It is tristated during local bus “hold acknowledge". INTA -Interrupt Acknowledge: This signal is used as a read strobe for interrupt acknowledge cycles, In other words, when it goes low, it means that the processor has accepted the interrupt. It is active low during T2, T3 and TW of each interrupt acknowledge cycle. ALE-Address latch Enable: This output signal indicates the availability of the valid address on the address/data lines, and is connected to latch enable input of latches. This signal is active high and is nevertristated. DT /R -Data Transmit/Receive: This output is used to decide the direction of data flow through the transreceivers (bidirectional buffers). When the processor sends out data, this signal is high and when the processor is receiving data, this signal is low. Logically, this is equivalent to S1 in maximum mode. Its timing is the same as M/I/O, This is tristated during, ‘hold acknowledge’. DEN-Data Enable This signal indicates the availability of valid data over the address/data lines. It is used to enable the transreceivers (bidirectional buffers) to separate the data from the multiplexed address/data signal. It is active from the middle ofT2 until the middle of T4 DEN is tristated during ‘hold acknowledge’ cycle. HOLD, HLDA-Hold/Hold Acknowledge: When the HOLD line goes high, it indicates to the processor that another master is requesting the bus access. The processor, after receiving the HOLD request, issues the hold acknowledge signal on HLDA pin, in the middle of the next clock cycle after completing the current bus (instruction) cycle. At the same time, the processor floats the local bus and control lines. When the processor detects the HOLD line low, it lowers the HLDA signal. HOLD is an asynchronous input and it should be externally synchronized. If the DMA request is made while the CPU is performing a memory or I/O cycle, it will release the local bus during T 4 provided: 1. The request occurs on or before T 2 state of the current cycle. 2. The current cycle is not operating over the lower byte of a word (or operating on an odd address).3. The current cycle is not the first acknowledge of an interrupt acknowledge sequence. 4, A Lock instruction is not being executed, So far we have presented the pin descriptions of 8086 in minimum mode. The following pin functions are applicable for maximum mode operation of 8086. $2, S1, SO -Status Lines: These are the status lines which reflect the type of operation, being carried out by the processor. These become active during T4 of the previous cycle and remain active during TI and T2 of the current bus cycle, The status lines return to passive state during T3 of the current bus cycle so that they may again become active for the next bus cycle during T4. Any change in these lines during T3 indicates the starting of a new cycle, and retum to passive state indicates end of the bus cycle. These status lines are encoded in table 2.3. Table 2.3. Status lines [Souree: Advanced Microprocessors and Microcontrollers by A.K Ray & K.M. Bhurchandil S Ss So Indication 0 fo fo Interrupt Acknowledge [0 fo 1 0 7 {o [0 a ie | 1 [fo fo ‘Code Access | T [o fi Read memory | [7 a 0 Write memory i = | LOCK: This output pin indicates that other system bus masters will be prevented from gaining the system bus, while the LOCK signal is low. The LOCK signal is activated by the ‘LOCK’ prefix instruction and remains active until the completion of the next instruction. This floats to tri-state off during "hold acknowledge". When the CPU is executing a critical instruction which requires the system bus, the LOCK prefix instruction ensures that other processors connected in the system will not gain the control of the bus. The 8086, while executing the prefixed instruction, asserts the bus lock signal output, which may be connected to an external buscontroller. QSI, QS0-Queue Status: These lines give information about the status of the code prefetch queue. These are active during the CLK eycle after which the queue operation is performed, These are encoded as shown in Table 2.4. Table 2.4. Queue Status [Source: Advanced Microprocessors and Microcontrollers by A.K Ray & K.M. Bhurchandi] QS:, QS, Indication 0 0 “No operation 0 1 "| First byte of opcode from the queue 1 fo Empty queue 1 1 Subsequent byte from the queue