MICROPROCESSOR INTERFACING

MOUNT KENYA UNIVERSITY

DATE 6TH /JANUARY / 2023

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 TABLE OF CONTENTS

Contents

1. INTRODUCTION................................................................................................................................1
2. LITERATURE REVIEW.....................................................................................................................2
2.1.1 TYPES OF MICROPROCESSOR INTERFACES...............................................................3
2.1.1.1 INPUT / OUTPUT (I/O) INTERFACING............................................................................3
2.1.1.2 MEMORY INTERFACING..................................................................................................16
2.1.1.2.4 Microprocessor Read Only Memory (ROM) Interfacing.........................................26
2.1.1.2.5 Microprocessor RAM Interfacing................................................................................28
4. CONCLUSION..................................................................................................................................35

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 MICROPROCESSOR INTERFACING
1. INTRODUCTION

A microprocessor is an electronic chip which operates like the central

processing unit of a computer (Kumar et al., 2012). Microprocessors are

found in almost all consumer electronic appliances and systems such as

washing machines, computers, microcontrollers, micro-eletro-mechanical

systems, computer printers, microwave ovens, fax machines, mobile phones,

photocopiers, vehicles, satellites, radars and aircrafts. A microprocessor has

only one set of addresses and data buses to be used by all peripherals. This

prompts the inclusion of some sort of interfacing schemes with techniques of

selecting the peripheral device that is required to communicate with the

microprocessor while isolating all other peripherals, and ensuring that all the

peripherals are connected with the microprocessor at all times. Computer

instructions referred to as programs are written by the user to be used by the

microprocessor to work with real world data. Data available in various forms

and from various sources requires input interfacing to feed them to the

microprocessor-based systems.

For a microprocessor to become a more useful device it requires to be linked

to other electronic components.  To design a computer the microprocessor

requires to be connected to the disk memory, USP ports, keyboard, main

memory etc. The display unit and the keyboard requires to be connected with

the microprocessor since it is used as a communication channel. During the

processing of data the microprocessor-based systems require the interface of

data electronic processing circuits. After processing the real world data, the

microprocessor-based systems requires an interface of output circuits, data

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converters, ports and devices to output data to the real world. Also the

microprocessor-based system requires an array of memory units and inter-

connecting circuits for outputs and inputs. For a microprocessor to function

efficiently and give accurate outputs it requires a proper communication with

its peripherals. All this is achieved through microprocessor interfacing.

2. LITERATURE REVIEW

2.1 MICROPROCESSOR INTERFACING

Microprocessor interfacing is a technique of connecting a microprocessor to

the peripherals. It is the creation of communication paths between the

microprocessor, the memories, output devices and input devices.

To interact with a certain device, the processor puts a device address on

address lines. Each Inter-interconnection decodes the address and control

gotten from the input / output bus, interprets them for peripherals and offers

signals for the peripheral controller. It is also synchronizes the data flow and

oversees the transmission between peripheral and processor. Each peripheral

owns a controller. The control lines are known as input/output command.

These commands are include control command, status command, data output

command and data input command. A control command is delivered to

actuate the peripheral and notify it what to do. A status command is used to

test various status circumstances in the interface and peripheral. A data

output command makes the interface to respond by transmitting data from the

bus to one of its registers. The data input command is the opposite of the

data output. In this case the interface receives on item of data from the

peripheral and places it in its buffer register.

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2.1.1 TYPES OF MICROPROCESSOR INTERFACES

There are two main types of microprocessor interfacing, namely memory

interfacing and input / output interfacing.

Figure 1 Memory and I/O Interfacing Pins

Figure 1 Types of microprocessor interfacing

2.1.1.1 INPUT / OUTPUT (I/O) INTERFACING

Input / output bus and interface module synchronize the data flow and delivers

a technique for transporting data between external input/output devices and

internal storage. Microprocessor reads data from input devices such as

keyboard, scanner and many other peripherals and writes data to output

devices like monitor, printer and many others. When one or several

input/output devices (peripherals) are to be linked to a microprocessor, a link

circuit for each device known as a peripheral interface is needed. The

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interface carry out buffering, address coding, command addressing, timing,

and control.

Buffering

Buffering takes care of incompatibility between the microprocessor and the

peripheral.

Address decoding

Address decoding selects one of the several peripherals connected in the

system.

Command decoding

Command decoding helps the peripherals to carry out activities other than

information transmission.

Timing and control

Timing and control regulate buffering, address decoding and command

decoding. Interfacing devices are extensive hardware (IC chips) and are used

for designing custom interfaces. Interfacing devices include multiplexer,

demultiplexers, line drivers, receivers, level translators, buffers, a stable

multivibrators and monostable multivibrators, latches, gates, shift registers,

and others. Also there are other more sophisticated interfaces like the

programmable inter-faces whose roles may be changed by the

microprocessor instruction. These programmable interfaces can be of or

special purpose or general purpose type commonly referred to dedicated

function type.

Some of the interfaces are different communication components like the

printer, mouse, keyboard and many others. Input / Output (I/O) interfacing is

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the linking of the microprocessor with the keyboard and other devices.

Latches and buffers are used to interface the microprocessor with the

keyboards and displays.

2.1.1.1.2 Keyboard Interfacing

In mmajority of the keyboards, the key switches are linked in a matrix of

columns and rows.

There are three major required tasks in getting meaningful data from a

keyboard:

1. Detect a key press.

2. De-bouncing the key press.

3. Encode the key press (produce a standard code for the pressed key).

The microprocessor read logic “0” when the key is pressed.

Key Debounce:

Whenever a mechanical push-bottom is pressed or depressed once, the

mechanical components of the key do not change the position smoothly;

instead it generates a transient response (Reddy, 2000). These can be

construed as the multiple pressures and answered amicably.

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Figure 2 A Mechanical Key and its response (Source: Reddy, 2000)

Figure 3 Hardware De-bouncing Circuit (Source: Reddy, 2000)

The rows of the matrix are linked to four output port lines and columns are

connected to four input port buses. When no keys are pressed, the column

lines are held high by the pull-up resistors connected to +5 volits. Pressing a

key connects a row & a column.

To determine whether any key is pressed is to output 0‟s to all rows & then

examine columns to see if a pressed key has connected a low (zero) to a

column. When all columns are high, the program enters another loop, which

holds until a low appears on one of the columns which is an indication of a

key press. A simple twenty (20) or ten (10) milliseconds delay is executed to

debounce the task. After the debounce time, another determination is made

to perceive whether the key is still pressed. If the columns are this time all

high, then no key is pressed and the earlier detection would have been

caused by a noise signal.

To prevent detection caused by a noise signal, two arrangements are

recommended:

1. Place a bistable multivibrator at the output of the key to debounce it.

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2. The microprocessor has to pause for the transient period (at least for ten

(10) milliseconds), so that the transient response reduces to a steady state

position.

If any of the columns are low at the moment, then the supposition is made

that it was an effective key press. The last activity is to define the row and

column of the pressed key and change this data to Hex-code for the pressed

key. The 4-bit code from the input port and the 4-bit code from the output port

(row and column) are changed to Hex-code.

Figure 4 Interfacing 4x4 keyboard (Source: Reddy, 2000)

Table 1 Display Interface

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2.1.1.1.2 Interfacing multiplexed 7-segment display

Figure 5 interfacing multiplexing 7 segment display (Source: Reddy, 2000)

To display 6: all LEDs A to G will be on except B; D7 to D0 = 00000010 =02H

MV1 A, 02 OUT F5H.

INTERFACING DIO SWITCHES (PARTIAL DECODING)

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To read switches: IN 84H / 8CH /94H / 9CH. A = F8H.

Figure 6 Interfacing DIO Switches (Partial Decoding)

2.1.1.1.5 Interfacing ADC chip with a microprocessor

Interfacing ADC 0808 with 8086 using 8255 port.

The 8255 is used to transfer digital data output of analogue to digital (ADC) to

the CPU and port C to control signals. Assume that an anlage input present

at input 2 of the analogue to digital (ADC) and a clock input of suitable

frequency is available for ADC.

Input / output (I / O) addressing

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Figure 9 Input / output (I / O) addressing

Microprocessor identifies, differentiates input / output (I/O) devices by their

unique addresses. Input / output (I/O) addressing is done in two ways namely

memory mapped I/O and I/O mapped I/O.

1. Memory mapped I/O:

In memory mapped I/O, I/O a device is treated or addressed as one of the

memory locations.

2. I/O mapped I/O:

I/O mapped I/O device is treated as I/O device. In I/O mapped I/O: eight

address lines are used (A0 – A7). 28 = 256 addresses are generated.

256 input and 256 output devices can be addressed. IN /OUT instructions are

used. [In XXH, OUT XXH]. Io/M is high i.e. control signals used are IOR and

low.

OUTPUT DEVICES ADDRESSING (LEDs)

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Figure 10 Output devices addressing (LEDs)

When a latch is enabled, data lines are transferred to LEDs. MVI, OFH

makes A = OFH which OUT 0IH.

The instruction out 01Hb results in: A7 – A0 = 00000001 = 01H which makes

IOARD’ low; WR’ low; IO/M’ high; latch enabled; copying of accumulator

contents to data line; LED0 – 3 go off and LED4-7 glows.

OUTPUT DEVICE ADDRESSING (LEDs): PARTIAL DECODING

A0 and A1 lines are not used. Latch will be enabled for all values of A0 and

A1 as long as A7 to A2 are equal to 000000. So we can write data on LEDs

using four addresses: 00H.01H, 03H and 03H termed as partial decoding.

Unique addresses are used for absolute decoding.

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Figure 11 Output device addressing (LEDs): Partial decoding

INPUT DEVICE ADDRESSING (SWICHES)

If the buffer is enabled the status of the switches will be transferred to D0 to

D7.

IN FFH

Instruction IN FFH result in A0 to A7 = FFH, IOADR’LOW; RD’ low; IO/M’

high; Buffer Enabled; Data lines (Switches) contents get copied to

accumulator and accumulator = FFH.

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Figure 12 Input device addressing (Switches)

ADDRESSING USING DECODER

For Latch

For Latch

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Figure 13 Addressing using decoder

Microcontroller input / output interfacing commands

Types of input output microprocessor interfacing commands

Microprocessor input / output interfacing use control, status and data input /

output commands.

1. Control command:

Control command is supplied to activate the peripheral and inform it what

action to take.

2. Status command:

Status command test various status conditions.

3. Data output / input command:

Data output / input command is used to transfer data from bus in one of the

shift registers.

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MEMORY MAPPED I/O

In memory mapped I /O, the I /O is treated as a memory, sixteen (16) address

lines are used (A0 – A15), 64K addresses are shared between memory I / O,

memory related instructions are used [LDA XXXX, STA XXXXH] and IO/M’ is

low that is control signals used are MEMR’ and MEMR’ and MEMW’.

MEMORY MAPPED I/O

For lach;

MVI A,48H,

STA FFF8H

For Buffer;

LDA FFF9H

A = B7H

Figure 14 Memory mapped I/O

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Comparison of memory mapped I/O and I/O mapped I/O

2.1.1.2 MEMORY INTERFACING

Memory interfacing requires a memory interface device. The memory

interface device selects the required chip, identifies the required register and

enables the appropriate buffers.

Memory is an integral part of a microprocessor and it is organized as two

dimensional arrays of memory locations. There are two main types of

memories, namely Random access memory (RAM) and Read only memory

(ROM).

1. A Read Only Memory reads signals and store programs that do not need

changes. The examples of Read Only Memories are PROM, EPROM and

EEPROM.

2. Random access memory (RAM) stores user programs, store temporary

data, reads and writes data.

The primary purpose of the memory interfacing is to help the microprocessor

to read and writing data in a given register of the chip. To executing any

instruction, the microprocessor must link with the memory to read the data

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and instruction codes stored in the memory. Both the microprocessor and the

memory requires some signals enable them to write to or read information

from the registers. The process of memory and microprocessor interfacing

needs matching of the requisite of the memory with the signals of the

microprocessor.

General procedure of memory interfacing of 8086 microprocessor unit

1. Arrange the available chips so as obtain a 16-bit data bus width. The

upper 8-bit bank is known as “odd address memory bank” and the lower 8 bit

bank is known as the “even address memory bank”.

2. Connect availlable memory address lines of memory chips with those of

the microprocessor and then connect the memor RD and WR input to the

corresponding processor control signals.

3. The remaining address lines of the microprocessor, BHE , AO used for

decoding the required chip select signals for the odd and even memory

banks. CS is derived from the output of circuit.

The figure below illustrates a generic interfacing between a microprocessor

and a memory sub-system. Assuming that it is a 16-bit address bus and an 8-

bit data bus. The control signals go between the two to control the transfer of

information, and is normally governed by the microprocessor which plays the

role of the “master”.

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Figure 15 Microprocessor memory interface (Source: Cheung, 2018)

During each memory cycle. A15:0 selects one of 2 16 possible memory

locations. D7:0 transfer one word (8 bits) of information either to the memory

(write) or to the microprocessor (read). D7:0 connections to the

microprocessor are tri-state (V ): they can be: - “logic 0”, or “high impedance”

(inputs). The control signal informs the memory what activity to perform and

when to carry it out.

Microprocessor memory chip selection

The chip select (CS) helps the microprocessor to select the required chip.

The address decoder circuit selects which memory sub-system and

determines which memory chip to enable. This circuit takes the upper bits of

the address bus, and produce enable signals for ROM, RAM, and

INOUTx for a specific I/O device. Normally an I/O device may take up to 4

memory locations.

In this case, INOUTx takes only the address space $F574 - $F577,

i.e. 4 locations. Therefore we require to decode a lot of address signals:

A15:2.

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The ROM CE signal is another challenge. The ROM is enable if the address

A15:A12 falls between the range 4’b1011 and 4’b1110. You should prove for

yourself that the Boolean equation to decode the address for the ROM is as

shown here.

Every memory circuit has a “chip enable” input (CE). The “decoder” utilizes

the top few address bits to make a choice of which memory circuit should be

enabled. Every memory circuit is enabled only for the correct address range

as follows;

ROM = A15 & A14 & ~ (A13 & A12) | (A15 & ~ A14 & A13 & A12)

RAM = ~15

INOUTx = A15 & A14 & A13 & A12& ~A11 & A10 & ~A9 & A8 & ~A7 A6 & A5

& A4 & ~A3 & A2. INOUTX replies to addresses 16F574 TO 16F577, other

I/O circuits will have different addresses. Low n address bits choose one of 2 n

locations in each memory circuit (value of n rest on on memory size).

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Figure 16 Memory chip selection (Source: Cheung, 2018)

Table 2 Address range and usage

Memory interface control signals

1) A clock signal that regulates the timing (may be like the system CLOCK)

2) A signal decides whether the microprocessor needs to read from memory

or write to memory. Must make sure the d7:0 is only driven at one end.

In addition to the address decoder circuit, we have to supply the regulating

signals from the microprocessor to the memory chips. At this point we

presume that there is at least two regulating signals from the microprocessor:

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The memory clock signal, MCLOCK which could be different from the system

clock signal, CLOCK), and a WRITE signal to memory when high and vice

versa.

There are two types of microprocessor and memory transactions: a Write

Cycle and a Read Cycle.

In Read Cycle the microprocessor declares the address A15:0 and the control

signals MCLOCK and WRITE. Shortly after the commencing of the Read

Cycle, the microprocessor must halt driving of the data bus D7:0, and at the

second half of the cycle, we presuppose that memory will deliver the data for

the microprocessor to read. Reading is essentially done at the end of the

Read Cycle that is on the falling edge of MCLOCK.

Throughout a Write Cycle, the microprocessor initiates everything. Writing too

occurs on the falling edge of MCLOCK.

Figure 17 Memory interface control signal (Source Cheung, 2018)

D7:0 from memory is solitary allowed when MCLOCK & ~WRITE true

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Memory circuit control signals

Figure 18 Memory circuit control signals (Source: Cheung, 2028)

This figure indicates the control circuit used to interface the microprocessor to

the 32k x 8 RAM chip. Chip Enable (CE) is run by the output from the

address decoder.

Microprocessor memory interfacing timing

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Figure 19 microprocessor memory interfacing timing (Source: Cheung, 2018)

At this point we consider what the microprocessor expects about timing. We

presuppose that a memory transaction cycle starts at falling edge of

MCLOCK. Gates are presumed to have a delay of 1 nanosecond.

Consequently WR and OE signals are halted by 1 nanosecond. A15:0 is

presumed to hold its preceding value for at least 3 nanoseconds, but will

transit to the new value after 8 nanoseconds, likewise with the WRITE signal.

2.1.1.2.2 Static Memory Interfacing

The general procedure of static memory interfacing is as stated below:

1. Place the existing memory chips so that you obtain a number of bit data

bus width. The upper number of bit bank is known as ‘odd address memory

bank’ and the lower number bit bank is known as ‘even address memory

bank’.

2. Attach existing memory address lines of the memory chips to those of the

microprocessor and also connect the memory WR and RD inputs to the

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conforming processor control signals. Link the total number of bit data bus of

the memory bank to that of the microprocessor.

3. The left over address lines of the microprocessor, BHE and A0 are used for

decoding the needed chip select signals for the even and odd and memory

banks. Chip select (CS) of memory is obtained from the decoding circuit

output. The address map of the system ought to be continuous as possible,

that is, there should be no windows in the map. A memory location must have

one address conforming to it, that is, outright decoding must be anticipated,

and least hardware should be used for decoding. Mostly, linear decoding are

used to diminish the hardware requirements.

2.1.1.2.3 Interfacing two 4 K X EPROMS and 4K X 8 RAM chips with 8086

To interface two 4K X EPROMS and 4K x 8 RAM chips with 8086, choose

appropriate maps. Upon reset, the IP and CS are set to form address

FFFFOH. So, this address should lie in the EPROM. The address of RAM

could be carefully chosen anywhere in the 1MB address space of 8086, but to

guarantee that the address map of the system is constant you select the

RAM address as shown in table 3 below.

Table 3 Memory Map for interfacing

FFFFFH 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

EPROM 8K X 8

FE000H 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0

FDFFFH 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1

RAM 8K X 8

FC000H 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0

Total 8K byte of EPROM takes13 address lines A 0 – A12 (Since 213 =8K. A13

– A19 are utilized for decoding to create the chip select. The BEH signal

drops low when a transfer is at odd address or a higher byte of data is to be

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accessed. Assuming that the latched address BEH and demultiplexed

statistics lines are freely available for interfacing. Figure 20 illustrates the

linking diagram for the memory system.

The memory system

At this point it has a total four of 4K x 8 memory chips. The 4Kx8 chip ROM

and RAM are organized in parallel to achieve 16-bit data bus breadith. If A 0 is

o, i.e. the address is even and in RAM, then the lower RAM cip is selected

indicating 8-bit transfer at even address. If A 0 is 1, that is, the address is odd

and is in RAM, the BEH changes to low, the upper RAM chip is chosen,

further showing that 8-bit transfer is at an odd address. If the chosen address

are in ROM, the particular ROM chips are chosen. If at a time A 0 and BEH

both are 0, both the RAM and ROM chips are selected that is the data is of 16

bits. The selection of chips here happens as shown in table 4.

Table 4 Memory Chip Selection

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Figure 20 Memory interfacing (Source: Rayand Bhurchandi, 2006)

2.1.1.2.4 Microprocessor Read Only Memory (ROM) Interfacing

and program instructions. The typical 8 bit microprocessor chip has a 16 bit

address-bus and can address up to 2 16 (i.e. 65,535) different memory

locations.

A simple case random access memory (ROM) is illustrate in Fig. 21. Here we

have 1024 bytes of ROM interfaced directly to the Z-80. In this situation the

ROM is assigned to the lower 1K of the memory-address range. The positions

existing are 00 00 (hex) to 03 FF (hex). Since it is dealing with the lower 1K, it

requires only the lower-order byte of the address bus, A O - A7, and two least-

significant-bits (LSB) of the upper-order byte (A8 and A9).

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Figure 21 ROM Interfacing (Source: Carr, 1982)

It consists of two chip-enable (CE) terminals CE 1 and CE2. The CE2 make

sure that the ROM responds only to address in the lower 1K of memory.

Address-bus bit-AlO at all times remains low when the CPU is addressing a

location in the lower 1K, but goes high when an address greater than 03 FF

(hex) is chosen. The ROM, therefore, is enabled only when the address on

the address bus is less than 03 FF (hex).

The second chip-enable pin (CE 1) turns on the ROM only when the

microprocessor memory-reading operation is taking place. This CE pin turns

on the ROM when it sees a high. This is because a NOR gate outputs a high

only when both inputs are low. Therefore, by applying the MREQ and RD

control signals from the CPU to the inputs of a NOR gate you create a device-

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select command for CE 1. The CE1 goes high only when the memory-read

operation takes place.

At least two of the more prevalent ROM chips need only a single chip-enable

command.

In Fig. 6-2, bellow is a 256-byte ROM. The chip enable is designated CE

which is an active-low input. The CE terminal is becomes low whenever the

microprocessor is to read the contents of one of the locations in the chip.

To carry out the read operation you construct external circuitry that brings the

chip-enable terminal low when you want. The easiest method to attain this is

to utilize a three-input NOR gate and an inverter. The output of the NOR gate

goes high only when all the three of the inputs are low. When the MRE , RD,

and bit A8 of the address bus are connected to the respective inputs of the

NOR gate and the conditions are attained, the output of the gate goes high

and is inverted to become the CE signal required by the erasable-

programmable ROM (EPROM) chip.

2.1.1.2.5 Microprocessor RAM Interfacing

An substitute method is illustrated in Fig. 23. Now use two inverters and a pair

of NOR gates to create the CE signal. The idea is to cause CE to go low when

the three conditions are met. To do this, both inputs of NOR-gate 2 must go

low simultaneously. One of the inputs is connected to bit AS of the address

bus, as the other is connected to the inverted MWEQ of NOR gate 1. The

inputs of gate 1 are, in tum, connected to RJ signals.

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Figure 22 RAM Interfacing circuit (Source: Carr, 1982)

Note in Fig. 23 that two chips are utilized to form a 256-byte static-RAM. Many

memories need more than a one chip so as to form a whole byte-array. In this

scenario, each memory chip contains a 256 x 4-bit array, so two of them form

a 256 x 8-bit array (i.e., 256 bytes of memory). The prevalent 2102 is listed as

a 1024 x I-bit device. Interfacing eight of them add up to a 1024-byte memory.

Figure 23 RAM interfacing (Source: Carr, 1982)

DYNAMIC MEMORY

Dynamic RAM does not keep its data for a long duration of time. It can on

keep data for a long time on when a refresh process is done. The refresh

process is a role of the CPU in most cases, but some non-central processing

units exist. Though the usage of Static RAM eradicates this problem, it

consumes more power. The Z-80A component provides for refresh of the

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dynamic memory by summing a refresh fragment to the first machine cycle

(instruction fetch).

Figure 24 Dynamic RAM interfacing

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STEPPER MOTOR INTERFACING

Stepper Motor Interfacing: A stepper motor is a device used to obtain an accurate

position control of rotating shafts. It employs rotation of its shaft in terms of steps,

rather than continuous rotation as in case of AC or DC motors. To rotate the shaft of

the stepper motor, a sequence of pulses is needed to be applied to the windings of the

stepper motor, in a proper sequence. The number of pulses required for one complete

rotation of the shaft of the stepper motor is equal to its number of internal teeth on its

rotor. The stator teeth and the rotor teeth lock with each other to fix a position of the

shaft. With a pulse applied to the winding input, the rotor rotates by one teeth position

or an angle x. The angle x may be calculated as: X=3600 /no. of rotor teeth. After the

rotation of the shaft through angel x, the rotor locks itself with the next tooth in the

sequence on the internal surface ofstator. The internal schematic of a typical stepper

motor with four windings is shown in fig.1.

Fig.1 Internal schematic of a four winding stepper motor

The stepper motors have been designed to work with digital circuits. Binary level

pulses of 0-5V are required at its winding inputs to obtain the rotation of shafts. The

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sequence of the pulses can be decided, depending upon the required motion of the

shaft. Fig.2 shows a typical winding arrangement of the stepper motor.

Fig.2 Winding arrangement of a stepper motor

Fig.3 shows conceptual positioning of the rotor teeth on the surface of rotor, for a six

teeth rotor.

Fig.3 Stepper motor rotor

The circuit for interfacing a winding Wn with an I/O port is given in fig.4. Each of the

windings of a stepper motor needs this circuit for its interfacing with the output port.

A typical stepper motor may have parameters like torque 3 Kg-cm, operating voltage

12V, current rating 0.2 A and a step angle 1.80 i.e. 200 steps/revolution (number of

rotor teeth).

A simple schematic for rotating the shaft of a stepper motor is called a wave scheme.

In this scheme, the windings Wa, Wb, Wc and Wd are applied with the required

voltages pulses, in a cyclic fashion. By reversing the sequence of excitation, the

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direction of rotation of the stepper motor shaft may be reversed. Table.1 shows the

excitation sequences for clockwise and anticlockwise rotations. Another popular

scheme for rotation of a stepper motor shaft applies pulses to two successive windings

at a time but these are shifted only by one position at a time. This scheme for rotation

of stepper motor shaft is shown in table2.

Fig.4 interfacing stepper motor winding

Table.1 Excitation sequence of a stepper motor using wave switching scheme

Table.2 An alternative scheme for rotating stepper motor shaft

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 ASSEBLY LANGUAGE PROGRAMS
ASSEMBLY PROGRAMME FOR RUNNING A SEVEN SEGMENT
INTERFACED WITH SEVEN SEGMENT DISPLAY

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ASSEMBLY PROGRAM FOR RUNNING A STEPPER MOTOR IN HALF
STEPS

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ASSEMBLY LANGUAGE PROGRAM FOR RUNNING A STEPPER MOTOR
IN FULL STEPS

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PROGRAM FOR STEPPER MOTOR ROTATION

STEPPER MOTOR INTERFACE

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38
ASSEMBLY LANGUAGE PROGRAM FOR INTERFACING A MATRIX
KEYBOARD

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KEYBOARD INTERFACING CMD (COMMAND PROMPT)
PROGRAM
The desktop computer is turned ON and start option is clicked and CMD (command
prompt) is selected. In order to enter the editor window for writing the program the
following steps are performed.

PROGRAM FOR MULTPLEXING DISPLAY

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41
AN ASSEBLY LANGUAGE PROGRAM FOR ROTATING A
STEPPER MOTOR CLOCKWISE WHEN INTERFACED WITH A
8086 MICROPROCESSOR

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