6 @ CO) 2 @ CO) & @ ) © M-isr22 A CMOS inverter has jn.con = 120 wA/ ‘V2 up.con = 60 pA/V2, VTO, n= 08 V, VTO, p = -1.0 V, TPHL = 02 ns, TPLH = 0.15 ns, VDD = 3v Cload = 300 ff Determine (W/L) and (W/L\p.9 Draw the explain VTC of resistive load inverter, 6 Unit 1V Draw the circuit diagram of six transistor SRAM cell and explain its working. 7 Explain the propagation delay and power consumption issues of CMOS gate, 8 Plot the precharge and evaluation modes of dynamic gates timing diagram. § Classify the various Ratioed circuit for CMOS circuits and explain in detail. § Design a one-ttansistor DRAM cell. 5 [No of Printed Pages Rall No. 18F22 B.Tech. EXAMINATION, 2022 (Sixth. Semester) (C Scheme) (Main & Re-appear) (ECE) ECE304C VLSI DESIGN Time : 3 Hours) [Maximum Marks : 75 Before answering the question-paper candidates should ensure that they have been supplied to correct nd complete question-paper: No compla regard, will be entertained after the examination Note : Attempt Fine questions in al. aman M1822 Pro.1 @ O) © CO) 3. @ M-isr22 Unit 1 Explain in detail about the body effect wits feet in MOS device. 5 What are the limitations ofthe MOSFET characteristics ? 5 What is Moore's law ? State various IC technologies on the basis of number of transistors on a chip. Define threshold voltage with suitable equation of a MOS device. 5 MOSFETs are said to be more efficient than BITS, Justify the answer ° How do you prevent latch up problem ? 6 Unit 1 Derive the expression for Logie Fan-Out Characteristics of any Digital Circuits. 6 2 O) What is a CMOS different from the MOS switch ? Draw the resistance characteristics of the CMOS. witch ? How is it switch. 9 4. (a) What are current sources and current sinks 2 7 (0) Derive the expression for MOS resistance and explain why very high resistance cannot be emulated using MOS resistor with the help of | MOSresistance characteristics, 8 Unie HL 5. (a) State the advantages of transmission gate 4 (b) Draw the switch level schematic of multiplexer based nMOS latch using nMOS only pass transistors for multipliers 6 (©) Draw the 3-input NOR gate using CMOS logic with truth table 5 sama) M1822 3 Pro.