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ESS AudioDrive ES1879a

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21 views112 pages

ESS AudioDrive ES1879a

Uploaded by

Greg
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
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PRELIMINARY ES1879

AudioDrive Solution
®

Data Sheet

DESCRIPTION Advanced Power Management (APM) features include


suspend and resume from disk.
The ES1879 AudioDrive solution is a mixed-signal single-chip
solution that adds 16-bit stereo sound and FM music The ES1879 is backward compatible and pin compatible with
synthesis to notebook computers. It is compliant with the the ES1878.
Microsoft PC97 specification and WHQL audio The ES1879 AudioDrive® solution is available in an industry-
requirements. The ES1879 includes an embedded standard 100-pin Small Quad Flat Pack (SQFP) package.
microcontroller, an OPL3™ superset ESFM™ music
synthesizer, 16-bit stereo wave CODEC, 16-bit stereo system
DAC, 16-bit stereo music DAC, 16-bit stereo I2S DAC,
FEATURES
optional ISA Plug and Play (PnP) support, hardware master ‡ Single, high-performance, mixed-signal, 16-bit stereo
volume control, DMA control logic with FIFO, ISA bus VLSI chip for digital audio
interface logic, general-purpose I/O, and digital dual game
‡ High-quality, OPL3 superset ESFM™ music synthesizer
port. The ES1879 also incorporates three serial ports that
allow interfacing with external DSP, wavetable, and MIDI ‡ Patented ESPCM compression
(MPU-401 UART mode compatible). In addition, the ES1879 ‡ High performance DMA supports Demand Transfer or
offers I2S Zoom Video interface and support for the optional F-type
ES978 Expansion Audio Mixer in docking stations.
‡ Integrated 3-D audio effects processor from Spatializer®
A four-wire expansion analog bus and two-wire serial control
bus connect the ES1879 with the ES978, allowing the Record and Playback Features
ES1879 to engage the docking station’s audio resources ‡ Record, compress, and play back voice, sound, and
when docked. music

The ES1879 AudioDrive can record, compress, and play back ‡ 16-bit stereo CODEC for digital audio
voice, sound, and music with built-in mixer controls. Using two
‡ 3 additional stereo DACs for system playback, music
high-performance DMA channels, the ES1879 supports full-
synthesis and I2S from PC card
duplex operation for simultaneous record and playback. One
channel supports bidirectional DMA data transfers and the ‡ Programmable sample rate from 4 kHz to 48 kHz for
other supports DMA playback. record and playback
The ES1879 AudioDrive supports optional ISA Plug and Play ‡ 2- or 3-button hardware volume control for up, down, and
with configuration for 4 logical devices: configuration device, mute
audio plus ESFM™ synthesis, game port, and MPU-401. ‡ Full-duplex stereo operation for simultaneous record and
playback
The integrated 3-D audio effects processor uses technology
from Spatializer® Audio Laboratories, Inc. and expands the Inputs/Outputs
sound field emitted by two speakers to create a resonant 3-D
sound environment. ‡ MIDI serial port compatible with MPU-401 UART mode
The MPU-401 hardware is for interfacing with an external ‡ Supports up to 7 general-purpose inputs and 7 general-
MIDI serial port. The ES1879 music DAC allows the use of an purpose outputs that can be slaved with corresponding
external wavetable (ES689/ES69x) connected to a wavetable pins of ES978 expansion audio mixer
serial port. I/O address, DMA and interrupt selection can be ‡ ESS high performance dual game port with hardware
controlled through system software or Plug and Play. timing
A DSP serial interface in the ES1879 allows an external DSP ‡ Optional full ISA Plug and Play support
to take over ADC or DAC resources. ‡ I2S Zoom Video port interface with a sample rate up to 48
The ES1879 supports telegaming architecture with headsets kHz for MPEG audio
and includes data paths for host-based Acoustic Echo ‡ Wavetable serial port interface to ES689/ES69x for direct
Cancellation processing. access to the music DAC
The enhanced dual game port supports hardware timing
interrupt generation that eliminates the need for CPU polling.

ESS Technology, Inc. SAM0025A-062397 1


PRELIMINARY ES1879 DATA SHEET
TYPICAL APPLICATION

Interfaces to Expansion Audio Mixer (ES978) Power


‡ Simple hot-docking interface to ES978 expansion audio ‡ Advanced Power Management supports suspend/
mixer resume from disk
‡ Two-wire digital status and data communication between ‡ Supports 3.3 or 5.0 V operation
ES1879 and ES978 supports register mirroring with
worst-case latency of approximately 140 µsec Compatibility
‡ Has on-chip dual pairs of analog differential signals for ‡ Supports PC games in Sound Blaster™ and Sound
audio I/O with ES978 expansion audio mixer Blaster™ Pro modes
‡ Supports Microsoft Windows™ Sound System
Mixer Features
‡ Meets PC97 and WHQL specifications.
‡ 6-channel stereo mixer inputs for line, auxiliary A (CD
audio), auxiliary B, digital audio (wave files), music Operating Systems
synthesizer, I2S Zoom Video plus a mono channel mixer
input for microphone ‡ Microsoft Windows95

‡ Programmable 6-bit logarithmic master volume control ‡ Microsoft Windows™ 3.1


‡ Microsoft Windows for Workgroups™
Plug and Play (PnP) Features ‡ Microsoft Windows NT™ 3.51 & 4.0
‡ On-chip Plug and Play support for audio, joystick port, ‡ IBM OS/2 Warp™
FM, and MPU-401
‡ Software address mapping, four DMA and five IRQ
selections for motherboard implementation
‡ Internal configuration data for audio Plug and Play
support
‡ Read/Write serial interface for Plug and Play resource
EEPROM

TYPICAL APPLICATION

Notebook PC
Docking Station
Line
Option
I2S Zoom Video Auxiliary
Line Aux
Mic Joystick
XA[3:0]
Mic
CD Audio XSC
ES978 XSD ES1879 CD Audio
Speakers DOCKED Speakers

I2S Zoom Video

Joystick
3-D Option Wavetable Option
ISA Bus
ES689/
ES938 ES69x Wavetable Option

ES689/
ES69x

2 SAM0025A-062397 ESS Technology, Inc.


ES1879 DATA SHEET PRELIMINARY
CONTENTS

CONTENTS
DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ANALOG DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . 28
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Reference Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Record and Playback Features . . . . . . . . . . . . . . . . . . . . 1 Switch-Capacitor Filter . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Inputs/Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Audio Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . . . 28
Interfaces to Expansion Audio Mixer (ES978) . . . . . . . . . 2 CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Mixer Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Using ISA PnP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Plug and Play (PnP) Features . . . . . . . . . . . . . . . . . . . . . 2 Non PnP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Bypass Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Accessing the ROM/EEPROM . . . . . . . . . . . . . . . . . . . . 30
Operating Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 PnP Configuration and Registers . . . . . . . . . . . . . . . . . . 30
TYPICAL APPLICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Logical Device Registers . . . . . . . . . . . . . . . . . . . . . . . . 36
CONTENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 PROGRAMMING THE ES1879 . . . . . . . . . . . . . . . . . . . . . . . 47
PINOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Identifying the ES1879 . . . . . . . . . . . . . . . . . . . . . . . . . . 47
PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Resetting the Audio Device via Software . . . . . . . . . . . . 47
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 8 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Digital Subsystems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Analog Subsystems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Compatibility Mode Programming . . . . . . . . . . . . . . . . . 50
MIXER SCHEMATIC BLOCK DIAGRAM . . . . . . . . . . . . . . . 10 Extended Mode Programming . . . . . . . . . . . . . . . . . . . . 52
TYPICAL APPLICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Programming the ES1879 Mixer . . . . . . . . . . . . . . . . . . 59
ISA BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
DIGITAL AUDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Types of Register Access . . . . . . . . . . . . . . . . . . . . . . . . 62
Programming Data Transfers . . . . . . . . . . . . . . . . . . . . 12 AUDIO MICROCONTROLLER COMMAND SUMMARY . . . 84
First Audio Channel “CODEC” . . . . . . . . . . . . . . . . . . . . 14 POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
DRQ LATCH FEATURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power Management Characteristics . . . . . . . . . . . . . . . 87
FOURTH DRQ CHANNEL . . . . . . . . . . . . . . . . . . . . . . . . . . 15 BIOS Power Management . . . . . . . . . . . . . . . . . . . . . . . 87
INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . 89
PERIPHERAL INTERFACING . . . . . . . . . . . . . . . . . . . . . . . 18 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . 89
DSP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 89
I2S Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Wavetable Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 89
MPU-401 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Power Management Characteristics . . . . . . . . . . . . . . . 90
Game/Joystick Interface . . . . . . . . . . . . . . . . . . . . . . . . 21 ES1879 TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . 91
ES978 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 95
Mono FDXI and FDXO . . . . . . . . . . . . . . . . . . . . . . . . . 25 MECHANICAL DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . 96
General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 APPENDIX A: ES1879 INTERNAL PNP RESOURCE ROM 97
GPI/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 APPENDIX B: ES689/ES69X DIGITAL SERIAL INTERFACE 99
Spatializer 3-D Audio Effects Processor . . . . . . . . . . . . 25 APPENDIX C: I2S ZV INTERFACE REFERENCE . . . . . . . 100
Master Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 APPENDIX D: SCHEMATIC EXAMPLES . . . . . . . . . . . . . . 105
Hardware Volume Controls . . . . . . . . . . . . . . . . . . . . . . 26 APPENDIX E: LAYOUT GUIDELINES . . . . . . . . . . . . . . . . 109
PC Speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 APPENDIX F: ES1879 BILL OF MATERIALS . . . . . . . . . . . 110
Serial EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . 27

ESS Technology, Inc. SAM0025A-062397 3


PRELIMINARY ES1879 DATA SHEET
FIGURES

FIGURES
Figure 1 ES1879 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Figure 21 Compatibility Mode DMA Write Cycle . . . . . . . . . 92
Figure 2 ES1879 Functional Block Diagram . . . . . . . . . . . . . .8 Figure 22 Compatibility Mode DMA Read Cycle . . . . . . . . . 92
Figure 3 ES1879 Mixer Schematic Block Diagram . . . . . . . .10 Figure 23 Serial Mode Receive Operation . . . . . . . . . . . . . . 93
Figure 4 ES1879 Typical Application . . . . . . . . . . . . . . . . . . 11 Figure 24 Serial Mode Transmit Operation . . . . . . . . . . . . . 93
Figure 5 Data Transfer Modes . . . . . . . . . . . . . . . . . . . . . . .12 Figure 25 Serial Input Timing for I2S Interface . . . . . . . . . . . 94
Figure 6 DRQ Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Figure 26 I2S Digital Input Format with 16 SCLK Periods . . 94
Figure 7 DSP Operating Modes . . . . . . . . . . . . . . . . . . . . . .18 Figure 27 ES1879 Physical Dimensions . . . . . . . . . . . . . . . 96
Figure 8 16-Bit Data, Positive Sync Pulse . . . . . . . . . . . . . .19 Figure 28 MIDI Interface Data Format . . . . . . . . . . . . . . . . . 99
Figure 9 I2S Implementation in ES1879 . . . . . . . . . . . . . . . .20 Figure 29 Example ZV Port Implementation . . . . . . . . . . . 100
Figure 10 Dual Joystick/MIDI Connector . . . . . . . . . . . . . . . .21 Figure 30 Typical ZV Port Audio Implementation . . . . . . . 101
Figure 11 MIDI Serial Interface Adapter . . . . . . . . . . . . . . . .22 Figure 31 Audio Interface Timing . . . . . . . . . . . . . . . . . . . . 102
Figure 12 PC Speaker Volume Circuitry . . . . . . . . . . . . . . . .27 Figure 32 I2S Digital Input Format with 16 SCLK Periods . 103
Figure 13 Serial EEPROM – Typical Application . . . . . . . . .27 Figure 33 ES1879 Schematic . . . . . . . . . . . . . . . . . . . . . . 105
Figure 14 Reference Generator Pin Diagram . . . . . . . . . . . .28 Figure 34 PC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 15 Switch-Capacitor Filter Pin Diagram . . . . . . . . . . .28 Figure 35 Amplifier Section . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 16 Configuration Register Outline . . . . . . . . . . . . . . .30 Figure 36 Switch and Connector Section . . . . . . . . . . . . . 108
Figure 17 Command Transfer Timing . . . . . . . . . . . . . . . . . .49 Figure 37 Analog Components on One Side of the PCB . . 109
Figure 18 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Figure 38 Analog Components on Both Sides of the PCB. 109
Figure 19 I/O Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Figure 20 I/O Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . .91

TABLES
Table 1 ES1879 ISA Bus Interface . . . . . . . . . . . . . . . . . . . .12 Table 20 Sound Blaster Pro/Extended Access Registers . . 59
Table 2 ES1879 Interrupt Sources . . . . . . . . . . . . . . . . . . . .16 Table 21 Mixer Input Volume Registers . . . . . . . . . . . . . . . . 61
Table 3 DSP Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . .18 Table 22 SB Pro Read Volume Emulation . . . . . . . . . . . . . . 61
Table 4 Digital Audio Mixing Methods in Serial Mode . . . . . .19 Table 23 SB Pro Write Volume Emulation . . . . . . . . . . . . . . 61
Table 5 I2S Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Table 24 Sound Blaster Pro-Compatible Register Summary 62
Table 6 Wavetable Interface Pins . . . . . . . . . . . . . . . . . . . . .20 Table 25 ESS Mixer Register Summary . . . . . . . . . . . . . . . 63
Table 7 Digital Joystick Read Values . . . . . . . . . . . . . . . . . .21 Table 26 Test Bus Assignments . . . . . . . . . . . . . . . . . . . . . . 78
Table 8 ES978 Interface Pins . . . . . . . . . . . . . . . . . . . . . . . .22 Table 27 ESS Controller Registers Summary . . . . . . . . . . . 79
Table 9 Docked Modes for Analog Audio . . . . . . . . . . . . . . .23 Table 28 Command Summary . . . . . . . . . . . . . . . . . . . . . . . 84
Table 10 Download Period Data Configuration . . . . . . . . . . .24 Table 29 Power Mode Description . . . . . . . . . . . . . . . . . . . . 87
Table 11 Upload Period Data Configuration . . . . . . . . . . . . .25 Table 30 Digital Characteristics . . . . . . . . . . . . . . . . . . . . . . 89
Table 12 Resource Assignment . . . . . . . . . . . . . . . . . . . . . .35 Table 31 Analog Characteristics
Table 13 Logical Device Summary . . . . . . . . . . . . . . . . . . . .36 (VDDA = 5.0 V ± 5%; TA = 25 °C) . . . . . . . . . . . . . . . . . . . . 89
Table 14 I/O Ports for Configuration, Audio, FM, MPU-401, and Table 32 Current Consumption for Power Modes . . . . . . . . 90
Joystick Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Table 33 Common Clock Frequencies . . . . . . . . . . . . . . . . 100
Table 15 Comparison of Operation Modes . . . . . . . . . . . . . .48 Table 34 AC Parameters for Audio Signals . . . . . . . . . . . . 102
Table 16 Uncompressed DAC Transfer Modes . . . . . . . . . . .50 Table 35 ZV Port Interface Pin Assignments . . . . . . . . . . . 104
Table 17 Uncompressed ADC Transfer Modes . . . . . . . . . . .51 Table 36 ES1879 Bill of Materials (BOM) . . . . . . . . . . . . . 110
Table 18 Command Sequences for DMA Playback . . . . . . .53
Table 19 Command Sequences for DMA Record . . . . . . . . .55

4 SAM0025A-062397 ESS Technology, Inc.


ES1879 DATA SHEET PRELIMINARY
PINOUT

PINOUT

DOCKED
RESET

IISCLK

IPROM
I I D ATA

GNDD

GNDA
VDDD

MCLK
SECS

DCLK

MSO
MSD

XSC
XSD
IILR

XA0
XA1
XA2
XA3
MSI
DR
DX
FS
XI
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
XO 76 50 PCSPKO
PCSPKI 77 49 AOUT_R
GNDD 78 48 AOUT_L
GPI0 79 47 LINE_R
DRQD / GPI1 80 46 LINE_ L
GPO0 81 45 CIN_R
GPO1 82 44 CIN_L
SECLK / GPO2 83 43 FOUT_L
DRQC / GPI2 84 42 FOUT_R
DACKBC / GPI3 85 41 VDDA
DRQB 86 40 CAP3D
DACKBB 87 39 GNDA
DRQA
DACKBA
88
89 ES1879S 38
37
MIC
CMR
DACKBD / MUTE / GPI4 90 36 AUXA_R
SEDI / VOLUP / GPI5 91 35 AUXA_L
SEDO / VOLDN / GPI6 92 34 AUXB_R/FDXO
IRQE / GPO6 93 33 AUXB_L/FDXI
IRQD / GPO5 94 32 TA
IRQC / GPO4 95 31 TB
IRQB / GPO3 96 30 TC
IRQA 97 29 TD
IORB 98 28 S WA
IOWB 99 27 SWB
VDDD 100 26 SWC
10

12
13
14
15
16
17
18
19
20
21
22
23
24
25
11
1
2
3
4
5
6
7
8
9
GNDD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A 11

D1
D2
D3
D4
D5
D6
D7
AEN
VDDD
D0

GNDD
SWD

Figure 1 ES1879 Pinout

ESS Technology, Inc. SAM0025A-062397 5


PRELIMINARY ES1879 DATA SHEET
PIN DESCRIPTION

PIN DESCRIPTION
Name Number I/O Description
GNDD 1, 24, 61, 78 I Digital ground.
A[11:0] 13:2 I ISA address bus.
AEN 14 I ISA address valid when active-low, DMA when high.
VDDD 15, 74, 100 I Digital power supply (3.0 - 5.5 V).
D[7:0] 23:16 I/O ISA data bus. 24 mA drivers.
SW(A-D) 28:25 I Joystick switch inputs. These pins have internal pull-ups to VDDD.
T(A-D) 32:29 I/O Joystick timers. Use the digital power supply. These pins have internally weak pull-downs
to GNDD (> 1M Ω).
AUXB_L I Aux B input, left. 50k Ω pull-up to CMR.
33
FDXI I Used with DSP interface as line-level mono input (25k Ω input impedance).
AUXB_R I Aux B input, right. 50k Ω pull-up to CMR.
34
FDXO O Used with DSP interface as line-level mono output, capable of driving a 5k Ω load.
AUXA_L, 35,36 I Aux A (CD) inputs, left and right. 50k Ω pull-ups to CMR.
AUXA_R
CMR 37 O 2.25 V reference buffer output.
MIC 38 I Mic input to +26 dB internal preamp. 80k Ω pull-up to CMR.
GNDA 39, 55 I Analog ground.
CAP3D 40 O Bypass capacitor to GNDA for 3-D effect.
VDDA 41 I Analog power supply, 4.75 - 5.25 V.
FOUT_L, 43:42 O Filter outputs, left and right. These pins are normally AC coupled to CIN_L and CIN_R.
FOUT_R The output resistance is about 5k Ω.
CIN_L, 44, 45 I Capacitive coupled inputs, left and right. The input resistance is about 50k Ω.
CIN_R
LINE_L, 46, 47 I Line inputs, left and right. 50k Ω pull-ups to CMR.
LINE_R
AOUT_L, 48, 49 O Analog outputs, left and right, from master volume. These pins can drive a 5k Ω load.
AOUT_R
PCSPKO 50 O PC speaker analog output.
XA[3:0] 51, 52, 53, 54 I/O Bidirectional differential transmitter/receivers. Expansion audio bus. These are analog sig-
nals that are DC-coupled to the corresponding pins of the ES978.
GNDA 55 I Analog ground.
XSD 56 I/O Expansion serial bus data I/O. High-impedance when DOCKED = 0.
XSC 57 O/Hi Z Expansion serial bus clock and frame sync. High-impedance when DOCKED = 0.
IPROM 58 I Select between internal PnP ROM and external EEPROM for Plug and Play configuration.
1 = internal ROM, 0 = external EEPROM. ES1878 function PNPEN is replaced by bit 2 of
PnP Vendor register 2Dh.
MSO 59 O MIDI serial output.
MSI 60 I MIDI serial input. MSI has an internal pull-up to VDDD.
DX 62 O/Hi Z Serial data transmit. Active output when data is being transmitted serially from the
ES1879; otherwise, high impedance. Tri-state output.
DR 63 I Serial data receive. This pin has an internal pull-down to GNDD.
DCLK 64 I Serial clock input. This pin has an internal pull-down to GNDD.
FS 65 I Frame sync input. Software-programmable to be active-high or active-low. This pin has
an internal pull-down to GNDD.
MCLK 66 I Serial clock input from ES689/ES69x. This pin has an internal pull-down to GNDD.
MSD 67 I Serial data input from ES689/ES69x. This pin has an internal pull-down to GNDD.
IIDATA 68 I Serial data for I2S interface. This pin has an internal pull-down to GNDD.
IISCLK 69 I Serial shift clock for I2S interface. This pin has an internal pull-down to GNDD. I2S
IILR 70 I Left/right signal for I2S interface. This pin has an internal pull-down to GNDD.

6 SAM0025A-062397 ESS Technology, Inc.


ES1879 DATA SHEET PRELIMINARY
PIN DESCRIPTION

Name Number I/O Description


SECS 71 I Serial EEPROM CS. This pin is an input during reset when IRPOM = 1. It is No-Connect
when IRPOM = 0.
IRPOM SECS ROM Type
0 1 93LC66, 512×8, 9 address bits.
1 x Internal mask ROM.
DOCKED 72 I Status input that is active-high when the ES1879 is docked to the ES978. This pin has an
internal pull-down to GNDD.
RESET 73 I ISA active-high reset.
XI 75 I 14.31818 MHz clock input, or external crystal.
XO 76 O Output to external 14.31818 MHz crystal.
PCSPKI 77 I PC speaker digital input. This pin has an internal pull-down.
GPI0 79 I General-purpose input 0.
DRQD O/Hi Z ISA active-high DMA request.
80
GPI1 I General-purpose input 1.
GPO[1:0] 82:81 O General-purpose outputs.
GPO2 O General-purpose outputs when SECS = 0.
83
SECLK I External serial EEPROM clock pin for PnP when SECS = 1.
DRQC O/Hi Z ISA active-high DMA request.
84
GPI2 I General-purpose input 2.
DACKBC I ISA active-low DMA acknowledge.
85
GPI3 I General-purpose input 3.
DRQB 86 O/Hi Z ISA active-high DMA request.
DACKBB 87 I ISA active-low DMA acknowledge.
DRQA 88 O/Hi Z ISA active-high DMA request.
DACKBA 89 I ISA active-low DMA acknowledge.
DACKBD I ISA active-low DMA acknowledge.
MUTE 90 I Active-low mute input. This pin has an internal pull-up to VDDD.
GPI4 I Optionally used as general-purpose input 4.
SEDI I Data input pin to external PnP serial EEPROM when SECS = 1.
VOLUP 91 I Active-low volume-up input. This pin has an internal pull-up to VDDD.
GPI5 I Optionally used as general-purpose input 5.
SEDO O Data output pin to external PnP serial EEPROM when SECS = 1.
VOLDN 92 I Active-low volume-down input. This pin has an internal pull-up to VDDD.
GPI6 I Optionally used as general-purpose input 6.
IRQE O/Hi Z ISA interrupt request. 16 mA driver.
93
GPO6 O General-purpose output 6.
IRQD O/Hi Z ISA interrupt request. 16 mA driver.
94
GPO5 O General-purpose output 5.
IRQC O/Hi Z ISA interrupt request. 16 mA driver.
95
GPO4 O General-purpose output 4.
IRQB O/Hi Z ISA interrupt request. 16 mA driver.
96
GPO3 O General-purpose output 3.
IRQA 97 O/Hi Z ISA interrupt request. 16 mA driver.
IORB 98 I ISA active-low read strobe.
IOWB 99 O ISA active-low write strobe.

ESS Technology, Inc. SAM0025A-062397 7


PRELIMINARY ES1879 DATA SHEET
FUNCTIONAL DESCRIPTION

FUNCTIONAL DESCRIPTION
This section shows the overall structure of the ES1879 The major subunits of the ES1879 are shown in Figure 2
and discusses its major functional subunits. and are briefly described in the following paragraphs.

GNDD VDDD CIN FOUT GPI[6:0]* GPO[6:0]* PCSPKI

VOL CTRL

PREAMP
MIC GENERAL 1-BIT
FILTER PURPOSE I/O
PCSPKO
LINE DAC

AUXA
AUXB*
FDXI/O* A[11:0]
D[7:0]
16-BIT
STEREO FIFO IRQ(A-E)*
DAC ISA DRQ(A-D)*
GNDA
BUS
DACKB(A-D)*
INTERFACE
RECORD IOWB
VDDA MIXER RECORD AND
SOURCE REGISTER
AND SET IORB
16-BIT
VOLUME
PLAYBACK CONTROL STEREO FIFO RESET
MIXER
CODEC
AEN
IPROM

CAP3D 3-D
ROM
MICROCONTROLLER DX
ES978 RAM
DSP
DR
XA[3:0] ANALOG
SERIAL
I/F ™
FS
ESFM PORT
DCLK

16-BIT DOCKED
16-BIT ES978
STEREO DAC
AOUT STEREO DAC DIGITAL XSC
I/F XSD
VOLUP* ES689/ES69x MPU-401 DUAL GAME
MASTER SERIAL PORT SERIAL PORT SERIAL PORT
I2S ZV OSCILLATOR REF GEN
VOLDN* VOL
SERIAL PORT
CTRL
MUTE*

IILR IISCLK IIDATA XI XO MSD MCLK MSI MSO SW(A-D) T(A-D) CMR
* Some of these pins are shared with other functions.

Figure 2 ES1879 Functional Block Diagram

Digital Subsystems ‡ ES978 digital interface – allows support for ES978


‡ RISC microcontroller – game-compatible audio Expansion Audio Mixer in the docking station. Two wires
functions are performed by an embedded microcontroller. transmit and receive control signals and a thrid wire
reports the docking status.
‡ Oscillator – circuitry to support an external crystal.
‡ I2S Zoom Video serial port – supports sample rates up
‡ ROM and RAM – firmware ROM and data RAM to the to 48 kHz for MPEG audio.
embedded microcontroller.
‡ MPU-401 serial port – asynchronous serial port for MIDI
‡ FIFO – RAM for a 256-byte FIFO data buffer for use with devices such as a wavetable synthesizer or a music
the first audio channel and RAM for a 64-byte FIFO for keyboard input.
use with the second audio channel.
‡ Wavetable serial port – serial port connection from the
‡ ISA bus interface – provides interface to ISA bus output of an ES689 or ES69x that eliminates the need for
address, data, and control signals. an external DAC.
‡ Digital dual game port – ESS high-performance digital ‡ DSP serial port – interface for an optional external DSP
switches for two joysticks with hardware timing. for control of the CODEC.

8 SAM0025A-062397 ESS Technology, Inc.


ES1879 DATA SHEET PRELIMINARY
FUNCTIONAL DESCRIPTION

‡ ESFM™ music synthesizer – high-quality OPL3 ‡ Recording source and input volume control – input
superset FM synthesizer. source and volume control for record. The recording
‡ 3-D Processor – Spatializer technology 3-D audio effects source can be selected from one of seven choices:
processor. – Mic
‡ Hardware volume control – three pushbutton inputs – Line
with internal pull-up devices for up/down/mute can be – Aux A (CD)
used to adjust the master volume control. – Record Mixer
The state of these pins is logically AND’d with the state – Playback Mixer – master volume inputs (outputs of
of the corresponding pins of the ES978 when docked. the Spatializer processor, but before master volume
A software-selectable option allows the mute input to is applied).
be omitted. The mute input is defined as the state when
both up and down inputs are low. By default, this – Playback Mixer – AOUT_L/AOUT_R (after master
feature is disabled. volume has been applied).
– Mic/master volume inputs mix. Left channel: Mic
The hardware volume inputs of the ES1879 can be (not mixed with ES978 mic), Right channel: master
used as general-purpose inputs (see bits 4 and 5 of volume inputs left and right.
Vendor-Defined Card-Level register 25h). They cannot
be used as volume control inputs. In any of the first four cases, the selected recording
source may be mixed with audio from the ES978 if the
Analog Subsystems selected source is also enabled in the ES978 and the
two chips are docked.
‡ Stereo programmable record and playback mixers –
seven input stereo mixers. Each input has independent ‡ Master volume and mute control – the master volume
left and right 4-bit volume control. is controlled by either Programmed I/O or volume control
switch inputs. The master volume supports 6 bits per
– Line In
channel plus mute. When docked, the ES1879 first
– Mic In transmits the master volume information to the ES978
– Aux A (CD) mixer before it can take effect.
– Aux B (or FDXI) ‡ ES978 analog interface – allows support for ES978
– Digital audio (wave files) Expansion Audio Mixer in the docking station. The four-
– FM/ES689/ES69x music DAC wire differential analog bus carries audio data between
the ES978 and the ES1879. Audio data from the ES978
– I2S serial port DAC is input to the mixer of the ES1879. A switch determines
‡ 16-Bit stereo CODEC – for audio record and playback whether audio data transmitted to the ES978 is taken
CODEC. before or after master volume is applied.
‡ 16-Bit stereo system DAC – for audio playback of the ‡ Reference generator – analog reference voltage
second audio channel. generator.
‡ 16-Bit stereo music DAC – for ESFM™ or external ‡ PC speaker volume control – the PC speaker is
wavetable synthesizer. supported with a 1-bit DAC with volume control. The
‡ 16-Bit Stereo I S DAC – I S Zoom Video for MPEG audio
2 2 analog output pin PCSPKO is intended to be externally
DAC. mixed at the external amplifier. PC speaker audio is not
transmitted to the ES978 through the expansion audio
‡ 1-Bit DAC – for PC speaker digital input. interface (XA[3:0]). The ES1879 is designed to play PC
speaker audio through the speakers inherent to the
portable unit.
‡ General-purpose I/O – Seven general-purpose inputs
and outputs which can be slaved with the corresponding
pins of the ES978 Expansion Audio Mixer.
‡ Filter – switched capacitor low-pass filter.
‡ Preamp – 26 dB microphone preamplifier.

ESS Technology, Inc. SAM0025A-062397 9


PRELIMINARY ES1879 DATA SHEET
MIXER SCHEMATIC BLOCK DIAGRAM

MIXER SCHEMATIC BLOCK DIAGRAM

ADC/DAC Output
Volume
DMA 1
digital audio

DAC
DMA 2
digital audio
DAC
I2S/ZV
I2S/ZV
MPEG audio
Preamp
MIC
Playback Spatializer
LINE Mixer 3-D
DOCKED
DAC
On
FM/ ES978
HWWT Off

AUXA Record
Monitor
AUXB Off
Record
Source AOUT
ES978 Σ On Master
Mute Volume
ES978
Volume Σ
Record
Input Volume
Volume
ADC

Record
Mixer

Mute

Figure 3 ES1879 Mixer Schematic Block Diagram

10 SAM0025A-062397 ESS Technology, Inc.


ES1879 DATA SHEET PRELIMINARY
TYPICAL APPLICATION

TYPICAL APPLICATION

ES1879
ISA BUS

ISA Bus AOUT


Interface Stereo
L R
Speakers

DSP
Serial 3-D 1-Mbyte
ES981 Wavetable
Port Processor ROM

2 or 3
Buttons Hardware 2 MIDI General Wavetable
MPU-401 Serial Port MIDI Synthesizer
Volume Interpreter
Up, Down,
Control
and Mute
2 Chorus &
Wavetable Serial
Reverb
Joystick Port
Audio Port (ES69x only)
Controls
ES689/ES69X

CD (stereo) MPEG Audio


Aux B (stereo) I2S ZV 3 (I2S ZV)
Line (stereo) Interface
Mic (mono) PC CARD
OPTIONAL
GPI/O

ES978 DOCKING UNIT


Interface

I2S ZV Port or ES689/ES69x


Wavetable Serial Port ES978 L R
Speakers

Oversampling
Stereo DAC
Record
2 & Analog CD (stereo)
Differential
Transceiver Playback I/O Aux B (stereo)
Mixers Line (stereo)
4 Digital
Controller Mic (mono)

PORTABLE UNIT
MIDI GPI/O 2 or 3
Buttons
Volume Control Up, Down,
Joysticks and Mute

Figure 4 ES1879 Typical Application

ESS Technology, Inc. SAM0025A-062397 11


PRELIMINARY ES1879 DATA SHEET
ISA BUS INTERFACE

ISA BUS INTERFACE


Table 1 shows the pins used to interface the ES1879 with the ISA bus.
Table 1 ES1879 ISA Bus Interface
Pin I/O Description
A[11:0] I ISA address bus.
AEN I ISA address valid when active-low, DMA when high.
D[7:0] I/O ISA data bus. 24 mA drivers.
IOWB O ISA active-low write strobe.
IORB I ISA active-low read strobe.
IRQ(A-E) O/Hi Z ISA interrupt request. 16 mA driver.
DACKB(A-D) I ISA active-low DMA acknowledge.
DRQ(A-D) O/Hi Z ISA active-high DMA request.
RESET I ISA active-high reset.

DIGITAL AUDIO
The ES1879 incorporates two audio channels: Programming Data Transfers
Audio 1 The first audio channel. This channel is used for Programming Data transfers can be quite complicated
Sound Blaster Pro-compatible DMA, Extended with the ES1879. Both Compatibility mode and Extended
mode DMA, and Programmed I/O. It can be mode offer a variety of modes for conducting transfers.
used for either record or playback. This channel The commands to enable the different transfers varies
can be mapped to any of the three 8-bit ISA depending on which audio channel is used and which
DMA channels: 0, 1, or 3. mode (Compatibility or Extended) is used.
Audio 2 The second audio channel. This channel is used The biggest difference in available data transfer modes is
for audio playback in full-duplex mode. This between audio channel 1 and audio channel 2. This is
channel can be mapped to any of the three 8-bit illustrated in Figure 5. Audio 2 allows only for DMA mode.
ISA DMA channels or the 16-bit channel. Audio 1 allows for Direct mode and DMA mode when
The two DMA sources are mapped to the four DMA pin using Compatibility mode. Audio 1 allows for Programmed
pairs through PnP registers. Also, the four DMA pin pairs I/O and DMA mode when using Extended mode.
are assigned ISA DMA channel numbers by Vendor-
Defined Card-Level registers 23h and 24h.
Digital Audio
In order for a DRQ output pin to be driving (as opposed to
high-impedance), two things must occur:
Audio 1 Audio 2
1. The PnP register for the DMA of a given device
must match the ISA DMA channel number of the
Compatibility Extended
pin. Mode Mode
2. The given device must be activated (that is, bit 0 of
PnP register 30h must be high).
Direct DMA Programmed DMA DMA
For detailed information, see “PnP Configuration and Mode Mode I/O Mode Mode
Registers” .
Figure 5 Data Transfer Modes Data Formats
See “Data Formats” on page 48.

12 SAM0025A-062397 ESS Technology, Inc.


ES1879 DATA SHEET PRELIMINARY
DIGITAL AUDIO

Data Transfers in Compatibility Mode Normal DMA Mode


The first audio channel can be programmed using the In Normal mode DMA transfers, the DMA controller must
standard Sound Blaster-compatible commands. These be initialized and the ES1879 must be commanded for
commands are written to the chip through port every block that is transferred.
Audio_Base+Ch.
Auto-Initialize DMA Mode
When programming the first audio channel for
Compatibilty mode transfers one of the following modes In Auto-Initialize mode, the DMA transfer is continuous, in
can be used: a circular buffer, and the ES1879 generates an interrupt
for the transition between buffer halves. In this mode, the
‡ Direct Mode DMA controller and ES1879 need to be set up only once.
‡ DMA Mode High-Speed Mode
– Normal
The ES1879 supports mono 8-bit DMA transfers at a rate
– Auto-Initialize of up to 44 kHz. Mono 16-bit transfers are supported up to
In addition, both Normal DMA mode and Auto-Initialize a rate of 22 kHz.
DMA mode can use a special High-Speed mode.
There is a special High-Speed mode” that allows 8-bit
Direct Mode sampling up to 44 kHz for ADC. This mode uses
In Direct mode, the timing for DMA transfers is handled by commands 98h (Auto-Initialization) and 99h (Normal). No
the application program. For example, the system timer automatic gain control (AGC) is performed. The input
can be reprogrammed to generate interrupts at the volume is controlled with command DDh.
desired sample rate. At each system timer interrupt, the
Data Transfers in Extended Mode
command 10h, 11h, 20h, or 21h is issued, followed by the
sample. Polling of the write buffer available flag The first audio channel is programmed using the controller
(Audio_Base+Ch [bit 7]) is required before writing the registers internal to the ES1879. The commands written to
command and between the command and the data. the controller registers are written to the chip through port
Audio_Base+Ch.
NOTE: The switched capacitor filter is initialized by reset
for an intended sample rate of 8 kHz. In Direct mode, the When programming the first audio channel for transfers,
application may try to adjust this filter appropriate to the one of the following modes can be used:
actual sample rate. The easiest way to do this is to
program the timer with command 40h just as if the ‡ Programmed I/O
application were using DMA mode. ‡ DMA mode:
DMA Mode – Normal (Single or Demand transfer)
In DMA mode, the programmable timer in the ES1879 – Auto-Initialize (Single or Demand transfer)
controls the rate at which samples are sent to the CODEC. In addition, both DMA Normal mode and DMA Auto-
The timer is programmed using command 40h, which also Initialize mode use Single transfer or Demand transfer
sets up the programmable filters inside the ES1879. The mode.
ES1879 firmware maintains an internal FIFO (32 levels for
16-bit transfers, 64 levels for 8-bit transfers) that is filled by Programmed I/O
DMA transfers and emptied by the timed transfers to the For some applications, DMA mode is not suitable or
DAC. available for data transfer, and it is not possible to take
exclusive control of the system for DAC and ADC
Before a DMA transfer, the application first programs the
transfers. In these situations, use I/O block transfers within
DMA controller for the desired transfer size and address,
an interrupt handler. The REP OUTSB instruction of the
then programs the ES1879 with the same size
80x86 family transfers data from memory to an I/O port
information. At the end of the transfer, the ES1879
specified by the DX register. The REP INSB instruction is
generates an interrupt request, indicating that the current
the complementary function. Use ES1879 port
block transfer is complete. The FIFO gives the application
Audio_Base+Fh for block transfers.
program sufficient time to respond to the interrupt and
initiate the next block transfer. I/O transfers to FIFO are nearly identical to the DMA
process, except that an I/O access to port
The ES1879 supports both Normal DMA mode and Auto-
Audio_Base+Fh replaces the DMA cycle. For details
Initialize DMA mode.
about Programmed I/O, operation see “Extended Mode
Programmed I/O Operation” on page 55.

ESS Technology, Inc. SAM0025A-062397 13


PRELIMINARY ES1879 DATA SHEET
DIGITAL AUDIO

DMA Mode Using Single transfer, one byte is transferred per DMA
Extended mode DMA supports both Normal and Auto- request. Demand transfer reduces the number of DMA
Initialize mode. In addition, Normal mode and Auto- requests necessary to make a transfer by allowing two,
Initialize mode both support Single and Demand transfer four, or eight bytes to be transferred per DMA request.
modes. Thus there are multiple DMA acknowledges for each DMA
request.
Using Single transfer, one byte is transferred per DMA
request. Demand transfer reduces the number of DMA For a description of DMA mode including Normal DMA
requests necessary to make a transfer by allowing two or mode and Auto-Initialize DMA mode, see “DMA Mode” on
four bytes to be transferred per DMA request. Thus there page 13.
are multiple DMA acknowledges for each DMA request. Audio 2 Related Mixer Registers
For a description of DMA mode including Normal DMA The following registers control DMA operations for the
mode and Auto-Initialize DMA mode see “DMA Mode” on second audio channel:
page 13.
Address Name
Extended Mode Audio 1 Controller Registers
70h Audio 2 Sample Rate Generator register
The following registers control operation of the first audio
channel in Extended mode: 72h Audio 2 Filter Clock Divider register
74h Audio 2 Transfer Count Reload register – low byte
Address Name
76h Audio 2 Transfer Count Reload register – high byte
A1h Audio 1 Sample Rate Generator register
A2h Audio 1 Filter Clock Divider register 78h Audio 2 Control 1 register
A4h Audio 1 Transfer Count Reload register – low byte 7Ah Audio 2 Control 2 register
A5h Audio 1 Transfer Count Reload register – high byte
B1h Audio Interrupt Control register First Audio Channel “CODEC”
B2h Audio 1 DRQ Control register The CODEC of the first audio channel is not a true stereo
B4h Input Volume Control register CODEC in that it cannot perform stereo DAC and ADC
B5h Audio 1 DAC Direct Access register – low byte simultaneously. The first audio channel CODEC can be
B6h Audio 1 DAC Direct Access register – high byte either a stereo DAC, a stereo ADC, or a mono CODEC.
B7h Audio 1 Control 1 register After reset, the CODEC is set up for DAC operations. Any
B8h Audio 1 Control 2 register ADC command causes a switch to the ADC “direction” and
B9h Audio 1 Transfer Type register any subsequent DAC command switches the converter
back to the DAC “direction.”
Data Transfers Using the Second Audio Channel The DAC output is filtered and input to the mixer. After
The second audio channel is programmed using mixer reset, input to the mixer from the first audio channel DAC
registers 70h through 7Ah. The commands written to the is muted. This is to prevent pops. The ES1879 maintains
mixer registers are written to the chip through ports a status flag to determine if the input to the mixer from the
Audio_Base+4h and Audio_Base+5h. first audio channel DAC is enabled or disabled. The
command D8h returns the status of the flag (00h =
DMA mode is used when programming the second audio disabled and FFh = enabled). Use command D1h to
channel for transfers: enable input to the mixer from the first audio channel DAC
DMA mode: and command D3h to disable the input.
– Normal (Single or Demand transfer) To play a new sound without resetting beforehand when
– Auto-Initialize (Single or Demand transfer) the status of the analog circuits is not clear, mute the input
to the mixer with command D3h, then set up DAC direction
In addition, both DMA Normal mode and DMA Auto- and level using the direct-to-DAC command:
Initialize mode use Single transfer or Demand transfer
modes. 10h + 80h
DMA Mode Wait 25 msec for the analog circuitry to settle before
DMA under the second audio channel supports both enabling the input to the mixer with command D1h.
Normal and Auto-Initialize modes. In addition, Normal
mode and Auto-Initialize mode both support Single and
Demand transfer modes.

14 SAM0025A-062397 ESS Technology, Inc.


ES1879 DATA SHEET PRELIMINARY
DRQ LATCH FEATURE

A pop may be heard if the DAC level was left at a value FOURTH DRQ CHANNEL
other than mid-level (code 80h on an 8-bit scale) by the
previous play operation. To prevent this, always finish a The ES1879 supports an optional fourth DMA channel
DAC transfer with a command to set the DAC level to mid- using pins DRQD and DACKBD. Connecting these pins to
range: an ISA DMA channel is optional.

10h + 80h If DRQD and DACKBD are not connected to an ISA DMA
channel, program bits 7:4 of PnP Vendor register 24h to be
2h (0010). In this case, pin 80 is available as GPI1
DRQ LATCH FEATURE (general-purpose input 1) and pin 90 is available as either
The DRQ latch feature is enabled when bit 7 of Vendor- the active-low hardware volume control MUTE input or as
Defined Card-Level register 29h is high (see Figure 6). GPI4 (general-purpose input 4).

If this feature is enabled, each of the four audio DRQs will If bits 7:4 of PnP Vendor register 24h are other than 2h,
be latched high until one of the following occurs: then pin 80 is assumed to be connected to an ISA DRQ pin
and is not available as GPI1 (if GPI1 is read, it appears to
‡ A DACK low pulse occurs while DRQ is low or if DRQ be 1 all the time). Likewise, pin 90 is assumed to be
goes low due to a DACK pulse. connected to an ISA DACK pin and is not available to be
‡ A hardware reset occurs. used as a hardware volume MUTE input or GPI4. If a mute
‡ 8-16 milliseconds elapse while DRQ is low. function is desired, program mixer register 64h so that the
combination of both VOLUP and VOLDN pins low together
acts as a mute command.
Normally, DRQA/DACKBA is connected to DMA channel
DRQ
0, DRQB/DACKBB is connected to DMA channel 1, and
S S DRQ Out DRQC/DACKBC is connected to DMA channel 3. This
125 Hz leaves one of the three 16-bit channels for DRQD/
R R DACKBD. Since the ES1879 only has 8 data lines, the
Windows driver will arrange the data so that a 16-bit
-DACK OR
AND channel can be used for 8-bit data. For this reason, the
DRQD/DACKBD channel should only be used for the
-RESET second DAC playback channel and not the game-
compatible first channel.
Figure 6 DRQ Latch
The DRQ latch feature is enabled when bit 7 of Vendor-
Defined Card-Level register 29h is high (see Figure 6).

ESS Technology, Inc. SAM0025A-062397 15


PRELIMINARY ES1879 DATA SHEET
INTERRUPTS

INTERRUPTS
There are four interrupt sources in the ES1879:
Table 2 ES1879 Interrupt Sources
Interrupt Source Description
Audio 1 This interrupt is used for the first audio channel (Sound Blaster-compatible DMA, Extended mode DMA, and
Extended mode Programmed I/O), as well as SB-compatible (Sound Blaster-compatible) MIDI receive. This
interrupt request is cleared by a hardware or software reset, or by an I/O read from Audio_Base+Eh. The
interrupt request can be polled by reading from Audio_Base+Ch. This interrupt is assigned to an interrupt
channel by PnP register 70h of LDN 1 (Logical Device Number 1).
Audio 2 Optional for the second DMA channel. The ES1879 can operate in full-duplex mode using two DMA channels.
However, the second DMA channel must have the same sample rate as the first DMA channel. For this rea-
son, it is not necessary to use a separate interrupt for the second DMA channel. This interrupt is masked by
bit 6 of mixer register 7Ah. It can be polled and cleared by reading or writing bit 7 of the same register. This
interrupt is assigned to an interrupt channel by PnP register 72h of LDN 1.
Hardware Volume This interrupt occurs when one of the three hardware volume controls generates an event. Bit 1 of mixer reg-
ister 64h is the mask bit for this interrupt. The interrupt request can be polled by reading bit 3 of the
same register. The interrupt request is cleared by writing any value to register 66h. This interrupt is
assigned to an interrupt channel by PnP register 28h. Typically this interrupt, if used, is shared with
an audio interrupt.
MPU-401 This interrupt occurs when a MIDI byte is received. It will go low when a byte is read from the MIDI FIFO and
go high again quickly if there are additional bytes in the FIFO. The interrupt status is the same as the Read
Data Available status flag in the MPU-401 Status register. This interrupt is masked by bit 6 of mixer reg-
ister 64h and is assigned to an interrupt channel in one of two ways: If the MPU-401 is part of the
audio device, then PnP register 28h is used to assign the MPU-401 interrupt. If the MPU-401 is its
own logical device, it can also be assigned to an interrupt via PnP register 70h of LDN 3. Both of
these methods access the same physical register.

Interrupt Sources Bit 1 Audio 2 interrupt request AND’d with bit 6 of


Interrupt sources are mapped to any one of the five Mixer Extension register 7Ah
interrupt output pins via the PnP registers. A given pin can Bit 0 Audio 1 interrupt request
have zero, one, or more interrupts mapped to it. Each PnP
pin is assigned to an ISA interrupt channel number by Interrupt Mask Register (IMR)
Vendor-Defined Card-Level PnP registers 20h, 21h, and Register 7h of the configuration device can be used to
22h. These registers are automatically loaded from the 8- mask any of the four interrupt sources.
byte header in the PnP configuration data. The mask bits can be used to force the interrupt source to
If a given interrupt pin has one or more sources assigned be zero, but they do not put the interrupt pin in a high-
to it, and one or more of those sources is activated impedance state. Each bit is AND’d with the
(register 30h, bit 0), then the interrupt pin will be active; corresponding interrupt source. This port is set to all ones
that is, it will always be driving high or low. Each interrupt on a hardware reset.
also has one or more mask bits that are AND'd with the The Interrupt Status Register (ISR) is not affected by the
interrupt request. state of the Interrupt Mask Register (IMR). That is, the ISR
Interrupt Status Register (ISR) reflects the status of the interrupt request lines before
being masked by the IMR.
Port Config_Base+6h of the configuration device can be
read to quickly find the current state of ES1879 interrupt The IMR is useful when interrupts are shared. For
sources. The following bits describe the state of the example, assume that audio 1, audio 2, hardware volume,
ES1879 interrupt sources: and MPU-401 all share the same interrupt in Windows.
When returning from Windows to DOS, the hardware
Bit 3 MPU-401 receive interrupt request AND’d
volume, MPU-401, and Audio 2 interrupts can be masked
with bit 6 of mixer register 64h
by setting the appropriate bits to 0.
Bit 2 Hardware volume interrupt request AND’d
with bit 1 of mixer register 64h

16 SAM0025A-062397 ESS Technology, Inc.


ES1879 DATA SHEET PRELIMINARY
INTERRUPTS

A second use of the IMR is within an interrupt handler. The


first thing the interrupt handler can do is mask all of the
interrupt sources mapped to the interrupt handler. The ISR
can then be polled to decide which sources to process.
Just before exiting the interrupt handler, the IMR can be
restored. If an unprocessed interrupt remains active, it
generates an interrupt request because the interrupt pin
was low during the masked period and then went high
when the interrupt sources were unmasked. While the
interrupts are masked, the individual interrupt sources can
change state any number of times without generating a
false interrupt request.

Interrupt Edge Generator


The interrupt logic has a feature that makes sharing of
interrupts easier. If more than one interrupt source shares
an interrupt request pin, the interrupt pin is normally the
logical OR of the shared interrupt requests. However, if
any one interrupt request goes from high to low, circuitry
inside the ES1879 will hold the interrupt request pin low
briefly to generate a clock edge if one of the other interrupt
sources is also high.

Sharing Interrupts
Plug and Play does not support sharing of interrupts in its
resource assignment decision making. If a device tries to
share an interrupt with another device that has been
assigned an interrupt by PnP, the first device cannot
request an interrupt for itself.
A logical device that supports interrupts can be assigned
to an interrupt after the PnP sequence is generated by the
Windows driver. In this case, the logical device would
typically be forced to share an interrupt with the first audio
interrupt. For most cases, this is done simply by
programming the appropriate PnP register (70h or 72h) for
the selected device.
A special case is the hardware volume interrupt. This
interrupt source can be assigned to an interrupt through
Vendor-Defined Card-Level register 28h, bits 7:4.
A second special case is the MPU-401 interrupt. The
MPU-401 device is either part of the audio device or its
own logical device. If it is part of the audio device, the
interrupt can be assigned by writing to Vendor-Defined
Card-Level register 28h, bits 3:0. If the MPU-401 device is
its own logical device, it is assigned an interrupt by either
Vendor-Defined Card-Level register 28h or LDN 3 register
70h.

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PERIPHERAL INTERFACING
DSP Interface Telegaming Mode
The ES1879 contains a synchronous serial interface for This mode is enabled when two conditions are present:
connection to a DSP serial interface. The typical ‡ The DSP serial port must be enabled (i.e., bit 7 of Mixer
application for this interface is a speakerphone. register 48h is high).
Table 3 DSP Interface Pins ‡ Bit 0 of mixer register 48h is high. This bit enables
Telegaming mode.
Pin Description
In earlier chips, when the DSP serial port is enabled, the
DCLK Data clock input. The rate can vary, but a typical
Audio 1 CODEC is unavailable for use by the first audio
value is 2.048 MHz (8 kHz x 256). Input with pull-
down. channel. This means digital audio for Sound Blaster Pro-
compatible games is muted. Sound Blaster can use only
DX Data transmit. Active output when data is being
the first audio channel for digital audio. The Audio 1
transmitted serially from the ES1879; otherwise,
CODEC is used by the DSP.
high impedance. Tri-state output.
DR Serial data input with pull-down. In Telegaming mode, the first audio channel can be
switched over to the Audio 2 DAC. Internally, the first audio
FS Frame sync input for transmit. Software-program-
mable to be active-high or active-low. Input with channel is routed to the second audio channel DAC and
pull-down. the second audio channel has no function. In addition, the
second audio channel mixer volume control is slaved to
the first audio channel mixer volume control.
DSP Operating Modes Default Mode
There are two DSP data transfer modes for the ES1879. The default mode operates just like telegaming mode
The state of a single switch internal to the ES1879 except that data from the first audio channel cannot be
determines which mode is enabled. This switch can route heard. Data sent through the second audio channel can be
the first audio channel to the second audio channel DAC. mixed as in Telegaming mode.
When the first audio channel is routed to the second audio
channel DAC, Telegaming mode is enabled. Otherwise, No Acoustic Echo Cancellation
the DSP is operating in its default mode. The DSP cannot perform acoustic echo cancellation in
either mode. Because the audio from the host does not
pass directly through the DSP, there is no way for the DSP
to compensate for acoustic echo. Therefore, using a
headset for either the microphone or speakers or both is
recommended.

16-bit Stereo DAC 16-bit Stereo DAC


DAC DAC
DMA2 DAC
DMA2 DAC
FIFO FIFO
ISA 16-bit Stereo ISA 16-bit Stereo
Bus CODEC Bus CODEC
DAC DAC
DMA1 ADC DMA1 ADC
FIFO Microphone FIFO Microphone
DAC FDXO DAC FDXO
ADC ADC

Serializer/ Serializer/
Mixer Speaker Mixer Speaker
Deserializer Deserializer

DSP/CODEC DSP/CODEC
Port Port

Telegaming Mode Default Mode


Figure 7 DSP Operating Modes

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DSP Digital Audio Playback Mixing External to the ES1879


There are two choices for mixing the DSP digital audio The second method is to use the FDXO output pin and mix
playback data with other audio sources. The audio data the DSP digital audio playback and the game-compatible
can be mixed in the ES1879’s internal playback mixer or digital audio playback in an external audio mixer. To select
external to the ES1879. this method, set the Output Signal Control bits of Mixer
Mixing Internal to the ES1879 register 44h for mixer output except DAC playback. To do
this, program bits 6:4 of register 44h to 1, 0, and 1,
The DSP digital audio playback can be mixed within the respectively. In addition, set bit 1 of Mixer register 46h high
ES1879 playback mixer. To select this method, set the to enable FDXO as an output when DSP serial mode is
Output Signal Control bits of the Mixer register 44h for enabled.
mixer output. To do this, program bits 6:4 of mixer register
44h to 1, 0, and 0, respectively. The volume of the DSP The volume of the DSP digital audio playback is controlled
digital audio playback is controlled by the DAC Play within the DSP by scaling the data.
Volume register 14h.
NOTE: In Telegaming mode, register 14h also controls
the game-compatible first audio channel digital audio
playback. If independent mixer volume control of the
game-compatible and DSP digital audio data is
necessary, use the second method.
Table 4 Digital Audio Mixing Methods in Serial Mode
...set the Output Signal
Control bits of register ...and the volume of the DSP
To mix DSP and digital
44h to... digital audio playback is In addition...
audio...
controlled by...
Bit 6 Bit 5 Bit 4
internal to the ES1879 1 0 0 DAC Play Volume register 14h N/A
external to the ES1879 1 0 1 scaling the data within the DSP set bit 1 of register 46h high.

DSP Interface Serial Data Format

DCLK

FS

Hi-Z
DX D15 D14 D13 D12 D1 D0
(MSB)

DR D15 D14 D13 D12 D1 D0

(MSB)

Figure 8 16-Bit Data, Positive Sync Pulse

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I2S Serial Interface I2S Serial Interface Timing


Three input pins, IIDATA, IISCLK, and IILR, are used for a This section discusses the I2S serial interface signals. The
serial interface between an external device and a stereo signals when the port is configured for use with an ES689/
DAC within the ES1879. IIDATA, IISCLK, and IILR can be ES69x wavetable synthesizer are defined in the
left floating or connected to ground if the serial interface is Wavetable Interface section.
not used. Three signals (plus one optional) are used for I2S:
2
A typical applications of the I S serial interface is MPEG IISCLK The shift clock. The maximum rate is 6.4 MHz.
audio or CD audio. The minimum number of IISCLK periods per
IILR period is 32. Any number greater than or
equal to 32 is acceptable.
IILR Sample synchronization signal. The maximum
IIDATA
sample rate is 50 kHz.
PC CARD IISCLK IIDATA Serial data.
IILR Within the ES1879, IILR and IIDATA are sampled on the
rising edge of IISCLK. See Figure 25 and Figure 26 for
ES1879 detailed I2S timing.

Figure 9 I2S Implementation in ES1879 Wavetable Interface


.
The ES1879 contains a synchronous serial interface for
connection to a wavetable music synthesizer.
Table 5 I2S Interface Pins
Table 6 Wavetable Interface Pins
Pin Description
Pin Description
IIDATA Serial data for I2S interface. This pin has an inter-
nal pull-down to GNDD. MCLK Serial clock from external ES689/ES69x music
synthesizer (2.75 MHz). Input with pull-down.
IISCLK Serial shift clock for I2S interface. This pin has an
internal pull-down to GNDD. MSD Serial data from external ES689/ES69x music
synthesizer. When both MCLK and MSD are
IILR Left/Right signal for I S interface. This pin has an
2
active, the stereo DACs normally used by the FM
internal pull-down to GNDD. synthesizer are acquired for use by the external
ES689/ES69x. The normal FM output is blocked.
Input with pull-down.
I2S Serial Interface Software Enable
By hardware reset default, the I2S interface is disabled. Bit
6 of Vendor-Defined Card-Level register 29h enables the MPU-401 Interface
I2S interface when it is set high. This register is accessed
The MPU-401 port can be used for interfacing with MIDI.
through the configuration device. In addition, bit 6 of mixer
register 71h enables the data bus connection to the I2S MIDI
interface. Both these bits must be set in order to enable The ES1879 has an MPU-401 MIDI interface with a 23-
the interface. byte receive FIFO and an 8-byte transmit FIFO. The
I2S Serial Interface Format Select output of the transmit FIFO is serialized out the MSO pin
and also sent to the ES978 in the expansion unit, where
The I2S serial interface supports two different formats:
it is serialized out the MSO pin of that chip.
ES689/ES69x two-wire serial interface and I 2S. When
used in the ES689/ES69x format, IIDATA is the serial data MIDI data can be received from either the MSI pin of the
and IISCLK is the bit clock. The IILR input is not used and ES1879 or from the MSI pin of the ES978 in the expansion
can be left floating or connected to ground. Vendor- unit. In the unlikely event that MIDI data is received from
Defined Card-Level register 29h bits 5 and 4 select the both sources simultaneously, the data might be corrupted.
format (this register is accessed through the configuration Data received by the ES978 is transmitted back to the
device). See Vendor-Defined Card-Level register 29h ES1879 in the next upload frame and then placed in the
under “PnP Configuration and Registers” on page 30 for MPU-401 receive FIFO.
more detailed information.

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Game/Joystick Interface Joystick/MIDI External Interface Connector


The ES1879 includes 8 pins for a dual joystick port. The The joystick portion of the ES1879 reference design is
digital game port address is decoded for timer pins TA, TB, identical to that on a standard PC game control adapter or
TC, and TD, and for switch pins SWA, SWB, SWC, and game port. The PC-compatible joystick can be connected
SWD. The MIDI serial input and output also come from the to a 15-pin D-sub connector. It supports all standard PC-
game port connector in most applications. compatible joystick software.

Four of these eight pins, SW(A-D), are inputs for the If you need to support two joysticks, a joystick conversion
switches of the joysticks. The remaining 4 pins, T(A-D), cable is required. This cable uses a 15-pin D-sub male
are "one-shot" timers that generate pulses of varying connector on one end and two 15-pin D-sub female
widths, where the width corresponds to the current connectors on the other end. All signals on this cable have
resistance of one of the joystick potentiometers. direct pin-to-pin connection, except for pins 12 and 15. On
the male connector, pins 12 and 15 should be left without
PC Joysticks connection. On the female connector, pin 15 is internally
Normally, the host processor is responsible for measuring connected to pin 8, and pin 12 is internally connected to
the width of the pulse. The ES1879 can also do this pin 4. The dual joystick port and MIDI port take up only one
automatically. The host processor can read the measured slot in your PC, leaving room for other cards. The dual
widths directly rather than having to do the timing itself. joystick/MIDI connector configuration is shown in Figure
This is referred to as a “digital joystick.” Bit 1 of Vendor- 10.
Defined Card-Level register 29h determines whether the
The MIDI serial interface adapter for the joystick/midi
joystick port is a digital or analog joystick.
connector is shown in Figure 11.
Digital Joysticks
For digital joysticks, the host processor first writes any
value to the joystick port and then reads back seven +5V
separate values (shown in Table 7). Joystick B Joystick A
1
9
Table 7 Digital Joystick Read Values X-axis 10
2
X-axis
3
11
Read #1 Low byte timer A Button 4 Button
12
5
Read #2 Low byte timer B 13
Button 6
14
Button
Read #3 Low byte timer C Y-axis 7
Y-axis
15 8
Read #4 Low byte timer D
MIDI OUT
Read #5 Bits 3:0 – Upper nibble timer A MIDI IN
GND
Bits 7:4 – Upper nibble timer B
Read #6 Bits 3:0 – Upper nibble timer C Figure 10 Dual Joystick/MIDI Connector
Bits 7:4 – Upper nibble timer D
Read #7 Bit 0 – switch A
Bit 1 – switch B
Bit 2 – switch C
Bit 3 – switch D

The timer values reported range from 0 to FFFh (0-4095).


The timer clock is 895 kHz.

ES978 Joystick Interface


When docked, a software-programmable bit (bit 0 of
Vendor-Defined Card-Level register 29h) causes the
joystick connected to the ES978 to replace automatically
the one connected to the ES1879f.

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JOYSTICK PORT
8 R3
15 220
7 R4
2.2K R2
14
6 270
2 4
13 5
R1
5
10K Q2 C2 3 1
12 Q1 2N3904 220pF DIN
C1
4 2N3904 220pF J1
11
R5
3
10
5.6K MIDI OUT
2
9
1 R6

270
DB15P D1

2 4
MIDI IN
ISO1 5
1
3
DIN
J2

Figure 11 MIDI Serial Interface Adapter

ES978 Interface This interface uses six wires: two analog ground wires and
four analog signal wires (XA[3:0]). The four signal wires
When docked, the ES1879 is in constant communication
are used in one of five different modes. In each of these
with the ES978 in the expansion unit. A half-duplex,
modes, the master always refers to the ES1879 and the
bidirectional serial link keeps each chip updated on the
slave always refers to the ES978.
status of the other. For example, the status of the mixer
registers located in the ES1879 are transmitted down to ‡ Mode 0 – Stereo playback. Two differential pairs for left
the ES978. MIDI data received in the ES978 is transmitted and right channels, transmitted from the master to the
up to the ES1879. slave.
In addition to the digital control link, four analog wires ‡ Mode 1 – Stereo record. Two differential pairs for left and
connect the two chips directly. These four wires are right channels, transmitted from the slave to the master.
configured as a pair of differential audio channels. The ‡ Mode 2 – Monophonic full-duplex. Two differential pairs.
ES1879 uses these two audio channels in one of four One pair is for monophonic playback from master to
ways: stereo playback (ES1879 transmits to the ES978), slave, the second pair is for monophonic recording from
stereo record (the ES978 transmits to the ES1879), mono slave to master. The mono playback signal is input to both
full-duplex (one mono channel in each direction), and left and right host audio inputs of the playback mixer. The
stereo full-duplex (one stereo channel in each direction). mono record signal is derived by averaging the left and
Table 8 ES978 Interface Pins right outputs of the record mixer.
‡ Mode 3 – Stereo full-duplex. The four signals are not used
Pin Description
differentially ( This mode is not supported by the
XA[3:0] Bidirectional differential transmitter/receivers. ES1878).
Expansion audio bus. These are analog signals
that are DC-coupled to the corresponding pins of ‡ Mode 4 – Not docked (DOCKED=0). Like Mode 0, except
the ES978. the analog outputs follow AOUT_L and AOUT_R rather
XSD Expansion serial bus data I/O. High-impedance than the output of the mixer.
when DOCKED = 0. After a change of mode, the data is muted at the receiving
XSC Expansion serial bus clock and frame sync. High- end for a period of 25 milliseconds. It is the responsibility
impedance when DOCKED = 0. of the master not to have contention caused by both ends
transmitting on the same signal wire.
DOCKED Status input that is active-high when the ES1879
is docked to the ES978. This pin has an internal
pull-down to GNDD.

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Table 9 shows the mode configurations when the Record Mode


notebook unit is docked. In record mode, the expansion audio bus is turned around,
and sound data is sent from the expansion unit ES978
Table 9 Docked Modes for Analog Audio
chip to the ES1879 in the portable unit. The sound data
Mode XA0 XA1 XA2 XA3 from the expansion unit can be mixed inside the ES1879
0 -Left Play +Left Play -Right Play +Right Play with local sources before recording. Because portable unit
sources (for example, FM) can be mixed into the
1 +Left -Left +Right -Right
Record Record Record Record recording, it is not possible to do a record monitor function
through the expansion unit speakers (they are
2 -Play +Play +Record -Record
automatically muted in record mode). It is possible for the
3 Left Record Left Play Right Record Right Play record monitor to use the speakers in the portable unit
(see bit 5 of Vendor-Defined Card-Level register 2Bh.)
Docking Status
The ES1879 is either in docked or undocked state. The The default situation for most applications is to have all
state is determined by the DOCKED input, which is active- speakers muted during recording.
high when docked. As in previous chips, one of four record sources can be
In the undocked state, the XSC and XSD pins are driven selected: Mic, Line, Aux A, or Mixer. When docked, the
low. The XA[3:0] pins act as in mode 0 (differential ES1879 chip knows whether each resource is present in
outputs), except they follow the AOUT_L/AOUT_R the portable, the docking station, or both, and acts
outputs directly (i.e., after the master volume). accordingly.

Playback Mode Mono Full-Duplex Mode


The ES1879/ES978 design assumes that the active In the ES1879, host-based software applications can use
speakers move from the portable to the expansion unit full-duplex mode through two 8-bit DMA channels. The
when docked. Except when recording, expansion audio restriction is that both record and playback are
sources are mixed in the expansion unit within the ES978 monophonic.
and played through speakers in the expansion unit. In The record channel can record from any analog input of
most cases, speakers within the portable unit are the ES1879, any analog input of the remote ES978, any
programmed to be automatically muted when docked. mix of the same, or from the FDXI input to the ES1879
An exception is PC speaker beeps, which are always when using the DSP serial port.
heard in the portable, even when docked. Stereo Full-Duplex Mode
Each audio input can be programmed individually on how In the ES1879, host-based software applications can use
to respond to a docking situation in one of the three ways: stereo full-duplex mode through two 8-bit DMA channels.
‡ As an analog input, such as mic, that remains in the The record channel can record from any analog input of
portable (ES1879) when docked and is muted in the the ES1879, any analog input of the remote ES978, or any
ES978. mix of the same. It is possible to record from the FDXI
‡ As an analog input, such as line-in, that is disabled in the input to the ES1879 when using the DSP serial port, but
ES1879 when docked and enabled in the ES978 when this data is monophonic.
docked, i.e., it is muted in the mixers in the ES1879 and No ES978 – Differential AOUT Mode
ES978.
In some applications, there is no ES978 in the expansion
‡ As an analog input that is enabled in both the ES1879 and unit. In this case, XA[3:0] are used as differential outputs
ES978 mixers, and shares a common volume control. that follow AOUT_L/AOUT_R and are intended to connect
(Note: An exception to sharing a common volume control to a differential-input power amplifier in the expansion unit.
is allowed for the Mappable Volume register 5Dh; see This mode of operation is selected automatically
below). whenever the DOCKED input is zero. When DOCKED is
The playback master volume is controlled through zero, XSC and XSD are high-impedance.
software programming or by the up/down/mute switch
Power Management
inputs. The latter method, called hardware volume control,
has active-low switch inputs in both the ES1879 and Power management is controlled by bits 1:0 of Vendor-
ES978. Defined Card-Level register 2Dh. In previous AudioDrive®
chips, power management was controlled via I/O port

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Audio_Base+7h. Only bit 5 (FM reset) and bit 7 (suspend Table 10 contains the data configuration for the download
request) of I/O port Audio_Base+7h are supported in the period.
ES1879.
Table 10 Download Period Data Configuration
Expansion Audio Interface – Digital Byte Bits Function
Two wires are used to transmit serial data between the 0 1:0 Mode of expansion analog interface
ES1879 and ES978. The first signal, XSC, acts as a frame 4:2 Record source select
sync and shift clock. The bit clock rate is 3.58 MHz. 5 Master output enable
6 1: MIDI loopback test
A typical frame consists of:
7 1: MIDI transmit signal (byte 1 contains
‡ Sync period – 24 clocks wide MIDI data)
‡ Download period – 144 clocks wide 1 15:8 MIDI transmit data (if bit 7 of byte 0 is high)
2 23:16 XGPO[7:0] data
‡ Turnaround period – 8 clocks wide
3 31:24 Playback mixer – Host audio volume
‡ Upload period – 80 clocks wide
4 39:32 Playback mixer – Line volume
Total: 256 bit clocks/frame, which is equivalent to a 14 kHz
5 47:40 Playback mixer – Mic volume
frame rate.
6 55:48 Playback mixer – Aux A (CD) volume
The function of the upload and download periods is to 7 63:56 Playback mixer – Aux B volume
continually update corresponding registers within each
8 71:64 Playback mixer – I2S/ES689 volume
device. For example, pressing the VOLUP button in the
9 79:72 Reserved
expansion unit, transmits the pin state to the ES1879
where it is AND’d with the same pin of the ES1879. The 10 87:80 Record mixer – Line volume
ES1879 updates its copy of the master volume register. 11 95:88 Record mixer – Mic volume
The ES978 receives the new value in the master volume 12 103:96 Record mixer – Aux A (CD) volume
register during the first download period of the next frame. 13 111:104 Record mixer – Aux B volume
Sync Period 14 119:112 Record mixer – I2S/ES689 volume
In the sync period, XSC is low for 12 bit clock periods, and 15 126:120 Master volume left
then high for 12 bit clock periods. 127 1: Mute left

Download Period 16 134:128 Master volume right


135 1: Mute right
In the download period, data is transmitted serially from
17 143:136 CRC checksum
the ES1879 to the ES978 via the signal XSD. XSC is the
bit shift clock. Data is shifted out of the ES1879 on the
falling edge of XSC. Data is shifted into the ES978 on the
Turnaround Period
rising edge of XSC.
There are 8 bits between the end of the download period
The download period is 144 bits wide. Each bit takes 4 and the start of the upload period.
oscillator clocks (bit rate = 3.58 MHz). The last 8 bits are a
Upload Period
checksum byte.
In the upload period, data is transmitted serially in the
The upload period is 80 bits wide. The last 8 bits are a opposite direction, from the ES978 to the ES1879 via the
checksum byte. same signal wire, XSD.

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Table 11 contains the data configuration for the upload Each enabled GPI input can be read by the host processor
period. at any time. Also, each GPI input can be programmed to
remotely control a corresponding GPO output in the
Table 11 Upload Period Data Configuration ES978, thereby saving interconnects between the
Byte Bits Function portable and expansion units.
0 3:0 Joystick switch status Each enabled GPO pin can be controlled either by a write
4 VOLUP input status by the host to an ES1879 register or remotely from a
5 VOLDN input status corresponding GPI pin of the ES978.
6 MUTE input status
7 1: MIDI receive data following The worst-case latency between the ES978 and ES1879,
1 15:8 MIDI receive data if bit 7 of byte 0 is set. due to the serial interconnection, is about 140 µsec.
2 23:16 XGPI input state GPI/O Registers
3 31:24 Low byte joystick timer A
The GPI/O registers are as follows:
4 39:32 Low byte joystick timer B
‡ Configuration_Device_Base+2h
5 47:40 Low byte joystick timer C
Bits 6:0 of this register set the state of the GPO[6:0]
6 55:48 Low byte joystick timer D
pins that are enabled as outputs and are not mapped
7 59:56 High nibble joystick timer A to the GPI pins of the ES978.
63:60 High nibble joystick timer B
8 67:64 High nibble joystick timer C ‡ Configuration_Device_Base+3h
71:68 High nibble joystick timer D Bits 7:0 of this register set the state of the XGPO[7:0]
9 79:72 CRC checksum pins of the ES978 that are not mapped to the GPI pins
of the ES1879.

Expansion Audio Interface – Analog


‡ Vendor-Defined Card-Level register 25h
This register controls whether any shared function pins
Mono FDXI and FDXO are general-purpose inputs/outputs.
FDXI is shared with AUXB_L and FDXO is shared with ‡ Vendor-Defined Card-Level register 26h
AUXB_R. The ES1879 supports the use of FDXI and
Vendor-Defined Card-Level register 26h, which is the
FDXO as input to the ADC and output from the DAC when
GPO Map register, selects whether a GPO pin is
using the DSP serial port.
controlled by Configuration_Device_Base+2h or by the
Mono FDXI/O mode is useful with an external modem that GPI pin of ES978.
has integrated a CODEC for speakerphone applications.
‡ Vendor-Defined Card-Level register 27h
Bits 1:0 of Mixer Extension register 46h enable FDXI as a Vendor-Defined Card-Level register 27h, which is the
mono input and FDXO as a mono output. When FDXI is a GPI Map register, selects whether a GPI pin controls a
mono input to the mixer, its input impedance is cut in half XGPO pin in the ES978, or if the XGPO pin is
to 25k ohms. When FDXO is an output, it has a 5k ohm controlled by Configuration_Device_Base+3h.
output impedance. When FDXO is not an output, it is the
AUXB_R input to the mixer and has a 50k ohm pull-up to NOTE: Bits 1 and 0 of register Audio_Base+7h do not
CMR. control GPO0 and GPO1 as in previous AudioDrive® chips.
Also, the feature of previous audio controllers that causes
Contact an ESS Field Application Engineer for an GPO0 and GPO1 to change state automatically when the
application note on how to use the FDXI/FDXO feature. chip is powered down is not supported in the ES1879.

General-Purpose I/O Spatializer 3-D Audio Effects Processor


Up to seven general-purpose inputs and seven general- The ES1879 incoporates an embedded Spatializer audio
purpose outputs are available. Four of the GPO pins have effects processor, positioned between the output of the
another function (ISA interrupt request output) and may playback mixer and the master volume controls. The
not be available for use as general-purpose outputs. All of Spatializer produces a wider perceived stereo effect.
the GPI pins have other functions (volume control, DRQC, Given a mono input, the Spatializer processor has a mode
DACKBC, DRQD, DACKBD) and may not be available for that generates a stereo effect.
use as general-purpose inputs. For more information, see
“GPI/O Registers” .

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The amount of effect can be controlled by either directly Master Volume


programming mixer register 52h or by allowing the
The master volume is controlled through Programmed I/O
ES1879 to control the effect level automatically, based on
or volume control switch inputs. The master volume
the stereo content of the input signal. This latter feature is
supports 6 bits per channel plus mute. When docked, the
called auto-limiting. In auto-limiting, the ES1879
ES1879 transmits the master volume information to the
constantly adjusts the amount of effect based on the
ES978 where it takes effect after the output of the ES978
stereo content of the input signal. The host software can
mixer.
set a maximum effect level by programming register 52h.
This gives the auto-limiting logic an upper bound. For support of legacy master volume control, any write to
legacy mixer register 22h or 32h is translated
automatically into writes to the master volume registers.
Since mixer register 22h only has 3-bit resolution and
mixer register 32h only 4-bit resolution, a translation circuit
is included in the ES1879 that translates 3- or 4-bit volume
values into the 6-bit volume plus mute that is used by the
master volume registers. Reading a legacy master volume
register (22h or 32h) also uses a translation circuit to
convert 6-bit master volumes plus mute into 3- or 4-bit
legacy master volume numbers. Support of legacy mixer
registers can be defeated under software control.
See also “Programming the ES1879 Mixer” on page 59.

Hardware Volume Controls


VOLUP, VOLDN, and MUTE are three input pins with
internal pull-up devices. The state of these pins is AND’d
with the state of the corresponding pins of the ES978
when docked.
The VOLUP and VOLDN buttons produce a single-step
change in volume when they are first pressed, and then, if
held down, enter a fast-scrolling mode up or down. The
single-step change can be either 1 volume unit (0.75 dB)
or 3 volume units (2.25 dB) as determined by bit 5 of mixer
register 64h. In fast-scrolling mode, the step change is
always 1 volume unit.
The three inputs have debounce circuitry within the
ES1879. Each input should be held low for 40 msec or
more to be recognized as a valid button press. Each input
should be held high for 40 msec or more between button
presses. A software option allows the debounce time to be
reduced from 40 msecs to 10 µsec (bits 3:2 of mixer
register 64h).
A software selectable option enables the mute input to be
omitted (bits 3:2 of mixer register 64h). The mute input is
defined as the state when both up and down inputs are
low. By default, this feature is disabled.
The hardware volume inputs of the ES1879 can be used
as general-purpose inputs (see bits 5:4 of Vendor-Defined
Card-Level register 25h). In this case, they cannot be used
as volume control inputs.

26 SAM0025A-062397 ESS Technology, Inc.


ES1879 DATA SHEET PRELIMINARY
PERIPHERAL INTERFACING

Split Mode Serial EEPROM Interface


Normally, the hardware volume controls change the The ES1879 gets Plug and Play configuration data from
master volume registers directly and produce an interrupt an internal masked ROM or an external EEPROM device.
at each change. Instead, the ES1879 can be programmed The external EEPROM is accessed by the ES1879 when
to use Split mode. In this case, the hardware volume IPROM (pin 58) is low. When IPROM is low, the chip select
counters (mixer registers 61h and 63h) are split from the pin SECS pulses high, enabling access to the external
master volume registers (mixer registers 60h and 62h). EEPROM. The external EEPROM device is 512 x 8-bit in
Pressing a hardware volume control button changes the size. When IPROM is high, the ES1879 reads its internal
hardware volume counter and produces an interrupt. The ROM for PnP configuration data.
host software can read the hardware volume counters and
update the master volume registers as needed. The EEPROM interface is shared with the hardware
volume controls. When the EEPROM interface is active,
PC Speaker the volume controls are deactivated. See Figure 13.
The PC speaker is supported by a 1-bit DAC with volume The host processor can read or write the EEPROM,
control. The analog output pin PCSPKO is intended to be allowing the EEPROM to be reprogrammed or initially
externally mixed at the external amplifier, which means programmed during production testing.
that the PC speaker audio is not transmitted to the ES978
through the expansion audio interface (XA[3:0]) but is EEPROM ROM FORMAT
always heard through the portable speakers. 'A5' Sync Byte
IRQB IRQA Mapping for IRQB/A
PC Speaker Volume Control IRQD IRQC Mapping for IRQD/C
When the PCSPKI signal is high, a resistive path to analog IRQE Mapping for IRQE
DRQB DRQA Mapping for DRQB/A
ground is enabled. The value of the resistor is selected from
DRQD DRQC Mapping for DRQD/C
among 7 choices to control the amplitude of the output signal.
PNP Reg 25h Miscellaneous
PNP Reg 26h Miscellaneous

VDDA The rest of the data is as per the ISA PnP


specification.
470 Ω
PCSPKO
.1 µF ES1879
.01 µF
93LC66
PCSPKI IPROM (512 x 8-bit serial EEPROM)

SEDI/VOLUP DI

SEDO/VOLDN DO
GNDA
SECLK/MUTE CLK
Figure 12 PC Speaker Volume Circuitry
SECS CS

With the external circuit shown in Figure 12, the amplitude


of a square wave output on pin PCSPKO should be mute
approximately VDDA/2 for maximum volume, i.e., the
vol down
internal resistor is approximately 500 ohms (± 30%). The
other levels are relative to this amplitude as follows: vol up

off, -18dB, -15dB, -12dB, -9dB, -6dB, -3dB, +0dB Figure 13 Serial EEPROM – Typical Application
The purpose of the circuit, beyond volume control of the
speaker, is to prevent digital noise from the PC speaker
signal being mixed into the analog signal. This circuit See “Accessing the ROM/EEPROM” on page 30.
provides a clean analog signal. The output can either be
mixed with the AOUT_L and AOUT_R pins externally or
used to drive a simple transistor amplifier to drive an 8
ohm speaker dedicated to producing beeps.

ESS Technology, Inc. SAM0025A-062397 27


PRELIMINARY ES1879 DATA SHEET
ANALOG DESIGN CONSIDERATIONS

ANALOG DESIGN CONSIDERATIONS


This section describes design considerations related to Switch-Capacitor Filter
inputs and outputs of analog signals and related pins on
The outputs of the FOUT_L and FOUT_R filters must be
the chip.
AC-coupled to the inputs CIN_L and CIN_R, respectively,
which provides for DC blocking and an opportunity for low-
Reference Generator
pass filtering with capacitors to analog ground at these
Reference generator pin CMR is connected through inputs.
bypass capacitors to analog ground.

ES1879
ES1879 .22 µF
FOUT_L
+47 µF
CMR .001 µF
CIN_L
.1 µF

.22 µF
FOUT_R
.001 µF
CIN_R

Figure 14 Reference Generator Pin Diagram Figure 15 Switch-Capacitor Filter Pin Diagram

Audio Inputs and Outputs


Analog inputs MIC, stereo LINE, stereo AUXA, and stereo
AUXB are to be capacitively coupled to their respective
input signals. All have pull-up resistors to CMR.
ES1879 analog outputs AOUT_L and AOUT_R are
intended to be AC-coupled to an amplifier, volume control
potentiometer, or line-level outputs.

28 SAM0025A-062397 ESS Technology, Inc.


ES1879 DATA SHEET PRELIMINARY
CONFIGURATION

CONFIGURATION
The ES1879 supports the industry-standard ISA Plug and Non PnP Mode
Play (PnP) specification, as well as a software
Because of the above restrictions imposed by use of PnP,
configuration method that does not rely on PnP. Bit 2 of
a separate configuration method is implemented in the
PnP vendor register 2Dh determines the configuration
ES1879. A special sequence of 34 bytes is written
method. When bit 2 is high, the ISA PnP configuration
consecutively to I/O address 279h or 388h. This sequence
mode is disabled. Bit 2 is low (ISA PnP) by default.
is called the “bypass key” because it can be used to short-
NOTE: The ES1878 supported PnP from an internal ROM circuit the PnP process and directly enable the
and/or a bypass key. External EEPROM was not configuration device of the ES1879. Once the
supported. An input pin PNPEN, when high, enabled both configuration device is enabled, all the PnP registers of the
PnP and a bypass key written to I/O address 279h. When ES1879 are accessible and can be programmed.
PNPEN was low, PnP was disabled and the bypass key
was written to I/O address 388h. In the ES1879, the Using Non PnP mode is advisable when the ES1879 is
function of pin PNPEN is replaced by bit 2 of PnP vendor designed into the motherboard. Send bypass key during
register 2Dh. The ES1879 also allows the bypass key to the BIOS PnP configuration.
be written to either port 279h or port 388h.
Bypass Key
Using ISA PnP Mode
If PnP is not supported by the system, it is possible to
There are several design implications of using ISA PnP: bypass PnP by issuing a special “bypass key” to the
1. The PCI-ISA bridge for the ES1879 must be in ES1879 to force the configuration device to be enabled at
subtractive decode mode. This mode is required a specific l/O address. The ES1879 must be in the “wait-
because PnP can place the I/O addresses of the for-key” Plug and Play state. The special key is 32 bytes
ES1879 devices in a very large number of locations. long, written to the PnP address register (279h or 388h).
Follow the bypass key immediately with two I/O writes to
2. All PnP devices within the system must share the
the PnP address register to set the low and high bytes of
same ISA bus and bridge.
the address register of the configuration device. The
3. The internal resource ROM cannot be changed. bypass key also activates the configuration device. The
I/O addresses, interrupts, and DMA channels must address of the configuration device must be in the range
be supported as defined by the resource ROM. 100h-FF8h, aligned on a multiple of 8. An “alias” of the
The joystick port must be supported. audio device address can be used. For example, use
4. All five IRQ lines must be connected to ISA E20h for the configuration device if the audio device
interrupt request channels as follows: address is at 220h.
IRQA -IRQ9 NOTE: Perform the entire sequence with interrupts
IRQB -IRQ5 disabled to minimize the chance that an interrupt corrupt
the sequence.
IRQC -IRQ7
66, a1, c2, f1, ea, e7, 71, aa
IRQD -IRQ10
c7, 63, 33, 1b, d, 96, db, 6d
IRQE -IRQ11 a4, 50, 28, 16, 9b, 4d, b6, c9
5. All three DRQ/DACK pairs must be connected to f4, 78, 3e, 8d, d6, fb, 7f, 3d
ISA DMA signals as follows: <config_address_low>, <config_address_high>
DRQA DRQ0
DACKBA -DACK0
DRQB DRQ1
DACKBB -DACK1
DRQC DRQ3
DACKBC -DACK3
DRQD DRQ5, 6, or 7
DACKBD -DACK5, 6, or 7

ESS Technology, Inc. SAM0025A-062397 29


PRELIMINARY ES1879 DATA SHEET
CONFIGURATION

Accessing the ROM/EEPROM


Card-Level Registers Logical Device Registers
The PnP ROM/EEPROM software interface is used to (one set per card) (one set per logical device on card)
directly read the PnP ROM or EEPROM, as well as send
Address Address
commands and data to program an external EEPROM.
00h Set Read Port Address 30h Activate
EEPROM Function Action

Card-Control Card-Level Registers


01h Serial Isolation 31h I/O Range Check
Read EEPROM data register or read Read PnP Vendor 32h
02h Configuration Control Reserved for
internal ROM, then increment one register 2Eh. •
• Logical Device
address. • Control
03h Wake Command 37h (Not supported)
Write EEPROM data register, then Write PnP Vendor 38h
Vendor-Defined
04h Resource Data •
increment one address. register 2Eh. •

Logical Device
Control
Write EEPROM command register. Write PnP vendor 05h Status 3Fh (Not supported)
40h ISA Memory
register 2Fh. •
06h Card Select Number (CSN) • Configuration
Reset EEPROM/ROM address Read PnP vendor • Registers 3:0
07h 5Fh (Not supported)
counter. register 2Fh. Logical Device Number
60h
08h • I/O Configuration
Reserved •
• • Registers 7:0
• Card-Level 6Fh
See “Serial EEPROM Interface” on page 27. • Registers 70h
(Not supported) • Interrupt Configuration
1Fh •
20h • Registers 1:0
PnP Configuration and Registers • Vendor-Defined 73h
• 74h
• Card-Level
Figure 16 shows the configuration register set that is 2Fh Registers •
• DMA Configuration
discussed in the following pages. As shown below, the • Registers 1:0
8 bits 75h
Card-Level registers supported by the ES1879 are the 76h 32-bit Memory
Card-Control Card-Level registers at addresses 00h-07h, 7 0 • Configuration

• Registers 1:0
and the Vendor-Defined Card-Level registers at (Not supported)
A8h
addresses 20h-2Fh. The Card-Control Card-Level register A9h Reserved for
• Logical Device
at address 07h is a pointer to the Logical Device registers •
• Configuration
supported by the ES1879 (one set of registers for each EFh (Not supported)
logical device on the “card”). In the ES1879, there are F0h Vendor-Defined
• Logical Device
three logical devices: the configuration device, the •
• Configuration
audio+FM+MPU-401 device, and the joystick device. FEh (Not supported)
FFh Reserved

8 bits
7 0

Figure 16 Configuration Register Outline

Accessing the PnP Configuration Registers


The PnP configuration registers of the ES1879 can be
accessed in two ways. First, the registers can be read or
written as defined by the PnP specification. Second, the
registers can be read or written using two I/O locations of
the configuration device.
The first location of the configuration device is written with
the PnP register number to be read or written. After
programming the PnP register number, the register can be
read or written by accessing the second location of the
configuration device.

30 SAM0025A-062397 ESS Technology, Inc.


ES1879 DATA SHEET PRELIMINARY
CONFIGURATION

Example Configuring IRQ, DMA, and GPI/O Pins


Using Non PnP Method to Configure the ES1879: IRQ (Registers 20h, 21h, 22h, 70h, 72h)
1. Enable the configuration device at I/O address 800h by If only one IRQ channel (IRQA) is connected to the bus,
sending the bypass key with interrupts disabled. program the Vendor-Defined Card-Level registers 20h,
2. Program Vendor-Defined Card-Level registers 20h- 21h, and 22h as follows:
2Dh as follows: write Vendor-Defined Card-Level register 20h = 10h + IRQA_channel_number
register number to I/O address 800h and data to I/O
“1” = IRQB is unused
address 801h.
register 21h = 11h“1” = IRQC/D are unused
1. 20h, 21h, 22h: assign ISA IRQ channels to pins.
Unused pins are assigned to IRQ1. register 22h = 01h“1” = IRQE is unused
2. 23h, 24h: assign ISA DMA channels to pins. The recommended IRQ lines are:
Unused pins are assigned DRQ2.
5 first choice
3. 25h: set bit 7 low, other bits as needed to
enable GPOs or GPIs. 9, 5, 7, 10 second choice
4. 26h: defines whether GPOs are under software 3, 4, 5, 7, 9, 10, 11, 12, 15 third choice
or ES978 control.
The IRQ channel number must also be programmed into
5. 27h: defines whether GPIs control ES978 register 70h of LDN 1. When register 70h matches one of
GPOs. the channel numbers in registers 20h, 21h, or 22h, a
6. 28h: leave all of the bits set to 00h until connection is made. The second interrupt of the audio
Windows starts up. The Windows driver will device is not used, so register 72h should be zero.
write this register to allow sharing MPU-401 DRQ/DACK (Registers 23h, 24h, 74h, 75h)
and H/W volume interrupts.
If DRQA/DACKBA is set for the first audio channel DMA
7. 29h: bit 7 high is recommended. Set bits 6:4 and DRQB/DACKBB is set for second audio channel
based on I2S interface use. Bit 1 should be left DMA, program register 23h to be the first DMA channel
low in the BIOS. Bit 0 is based on the system number in bits 3:0 and the second DMA channel number
design. in bits 7:4. Registers 74h and 75h of LDN 1 must also be
8. 2Ah: set this register to default value 0Eh. programmed to match the DRQA and DRQB channel
9. 2Bh: leave bits 7:5 set at 00h. Bits 4:0 settings numbers.
are based on the system design. Example:
10. 2Ch: settings are based on the system design.
First DMA channel is “1” and second DMA channel is “3”.
11. 2Dh: leave this register value set at 03h (fully
powered on). register 23h = 31h
3. Configure and enable audio device. Set register 7h register 24h = 02h
(LDN number) to 01h. Then program device registers “2” = DRQC/DACKBC are unused
60h-65h, 70h, 74h, and 75h. Leave register 72h set at “0” = DRQD/DACKBD are unused
00h (second interrupt not used). Finally, set register
register 74h, LDN 1 = 01h
30h to 01h in order to activate the audio device.
register 75h, LDN 1 = 03h
4. (Optional) Configure and enable joystick device. Set
register 7h (LDN number) to 02h. Then program GPI/O (Vendor-Defined Card-Level Register 25h)
registers 60h and 61h with base address. Set register As long as DRQC/DACKBC and DRQD/DACKBD are not
30h to 01h in order to activate the joystick device. selected, these pins are usable as general-purpose inputs
without further setup.
General-purpose inputs, GPI 4, 5, and 6 are the MUTE,
VOLUP, and VOLDN inputs. They can be read at any time,
but if the pins are not to act as hardware volume control,
bits 4 and 5 of Vendor-Defined Card-Level register 25h
must be set.
To use IRQ(B-E) as GPOs, the appropriate bits in Vendor-
Defined Card-Level register 25h must be set.

ESS Technology, Inc. SAM0025A-062397 31


PRELIMINARY ES1879 DATA SHEET
CONFIGURATION

Card-Control Card-Level Registers (00h – 07h) Resource Data (04h, R)


This section describes the PnP Card registers of the Resource data
ES1879. 7 6 5 4 3 2 1 0

Set RD_DATA Port (00h, R/W) Returns next byte of resource data, provided the status bit
Bits 9:2 of the PnP RD_DATA port in register 05h has been polled before each byte read,
7 6 5 4 3 2 1 0 indicating that data is ready. Only works in Configuration
mode.
The PnP read port can be written only when the card is in
Isolation mode. It is reset low by hardware reset. It can be Status (05h, R)
read only from Configuration mode. Bits 1:0 of PnP read 0 Status
port are always one. 7 6 5 4 3 2 1 0

Serial Isolation (01h, R) Bit Definitions:


Data Bits Name Description
7 6 5 4 3 2 1 0 7:1 – Reserved. Always write 0.
0 Status 1 = Ready to read resource data from register
Read-only in isolation state. Used to read the serial 04h. Only works in Configuration mode.
identifier during the card isolation process. 0 = Resource data not available.

Config Control (02h, W) CSN (06h, R/W)


x x x x x RESET_CSN WFK SWR Card select number
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Bit Definitions: Read/Write card select number. Write only works in


Bits Name Description Isolation mode. Causes transition to Configuration mode.
7:3 – Don’t care. Read works only in Configuration mode.
2 RESET_CSN RESET_CSN command.
1 = Card’s CSNs set to zero. LDN (07h, R/W)
1 WFK WAIT_FOR_KEY command. Logical device number
1 = Enter wait-for-key state. 7 6 5 4 3 2 1 0
0 SWR Software reset command. Does not work
in wait-for-key state. Read/Write logical device number. Only works in
1 = Reset config registers to default. Configuration mode.
LDN 0 Configuration device
Wake[CSN] (03h, W)
LDN 1 Audio/FM device
Data
7 6 5 4 3 2 1 0
LDN 2 Joystick device
LDN 3 MPU-401 device (only if bit 7 of Vendor
If data written is 00h and it: register 25h is high)
‡ matches the CSN:
this card goes from Sleep mode to Isolation mode.
‡ does not match the CSN:
this card goes from Configuration mode to Sleep
mode.
If the data written is non zero, and it:
‡ matches the CSN:
this card goes from Sleep mode to Configuration mode.
‡ does not match the CSN:
this card goes from Isolation mode to Sleep mode.

32 SAM0025A-062397 ESS Technology, Inc.


ES1879 DATA SHEET PRELIMINARY
CONFIGURATION

Vendor-Defined Card-Level Registers (20h – 2Fh) Shared Function Assignment (25h, R)


This section describes the PnP Vendor registers of the MPU-401 VOLUP,
MUTE/ IRQE/ IRQD/ IRQC/ IRQB/
ES1879. LDN 1/ x VOLDN/
GPI4 GPO6 GPO5 GPO4 GPO3
LDN 3 GPI5, GPI6
7 6 5 4 3 2 1 0
IRQB, IRQA (20h, R)
IRQB IRQA
Loaded from Configuration ROM header after PnP reset.
7 6 5 4 3 2 1 0
Bit Definitions:
Defines IRQ number assigned to B and A pins. Loaded Bits Name Description
from configuration ROM header after PnP reset. Unused 7 MPU- Determines whether MPU-401 is LDN 3 or part
IRQ pins should be assigned IRQ #1. 401 LDN of LDN 1.
1/LDN 3 1 = MPU-401 is LDN 3.
IRQD, IRQC (21h, R) 0 = MPU-401 is part of LDN 1.
IRQD IRQC 6 — Don’t care.
7 6 5 4 3 2 1 0 5 VOLUP, Determines which functions pins 91 and 92 are
VOLDN/ used for. These pins are also SEDI and SEDO.
Defines IRQ number assigned to D and C pins. Loaded GPI5, 1 = Pins 91 and 92 are GPI5 and GPI6.
from configuration ROM header after PnP reset. Unused GPI6 0 = Pins 91 and 92 are VOLUP and VOLDN.
IRQ pins should be assigned IRQ1. 4 MUTE/ Determines which function pin 90 is used for.
GPI4 1 = Pin 90 is GPI4.
IRQE (22h, R) 0 = Pin 90 is MUTE.
0 IRQE 3 IRQE/ Determines which function pin 93 is used for.
GPO6 1 = Pin 93 is GPO6.
7 6 5 4 3 2 1 0
0 = Pin 93 is IRQE.
Bits 3:0 define IRQ number assigned to E pin. Loaded from 2 IRQD/ Determines which function pin 94 is used for.
GPO5 1 = Pin 94 is GPO5.
configuration ROM header after PnP reset. If the IRQ pin is
0 = Pin 94 is IRQD.
unused, it should be assigned IRQ1. Bits 7:4 are reserved.
Always write 0. 1 IRQC/ Determines which function pin 95 is used for.
GPO4 1 = Pin 95 is GPO4.
0 = Pin 95 is IRQC.
DRQB, DRQA (23h, R)
0 IRQB/ Determines which function pin 96 is used for.
DRQB DRQA
GPO3 1 = Pin 96 is GPO3.
7 6 5 4 3 2 1 0 0 = Pin 96 is IRQB.

Defines DRQ number assigned to B and A pins. Loaded GPO Map (26h, R)
from configuration ROM header after PnP reset. Unused
x GPO6 GPO5 GPO4 GPO3 GPO2 GPO1 GPO0
DRQ pins should be assigned DRQ2.
7 6 5 4 3 2 1 0

DRQD, DRQC (24h, R)


One bit for each GPO[6:0]. This register is reset to zero by
DRQD DRQC
hardware reset, but not by PnP reset.
7 6 5 4 3 2 1 0
Bit Definitions:
Bits 3:0 define DRQ number assigned to C pins. Bits 7:4 Bits Name Description
define DRQ number assigned to D pins. If DRQD and 7 — Don’t care.
DACKBD are not connected to an ISA DMA channel, then 6:0 GPO[6:0] 1 = GPO pin controlled by corresponding GPI
these pins should be assigned DRQ2. Loaded from pin of the ES978.
Configuration ROM header after PnP reset. 0 = GPO pins controlled by port
Configuration_Device_Base+2h.

ESS Technology, Inc. SAM0025A-062397 33


PRELIMINARY ES1879 DATA SHEET
CONFIGURATION

GPI Map (27h, R) Miscellaneous Digital Control (29h, R/W)


x GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 Digital ES978
DRQ latch I2S port I2S port MIDI loopback
x joystick joystick
7 6 5 4 3 2 1 0 enable enable function test enable
enable enable
7 6 5 4 3 2 1 0
One bit for each GPI[6:0]. This register is reset to zero by
hardware reset but not by PnP reset.
This register is reset to 21h by hardware reset but not by
Bit Definitions: PnP reset. The hardware reset default format is I2S.
Bits Name Description Bit Definitions:
7 — Don’t care. Bits Name Description
6:0 GPI[6:0] 1 = GPI pin controls corresponding GPO pin of 7 DRQ 1 = DRQ latch feature enabled.
the ES978. latch 0 = DRQ latch feature disabled (default).
0 = GPO pins of the ES978 controlled by port enable
Configuration_Device_Base+3h, not by the
GPI pins of the ES1879. 6 I2S port 1 = I2S port enabled.
enable 0 = I2S port disabled (hardware reset default).
MPU-401 and Hardware Volume IRQ (28h, R) 5:4 I2S port Selects the function for the I2S port.
function bit 5 bit 4 function
Hardware volume IRQ number MPU-401 IRQ number
0 0 ES689/ES69x. IIData is data.
7 6 5 4 3 2 1 0 IISCLK is bit clock. IILR should
connect low or float.
Bit Definitions: 0 1 Reserved.
Bits Name Description 1 0 I2S port is x384 oversampling
(hardware reset default).
7:4 Hardware Hardware volume IRQ number. This number
1 1 Reserved.
volume must be shared with audio 1 or audio 2.
IRQ num- 3 MIDI 1 = Enable ES978 MIDI loopback test.
ber loopback 0 = Disable ES978 MIDI loopback test.
test
6:0 MPU-401 MPU-401 IRQ number. Alias address with
enable
IRQ num- register 70h of MPU-401 LDN 3.
ber 2 – Don’t care.
1 Digital 1 = Digital joystick.
joystick 0 = Analog joystick (default).
enable
0 ES978 1 = Use ES978 joystick when docked (default).
joystick 0 = Use ES1879 joystick when docked.
enable

Special Volume (2Ah, R)


Volume mixed into ES978 record Volume mixed into ES978 playback
7 6 5 4 3 2 1 0

This register is reset to 0Eh by hardware reset but not by


PnP reset.
Bit Definitions:
Bits Name Description
7:4 Volume Volume of host audio mixed into ES978 record
mixed mixer (default = 0).
into
ES978
record
3:0 Volume Volume of host audio mixed into ES978 play-
mixed back mixer (default = 0Eh).
into
ES978
playback

34 SAM0025A-062397 ESS Technology, Inc.


ES1879 DATA SHEET PRELIMINARY
CONFIGURATION

Miscellaneous Analog Control (2Bh, R) Resource Assignment (2Ch, R)


External ES978 ES1879 AuxB control AuxA control Line control Mic control
ES1879 master 2 ES978 mappable
record I S volume I2S volume
volume mute mixer target 7 6 5 4 3 2 1 0
volume tracking control
7 6 5 4 3 2 1 0
Two bits per analog resource of the ES978 control
treatment of analog resources in both the ES1879 and
The I2S DAC volume can track the volume of the FM DAC
ES978 when docked.
when its own Mixer Volume Control register 6Dh is not
used. This is useful when the I2S interface is used for an This register is set to FFh by hardware reset, but not PnP
external wavetable synthesizer. Bit 3 of Vendor-Defined reset.
Card-Level register 2Bh when set high enables tracking Bit Definitions:
with FM volume.
Bits Name Description
This register is reset to 00h by hardware reset but not by 7:6 AuxB
PnP reset. control
Bit Definitions: 5:4 AuxA
control
Bits Name Description See Table 12 below.
7:6 External Common volume of mix with external record 3:2 Line
record sources. control
volume bit 7 bit 6 volume 1:0 Mic
0 0 0 dB (default) control
0 1 -1.5 dB
1 0 -3 dB Table 12 Resource Assignment
1 1 -4.5 dB Bit Values ES1879 ES978
5 ES1879 1 = ES1879 master volume mute disabled 00 Mute Mute
master when docked. 01 Mute Enabled: track corresponding
volume 0 = ES1879 master volume mute enabled 1879 Mixer register
mute when docked (default). 10 Enabled Mute
4 ES978 1 = ES978 I S volume tracks FM Mixer register
2 11 Enabled Enabled: track corresponding
I2S 36h of ES1879. 1879 Mixer register
volume 0 = ES978 I2S volume tracks I2S Mixer register
tracking 68h of ES1879.
3 ES1879 1 = ES1879 I2S volume controlled by FM Mixer
I2S register 36h.
volume 0 = ES1879 I2S volume controlled by I2S Mixer
control register 68h.
2:0 ES978 Assigns ES978 target for Mappable Mixer reg-
mappa- isters 5Dh (playback) and 5Fh (record).
ble mixer bit 2 bit 1 bit 0 ES978 target
target 0 0 0 None (default).
0 0 1 Mic.
0 1 0 Line.
0 1 1 Aux A.
1 0 0 Aux B.
1 0 1 I2S/ES689/ES69x interface.
1 1 0 Reserved.
1 1 1 Reserved.

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PRELIMINARY ES1879 DATA SHEET
CONFIGURATION

Power Management (2Dh, R/W) Logical Device Registers


IPROM PnP
x state disable Power Table 13 Logical Device Summary
flag
LDN # Device
7 6 5 4 3 2 1 0
LDN 0 (mandatory) Configuration device
After hardware reset or PnP reset, this register is set to 30h Activate; bit 0 is activate bit.
03h. Suspend and Resume operation requires 31h I/O Range Check.
programming register Audio_Base+7h.
60h I/O base address, bits 11:8. If zero, this device is
Bit Definitions: disabled. Eight locations.
Bits Name Description 61h I/O base address, bits 7:0.
7:4 – Don’t care. LDN 1 (mandatory) Audio device
3 IPROM Read-only. State of IPROM input pin. 30h Activate; bit 0 is activate bit.
state flag 1 = PnP data loaded from internal ROM. 31h I/O Range Check.
0 = PnP data loaded from external EEPROM.
60h I/O base address of audio microcontroller; bits
2 PnP 1 = PnP disable. The ES1879 will not respond 11:8. If zero, this device is not accessible. Sixteen
disable to PnP commands. locations.
0 = PnP enable. (Hardware reset default.)
61h I/O base address of audio microcontroller, bits
1:0 Power These bits set the power state of the ES1879. 7:0.
bit 1 bit 0 power state
0 0 Fully powered down. 62h I/O base address of FM alias, bits 11:8. If zero,
this device is not accessible. Four locations.
0 1 Oscillator enabled; everything else
is powered down. 63h I/O base address of FM alias, bits 7:0.
1 0 Low-power mode: analog enabled, 64h I/O base address of MPU-401, bits 11:8. If zero,
expansion interface enabled, MPU- this device is not accessible. MPU-401 may also
401 enabled, joystick enabled, I2S be accessible through LDN 3. Two locations.
interface enabled, PnP enabled.
65h I/O base address of MPU-401, bits 7:0.
DSP and ES689/69x serial inter-
faces are disabled, audio device 70h Interrupt Request Level Select 0.
and FM disabled. 71h Interrupt Request Type Select 0 (returns 2).
1 1 Fully powered up.
72h Interrupt Request Level Select 1.

EEPROM Serial Interface Data Port (2Eh, R/W) 73h Interrupt Request Type Select 1 (returns 2).

D D D D D D D D 74h DMA Channel Select 0 (default = 4).


7 6 5 4 3 2 1 0 75h DMA Channel Select 1 (default = 4).
LDN 2 (mandatory) Joystick device
EEPROM serial interface data port.
30h Activate; bit 0 is activate bit.

EEPROM Serial Interface Command Port (2Fh, R/W) 31h I/O Range Check.
60h I/O base address, bits 11:8. If zero, this device is
disabled. One location.
7 6 5 4 3 2 1 0
61h I/O base address, bits 7:0.
EEPROM serial interface command port. Reading from LDN 3 (optional) MPU-401 device
this port resets the EEPROM serial interface address. 30h Activate; bit 0 is activate bit.
31h I/O Range Check.
60h I/O base address, bits 11:8. If zero, this device is
disabled. Two locations.
61h I/O base address, bits 7:0.
70h Interrupt Request Level Select 0.
71h Interrupt Request Type Select 0 (returns 2).

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ES1879 DATA SHEET PRELIMINARY
CONFIGURATION

LDN 0: Configuration Device LDN 1: Audio Device


This device actually supports three functions: audio, FM,
Activate (30h, R/W) and MPU-401. Audio requires sixteen I/O locations, one
0 Activate interrupt that is shared with MPU-401, and two DMA
7 6 5 4 3 2 1 0 channels. FM requires four I/O locations. MPU-401
requires two I/O locations.
After reset or after a 1 is written to the reset bit in the card’s
configuration control bit, the default for this register is 0. Activate (30h, R/W)
Bit Definitions: 0 Activate
7 6 5 4 3 2 1 0
Bits Name Description
7:1 – Reserved. Always write 0. After reset or after a 1 is written to the reset bit in the card’s
0 Activate 1 = Activate. configuration control bit, the default for this register is 0.
0 = Deactivate (default).
Bit Definitions:
I/O Range Check (31h, R) Bits Name Description
0 Enable range check Pattern select 7:1 – Reserved. Always write 0.
7 6 5 4 3 2 1 0 0 Activate 1 = Activate.
0 = Deactivate (default).
This register verifies that the I/O range assigned to a logical
device does not conflict with the I/O range used by another I/O Range Check (31h, R)
device. 0 Enable range check Pattern select

Bit Definitions: 7 6 5 4 3 2 1 0

Bits Name Description


This register verifies that the I/O range assigned to a
7:2 – Reserved. Always write 0. logical device does not conflict with the I/O range used by
1 Enable 1 = Enable range check. another device.
range 0 = Disable.
check Bit Definitions:
0 Pattern 1 = 55h. Bits Name Description
select 0 = AAh. 7:2 – Reserved. Always write 0.
1 Enable 1 = Enable range check.
I/O Decoder 0 Base Address (60h, R/W) range 0 = Disable.
0 A[11:8] check
7 6 5 4 3 2 1 0 0 Pattern 1 = 55h.
select 0 = AAh.
This register is used to assign an I/O base address to I/O
decoder 0 of the logical device. I/O base address, bits Audio Microcontroller I/O Base Address (60h, R/W)
11:8. 0 A[11:8]
7 6 5 4 3 2 1 0
I/O Decoder 0 Base Address (61h, R/W)
A[7:3] 0 I/O base address of audio microcontroller, bits 11:8.
7 6 5 4 3 2 1 0 Sixteen locations.

I/O base address, bits 7:3. Audio Microcontroller I/O Base Address (61h, R/W)
A[7:4] 0
7 6 5 4 3 2 1 0

I/O base address of audio microcontroller, bits 7:4.

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PRELIMINARY ES1879 DATA SHEET
CONFIGURATION

FM Alias I/O Base Address (62h, R/W) Interrupt Request Type Select 1 (73h, R)
0 A[11:8] 0 0 0 0 0 0 1 0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

I/O base address of FM alias, bits 11:8. Four locations. Interrupt request type select 1. Returns 2 (low-to-high
transition).
FM Alias I/O Base Address (63h, R/W)
A[7:2] 0 DMA Channel Select 0 (74h, R)
7 6 5 4 3 2 1 0 0 Data
7 6 5 4 3 2 1 0
I/O base address of FM alias, bits 7:2.
Returns 4 (no DMA channel selected).
MPU-401 I/O Base Address (64h, R/W)
Bit Definitions:
0 A[11:8]
Bits Name Description
7 6 5 4 3 2 1 0
7:3 – Reserved. Always write 0.
I/O base address of MPU-401, bits 11:8. (MPU-401 may 2:0 Data Select which channel is in use for DMA 0.
also be accessible through LDN 3.) Two locations.
DMA Channel Select 1 (75h, R)
MPU-401 I/O Base Address (65h, R/W) 0 Data
A[7:2] 0 7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Returns 4 (no DMA channel selected).
I/O base address of MPU-401, bits 7:2. Bit Definitions:
Bits Name Description
Interrupt Request Level Select 0 (70h, R/W)
7:3 – Reserved. Always write 0.
0 Data
2:0 Data Select which channel is in use for DMA 1.
7 6 5 4 3 2 1 0

Interrupt request level select 0.


Bit Definitions:
Bits Name Description
7:4 – Reserved. Always write 0.
3:0 Data Select which interrupt level used for Interrupt 0.

Interrupt Request Type Select 0 (71h, R)


0 0 0 0 0 0 1 0
7 6 5 4 3 2 1 0

Interrupt request type select 0. Returns 2 (low-to-high


transition).

Interrupt Request Level Select 1 (72h, R/W)


0 Data
7 6 5 4 3 2 1 0

Interrupt request level select 1.


Bit Definitions:
Bits Name Description
7:4 – Reserved. Always write 0.
3:0 Data Select which interrupt level used for Interrupt 1.

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ES1879 DATA SHEET PRELIMINARY
CONFIGURATION

LDN 2: Joystick Device LDN 3: MPU-401 Device


The MPU-401, as an independent device, is optional;
Activate (30h, R/W) normally MPU-401 is part of the AudioDrive® solution.
0 Activate
7 6 5 4 3 2 1 0 Activate (30h, R/W)
0 Activate
After reset or after a 1 is written to the reset bit in the card’s 7 6 5 4 3 2 1 0
configuration control bit, the default for this register is 0.
Bit Definitions: After reset or after a 1 is written to the reset bit in the card’s
configuration control bit, the default for this register is 0.
Bits Name Description
7:1 – Reserved. Always write 0. Bit Definitions:
0 Activate 1 = Activate. Bits Name Description
0 = Deactivate (default). 7:1 – Reserved. Always write 0.
0 Activate 1 = Activate.
I/O Range Check (31h, R) 0 = Deactivate (default).
0 Enable range check Pattern select
7 6 5 4 3 2 1 0 I/O Range Check (31h, R)
0 Enable range check Pattern select
This register verifies that the I/O range assigned to a 7 6 5 4 3 2 1 0
logical device does not conflict with the I/O range used by
another device. This register verifies that the I/O range assigned to a
Bit Definitions: logical device does not conflict with the I/O range used by
another device.
Bits Name Description
7:2 – Reserved. Always write 0. Bit Definitions:
1 Enable 1 = Enable range check. Bits Name Description
range 0 = Disable. 7:2 – Reserved. Always write 0.
check 1 Enable 1 = Enable range check.
0 Pattern 1 = 55h. range 0 = Disable.
select 0 = AAh. check
0 Pattern 1 = 55h.
I/O Decoder 0 Base Address (60h, R/W) select 0 = AAh.
0 A[11:8]
7 6 5 4 3 2 1 0 I/O Decoder 0 Base Address (60h, R/W)
0 A[11:8]
I/O base address, bits 11:8. One location. 7 6 5 4 3 2 1 0

I/O Decoder 0 Base Address (61h, R/W) I/O base address, bits 11:8. Two locations.
A[7:0]
7 6 5 4 3 2 1 0 I/O Decoder 0 Base Address (61h, R/W)
A[7:0]
I/O base address, bits 7:0. 7 6 5 4 3 2 1 0

I/O base address, bits 7:0.

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PRELIMINARY ES1879 DATA SHEET
CONFIGURATION

Interrupt Request Level Select 0 (70h, R/W)


0 Data
7 6 5 4 3 2 1 0

Interrupt request level select 0.


Bit Definitions:
Bits Name Description
7:4 – Reserved. Always write 0.
3:0 Data Select which interrupt level used for Interrupt 0.

Interrupt Request Type Select 0 (71h, R)


0 0 0 0 0 0 1 0
7 6 5 4 3 2 1 0

Interrupt request type select 0. Returns 2 (low-to-high


transition).

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ES1879 DATA SHEET PRELIMINARY
I/O PORTS

I/O PORTS
Table 14 I/O Ports for Configuration, Audio, FM, MPU-401, and Joystick Devices
Port Read/Write Function
Configuration Device
Base+0h Read/write Configuration Register Address.
Base+1h Read/write Configuration Register Data.
Base+2h Read/write ES1879 GPO State register.
Base+3h Read/write ES978 GPO State register.
Base+4h Read-only ES1879 GPI Status register.
Base+5h Read-only ES978 GPI Status register.
Base+6h Read-only Interrupt Status register.
Base+7h Read/write Interrupt Mask register.
Audio Device
Base+0h - Base+3h Read/write 20-voice FM synthesizer. Address and data registers.
Base+4h Read/write Mixer Address register (port for address of mixer controller registers).
Base+5h Read/write Mixer Data register (port for data to/from mixer controller registers).
Base+6h Read/write Audio reset and status flags.
Base+7h Read/write Power Management register. Suspend request and FM reset.
Base+8h - Base+9h Read/write 11-voice FM synthesizer. Address and data registers.
Base+Ah Read-only Input data from read buffer for command/data I/O. Poll bit 7 of port Audio_Base+Eh to test
whether the read buffer contents are valid.
Base+Ch Read/write Output data to write buffer for command/data I/O. Read embedded microcontroller status.
Base+Eh Read-only Data available flag from embedded microcontroller.
Base+Fh Read/write Address for I/O access to FIFO in Extended mode.
FM Device
Base+0h - Base+3h Read/write 20-voice FM synthesizer. Address and data registers.
MPU-401 Device
Base+0h - Base+1h Read/write MPU-401 port (x=0,1, 2, or 3) if enabled.
Joystick Device
Base+0h Read/write Joystick.

Port Descriptions Configuration Register Data (Config_Base+1h, R/W)


This section describes the I/O ports in detail. D7 D6 D5 D4 D3 D2 D1 D0
7 6 5 4 3 2 1 0
Configuration Device
Logical device 0 is the configuration device. It has eight I/ Sets the PnP configuration data.
O Configuration Device ports assigned to it. Two of these
ports are used to access a set of Plug and Play registers ES1879 GPO State Register (Config_Base+2h, R/W)
that define I/O resources and activation controls for audio,
x GPO6 GPO5 GPO4 GPO3 GPO2 GPO1 GPO0
FM, MPU-401, and joystick devices.
7 6 5 4 3 2 1 0

Configuration Register Address (Config_Base+0h, R/W)


Sets the state of the ES1879 GPO pins that are not
A7 A6 A5 A4 A3 A2 A1 A0 mapped to GPI pins of the ES978.
7 6 5 4 3 2 1 0

Sets the PnP configuration address.

ESS Technology, Inc. SAM0025A-062397 41


PRELIMINARY ES1879 DATA SHEET
I/O PORTS

ES978 GPO State Register (Config_Base+3h, R/W) Interrupt Mask Register (Config_Base+7h, R/W)
x GPO6 GPO5 GPO4 GPO3 GPO2 GPO1 GPO0 x MPU-401 H/W vol Audio 2 Audio 1
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Sets the state of the ES978 GPO pins that are not mapped The mask bits of this register can be used to force the
to GPI pins of the ES1879. interrupt source to be zero without putting the interrupt pin
in a high-impedance state. Each bit is AND’d with the
ES1879 GPI Status Register (Config_Base+4h, R) corresponding interrupt source. Set to all ones by
x GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0
hardware reset.
7 6 5 4 3 2 1 0 Bits 3:0 are set high by hardware reset.
Bit Definitions:
ES1879 general-purpose input status (read-only).
Bits Name Description
ES978 GPI Status Register (Config_Base+5h, R) 7:4 – Don’t care.
x GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 3 MPU-401 MPU-401 interrupt mask bit.
7 6 5 4 3 2 1 0 2 H/W vol Hardware volume interrupt mask bit.
1 Audio 2 Audio 2 interrupt mask bit.
ES978 general-purpose input status (read-only). 0 Audio 1 Audio 1 interrupt mask bit.

Interrupt Status Register (Config_Base+6h, R)


Docked PnPOK H/W
PnP state MPU-401 Audio 2 Audio 1
status status volume
7 6 5 4 3 2 1 0

Read this register to find out which ES1879 interrupt


sources are active.
Bit Definitions:
Bits Name Description
7 Docked Current docking state (status; not an interrupt
status request).
6 PnPOK PnPOK status bit.
status
5:4 PnP state Shows the PnP state.
bit 5 bit 4 PnP state
0 0 wait-for-key
0 1 sleep
1 0 isolation
1 1 configure
3 MPU-401 MPU-401. MPU-401 receive interrupt request
AND’d with bit 6 of mixer register 64h.
2 H/W vol Hardware volume. Hardware volume interrupt
request AND’d with bit 1 of mixer register 64h.
1 Audio 2 Audio 2. Audio 2 interrupt request AND’d with
bit 6 of mixer register 7Ah.
0 Audio 1 Audio 1. Audio 1 interrupt request.

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ES1879 DATA SHEET PRELIMINARY
I/O PORTS

Audio Device Reset and Status Flags (Audio_Base+6h, R)


Digital
Act Act Act Serial MIDI FIFO SW
Mixer Address Register (Audio_Base+4h, R/W) flag 2 flag 1 flag 0 act flag
power
mode reset reset
status
x A6 A5 A4 A3 A2 A1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0

Bits 7:4 of port Audio_Base+6h can be used to monitor I/O


The ES1879 provides a means to read back the Mixer
activity to the ES1879.
Address register. Reading back this register is useful for a
“hot-key” application that needs to change the mixer while Bits 7:5 are set high after any read from port
preserving the address register. Audio_Base+6h. Then specific I/O activity can set these
bits low. When port Audio_Base+6h is read at a later time,
Mixer Data Register (Audio_Base+5h, R/W) these bits will indicate whether I/O activity has occurred
D7 D6 D5 D4 D3 D2 D1 D0
between the reads from Audio_Base+6h.
7 6 5 4 3 2 1 0 In addition, bit 4 can be used to indicate if the DSP or
ES689/ES69x serial interface is in use. Bit 4 is set high if
Reset and Status Flags (Audio_Base+6h, W) bit 7 or bit 5 of mixer register 48h is high (software serial
FIFO SW enable or serial reset). It is also set high if the ES689/
0
reset reset ES69x serial interface is active, which is a combination of
7 6 5 4 3 2 1 0 bit 4 of mixer register 48h set high and MCLK (ES689/
ES69x serial bit clock) being high periodically.
Bit Definitions:
Bit Definitions:
Bits Name Description
Bits Name Description
7:2 – Reserved. Always write 0.
7 Act flag 2 Set low by I/O reads/writes to MPU-401, Joy-
1 FIFO 1 = Hold ES1879 FIFO in reset. stick, Configuration devices, as well as PnP I/
reset 0 = Release ES1879 FIFO from reset. O activity (the last includes almost any I/O
Bit 1 has no function for Compatibility mode. write to 279h or A79h if IRPOM = 1).
0 SW 1 = Hold ES1879 in reset. 6 Act flag1 Set low by I/O reads/writes to audio ports
reset 0 = Release ES1879 from reset. Audio_Base+4h and Audio_Base+5h (mixer
ports).
5 Act flag 0 Set low by I/O writes to audio and FM ports
excepting Audio_Base+4h, Audio_Base+5h,
and Audio_Base+7h. Set low by I/O reads from
audio and FM ports excepting Audio_Base+4h,
Audio_Base+5h, Audio_Base+6h, and
Audio_Base+7h. Also set low by DMA
accesses to ES1879.
4 Serial 1 = Serial activity flag. High if DSP serial mode
act flag is enabled (SE input pin is high or bit 7 of Mixer
Extension register 48h is high) or if an external
ES689/ES69x is using MCLK/MSD to drive the
FM DACs.
3 Digital 1 = ES1879 digital audio is powered-up.
power 0 = ES1879 digital audio is currently powered
status down (power mode 0, 1, and 2).
2 MIDI 1 = The ES1879 is processing a MIDI com-
mode mand 30h, 31h, 34h, or 35h. In this mode, the
ES1879 is monitoring serial input. Powering-
down may cause a loss of data.
The ES1879 does not automatically wake up
on serial input on the MSI pin.
1 FIFO FIFO Reset bit.
reset
0 SW reset Software Reset bit.

ESS Technology, Inc. SAM0025A-062397 43


PRELIMINARY ES1879 DATA SHEET
I/O PORTS

Power Management Register (Audio_Base+7h, R/W) Read Data Register (Audio_Base+Ch, R)


FM D7 D6 D5 D4 D3 D2 D1 D0
Suspend
0 synth 0
request 7 6 5 4 3 2 1 0
reset
7 6 5 4 3 2 1 0
Bit Definitions:

Reading or writing port Audio_Base+7h does not Bits Name Description


automatically wake up the ES1879. 7 Busy flag 1 = write buffer not available or ES1879 busy.
0 = write buffer available or ES1879 not busy.
Bit Definitions:
6 1 = Data available in read buffer.
Bits Name Description 0 = Data not available in read buffer.
7 Suspend Pulse high, then low to request suspend. This flag is reset by a read from port
request Audio_Base+Ah.
6 – Reserved. Always write 0. 5 1 = Extended mode FIFO Full (256 bytes
5 FM synth 1 = Hold FM synthesizer in reset. loaded).
reset 0 = Release FM synthesizer from reset. 4 1 = Extended mode FIFO Empty (0 bytes
4:0 – Reserved. Always write 0. loaded).
3 1 = FIFO Half Empty, Extended mode flag.
Read Data Register (Audio_Base+Ah, R) 2 1 = ES1879 microcontroller generated an inter-
rupt request (e.g., from Compatibility mode
D7 D6 D5 D4 D3 D2 D1 D0
DMA complete).
7 6 5 4 3 2 1 0
1 1 = Interrupt request generated by FIFO Half
Empty flag change. Used by Programmed I/O
Reads data from embedded audio microcontroller. Poll bit interface to FIFO in Extended mode.
7 of port Audio_Base+Eh to test whether the register
0 1 = Interrupt request generated by DMA
contents are valid.
counter overflow in Extended mode.

Write Data Register (Audio_Base+Ch, W)


Read Buffer Status Register (Audio_Base+Eh, R)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0

Writes data to embedded audio microcontroller. Sets bit 7


A read from port Audio_Base+Eh will reset any interrupt
of port Audio_Base+Ch high (write buffer not available)
request.
until data is processed by the ES1879.
Bit Definitions:
Bits Name Description
7 1 = Data available in read buffer.
0 = Data not available in read buffer.
This flag is reset by a read from port
Audio_Base+Ah.

Programmed I/O Access to FIFO Register


(Audio_Base+Fh, R/W)
D7 D6 D5 D4 D3 D2 D1 D0
7 6 5 4 3 2 1 0

This port can be used to replace Extended mode DMA


with Programmed I/O.

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ES1879 DATA SHEET PRELIMINARY
I/O PORTS

FM Device MPU-401 Device


The FM synthesizer operates in two different modes:
Emulation mode and Native mode. In Emulation mode, the MPU-401 Data (MPU_Base+0h, R/W)
FM synthesizer is fully compatible with the OPL3 FM D7 D6 D5 D4 D3 D2 D1 D0
synthesizer. In Native mode, the FM synthesizer has 7 6 5 4 3 2 1 0
increased capabilities and performance for more realistic
music. The following register descriptions are for This register is used to read data from the MPU-401
Emulation mode only. receive FIFO or a command acknowledge byte (0FEh).
This register is also used to write data to the MPU-401
FM Status (FM_Base+0h, R) transmit FIFO.
IRQ FT1 FT2 0 0 0 0 0
7 6 5 4 3 2 1 0 MPU-401 Command (MPU_Base+1h, W)
D7 D6 D5 D4 D3 D2 D1 D0
Reading this register returns the overflow flags for timers 7 6 5 4 3 2 1 0
1 and 2 and the “interrupt request” from these timers (this
is not a real interrupt request but is supported as a status The MPU-401 device accepts only two commands:
flag for backward compatibility with the OPL3 FM
FFh Reset/return to Smart mode. This command
synthesizer).
generates an acknowledge byte if received
when already in Smart mode.
FM Low Bank Address (FM_Base+0h, W)
A7 A6 A5 A4 A3 A2 A1 A0
3Fh Go to UART mode. This command generates
an acknowledge byte if received while in
7 6 5 4 3 2 1 0
Smart mode. It is ignored if the device is
already in UART mode.
Low bank register address.
NOTE: Any write to this register will also put the FM MPU-401 Status (MPU_Base+1h, R)
synthesizer in Emulation mode if it is currently in Native -RR -TR x
mode.
7 6 5 4 3 2 1 0

FM Data Write (FM_Base+1h, W)


Bit Definitions:
D7 D6 D5 D4 D3 D2 D1 D0
Bits Name Description
7 6 5 4 3 2 1 0
7 -RR 0 = read data available in the receive FIFO, or
pending acknowledge byte to be read
FM register write. The data written to FM_Base+1h is
(0FEh).
written to the current address FM register. Note that
register writes must follow the timing requirements of the 6 -TR 0 = there is room in the transmit FIFO to accept
another byte.
OPL3 FM synthesizer.
5:0 – Don’t care.
FM High Bank Address (FM_Base+2h, W)
A7 A6 A5 A4 A3 A2 A1 A0
7 6 5 4 3 2 1 0

High bank register address.

FM Data Write (FM_Base+3h, W)


D7 D6 D5 D4 D3 D2 D1 D0
7 6 5 4 3 2 1 0

FM register write. Writing to this register in Emulation


mode is the same as writing to register FM_Base+1h.

ESS Technology, Inc. SAM0025A-062397 45


PRELIMINARY ES1879 DATA SHEET
I/O PORTS

Joystick Device
The joystick device uses only a single I/O port. The device
can function in one of two modes: Analog mode or Digital
mode. The use of this I/O port is different depending on the
mode. This section describes Analog mode. Digital mode
is described in the MPU-401/Joystick Interface section.

Joystick_Base+0h (W)
x x x x x x x x
7 6 5 4 3 2 1 0

Any value written to the Joystick_Base+0h port will restart


the timing sequence. This should be done before reading
the timer status flags.

Joystick_Base+0h (R)
SWD SWC SWB SWA TD TC TB TA
7 6 5 4 3 2 1 0

SW(A-D) return the current state of the joystick switch


inputs. T(A-D) return the current state of the four one-shot
timers connected to the X and Y resistors of the dual
joysticks.

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ES1879 DATA SHEET PRELIMINARY
PROGRAMMING THE ES1879

PROGRAMMING THE ES1879


Identifying the ES1879 In addition to performing actions on the above list, a
hardware reset will reset all Mixer registers to default
The ES1879 can be identified by reading Mixer Extension
values.
register 40h successfully.
Mixer Extension register 40h returns the following 8-bit Modes of Operation
values on four successive reads: The ES1879 can operate the first audio channel in one of
18h, 79h, A[11:8], A[7:0] two modes: Compatibility mode or Extended mode.
where 18h and 79h are data reads indicating the part In both modes, a set of mixer and controller registers
number (1879) and A[11:0] is the base address of the enables application software to control the analog mixer,
configuration device. Writing to the Mixer Address register record source, and output volume. Programming the
(Audio_Base+4h) resets the sequence so that the next ES1879 Enhanced Mixer is described later in this
read of 40h returns 18h. document. See “Programming the ES1879 Mixer” on
page 59.
Resetting the Audio Device via Software
Compatibility Mode Description
The ES1879 audio embedded microcontroller can be
reset in one of two ways: hardware reset or software reset. The first mode, Compatibility mode, is compatible with the
The hardware reset signal comes from the ISA bus. Sound Blaster Pro. This is the default mode after reset. In
Software reset is controlled by bit 0 of port this mode, the ES1879 microcontroller is an intermediary
Audio_Base+6h. in all functions between the ISA bus and the CODEC. The
ES1879 microcontroller performs limited FIFO functions
To reset the ES1879 audio microcontroller by software: using 64 bytes of internal memory.
1. Write a 1 to port Audio_Base+6h. Extended Mode Description
2. Delay a short period, for example, by reading back The ES1879 also supports an Extended mode of
Audio_Base+6h for 10 msecs. operation. In this case, a 256-byte FIFO is used as an
3. Write a 0 to port Audio_Base+6h. intermediary between the ISA bus and the ADC and DAC
4. In a loop that lasts at least 1 msec, poll port Control registers, and various Extended mode controller
Audio_Base+Eh bit 7=1 for read data available. registers are used for control. The ES1879 microcontroller
is mostly idle in this mode. DMA control is handled by
If bit 7=1, then read the byte from port Audio_Base+Ah.
dedicated logic. Programming for Extended mode
Exit the loop if the content is 0AAh; otherwise, continue
operation requires accessing various control registers with
polling.
ES1879 commands. Some of these commands are also
Both hardware reset and software reset will: useful for Compatibility mode, such as those that
configure DMA and IRQ channels.
‡ Disable Extended mode.
‡ Reset the timer divider and filter registers for 8 kHz
sampling.
‡ Stop any DMA in progress.
‡ Clear any active interrupt request.
‡ Disable voice input of mixer (see the D1h/ D3h
commands).
‡ Reset Compatibility mode and Extended mode DMA
counters to 2048 bytes.
‡ Set analog direction to be DAC, with the DAC value set to
mid-level.
‡ Set input volume for 8-bit recording with AGC (Automatic
Gain Control) to maximum.
‡ Set input volume for 16-bit recording to mid-range.

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Table 15 Comparison of Operation Modes


Compatibility Mode
Extended Mode
(Sound Blaster Pro)
Sound Blaster Pro-compatible Yes No
FIFO size 64 bytes (firmware managed) 256 bytes (hardware managed)
Mono 8-bit ADC, DAC Yes, to 44 kHz Yes, to 44 kHz
Mono 16-bit ADC, DAC Yes, to 22 kHz Yes, to 44 kHz
Stereo 8-bit DAC Yes, to 22 kHz Yes, to 44 kHz
Stereo 8-bit ADC Yes, to 22 kHz Yes, to 44 kHz
Stereo 16-bit DAC Yes, to 11 kHz Yes, to 44 kHz
Stereo 16-bit ADC No Yes, to 44 kHz
Signed/Unsigned Control No Yes
Automatic Gain Control during recording Firmware controlled, to 22 kHz, mono only No
Programmed I/O block transfer for ADC and DAC No Yes
FIFO status flags No Yes
Auto reload DMA Yes Yes
Time base for programmable timer 1 MHz or 1.5 MHz 800 kHz or 400 kHz
ADC and DAC jitter ± 2 microseconds None

Mixing Modes Not Recommended Sound Blaster Pro-Compatible Data Formats


Avoid mixing Extended mode commands with There are four formats available from combining the
Compatibility mode commands. The Audio 1 DAC Enable/ following two options:
Disable commands D1h and D3h are safe to use when
using Extended mode to process ADC or DAC. However,
‡ 8-bit or 16-bit
other Compatibility mode commands can cause problems. ‡ Mono or stereo
The Extended mode commands may be used to set up the The 8-bit samples are unsigned, ranging from 0h to 0FFh,
DMA or IRQ channels before entering Compatibility mode. with the DC levels around 80h.

Data Formats 16-bit samples are unsigned, ranging from 0000h to


0FFFFh, with the DC levels around 8000h.
This section briefly describes the different audio data
formats used by the ES1879. Stereo DMA Transfers in Compatibility Mode
Stereo DMA transfers are only available using DMA rather
Compressed Data Formats
than Direct mode commands.
The ES1879 supports two types of compressed sound
DAC operations: ESPCM®, which uses a variety of To perform a stereo DMA transfer, first set bit 1 of mixer
proprietary compression techniques developed by ESS register 0Eh high. Then set the timer divider to twice the
Technology, and ADPCM, which is supported by many per-channel sample rate.
other sound cards but is of a lower quality. The maximum stereo transfer rate for 8-bit data is 22 kHz
Both ADPCM and ESPCM® are only transferred using DMA per channel, so for this case, program the timer divider as
transfer. The first block of a multiple-block transfer uses a if it were for 44 kHz mono. The maximum stereo transfer
different command than subsequent blocks. The first byte rate for 16-bit data is 11 kHz per channel. Stereo ADC
of the first block is called the reference byte. transfers for 16-bit data are not allowed in Compatibility
mode.
Use Compatibility mode when transferring compressed
data. For 8-bit data, the ES1879 expects the first byte
transferred to be for the right channel, and subsequent
bytes to alternate left, right, etc.

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For 16-bit data, the ES1879 expects DMA transfers to be Commands such as D1h and D3h, which control the Audio
a multiple of 4, with repeating groups in the order: 1 DAC mixer input enable/disable status, and command
D0h, which suspends or pauses DMA, are acceptable to
1. Left low byte
send during this window.
2. Left high byte
The ES1879 chip sets the Busy flag when the command
3. Right low byte
window is no longer open. Application software must send
4. Right high byte a command within 13 microseconds after the Busy flag
goes high or the command will be confused with DMA
ES1879 Data Formats (Extended Mode and Audio 2)
data. Sending a command within the command window is
There are eight formats available from the combination of easy if polling is done with interrupts disabled.
the following three options:
As an example of sending a command during DMA,
‡ Mono or stereo consider the case where the application wants to send
‡ 8-bit or 16-bit command D0h in the middle of a DMA transfer. The
‡ Signed or unsigned application disables interrupts and polls the Busy flag.
Because of the FIFO and the rules used for determining
For stereo data, the data stream always alternates the command window, it is possible for the current DMA
channels in successive samples: first left, then right. For transfer to complete while waiting for the Busy flag to clear.
16-bit data, the low byte always precedes the high byte. In this event, the D0h command has no function, and a
Sending Commands During DMA Operations pending interrupt request from the DMA completion is
generated.
It is useful to understand the detailed operation of sending
a command during DMA. The interrupt request can be cleared by reading port
Audio_Base+Eh before enabling interrupts or by having a
The ES1879 uses the Audio 1 FIFO for DMA transfers to
way of signaling the interrupt handler that DMA is inactive
and from the CODEC. When the FIFO is full (in the case
so that it does not try to start a new DMA transfer.
of DAC) or empty (in the case of ADC), DMA requests are
temporarily suspended and the Busy flag (bit 7 of port Figure 17 shows timing considerations for sending a
Audio_Base+Ch) is cleared. This opens a window of command.
opportunity to send a command to the ES1879.

Busy Flag
13 µsec
Poll Busy
Write Command OK
Write Command NOT OK

Figure 17 Command Transfer Timing

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Compatibility Mode Programming 7. Delay approximately 100 milliseconds to allow the


analog circuits to settle, then enable the Audio 1 DAC
This section describes Compatibility mode programming.
input to mixer with command D1h.
Compatibility Mode DAC Operation 8. During DMA.
1. Reset For Auto-Initialize mode, it is not necessary to send any
Write 1h to port Audio_Base+6h. commands to the ES1879 at interrupt time, except to
read Audio_Base+Eh to clear the interrupt request.
To play a new sound without resetting the ES1879
beforehand when the status of the analog circuits is not For Normal mode, initialize the system DMA controller
clear, mute the input to the mixer with command D3h to with the address and count of the next block size if it
prevent pops. changes. Use command 48h. To start the next transfer,
use command D4h.
2. Enable stereo mode (optional).
Set bit 1 of mixer register 0Eh high. Use only DMA To stop DMA after the current auto-initialize block is
mode. Clear bit 1 of mixer register 0Eh after the DAC finished, use command D0h.
transfer. Commands such as D1h and D3h, which control the
3. Set sample rate and filter clock. Audio 1 DAC mixer input enable/disable status, and
command D0h, which suspends DMA, are acceptable
Use commands 40h or 41h to set the sample rate and
to send during DMA transfers. These commands can
filter clock divider. To set the filter clock to be
only be sent during certain windows of opportunity. See
independent from the sample rate, use command 42h
“Stereo DMA Transfers in Compatibility Mode” on
in addition to 40h or 41h.
page 48.
For stereo transfers, set the timer divider to twice the
9. After DMA is finished, restore the system interrupt
per-channel sample rate. The maximum stereo
controller and DMA controller to their idle state. Monitor
transfer rate for 8-bit data is 22 kHz per channel; so for
the FIFO Empty status flag in port Audio_Base+Ch to
this case, program the first timer divider as if you were
be sure that data transfer is completed. Delay 25
transferring data at 44 kHz mono. The maximum stereo
milliseconds to let the filter outputs settle to DC levels,
transfer rate for 16-bit data is 11 kHz per channel.
then disable the Audio 1 DAC input to the mixer with
4. Set the block size. Only use this command (48h) with command D3h.
High-Speed DMA transfer modes (commands 90h and 10.Issue another software reset to the ES1879 to initialize
91h). the appropriate registers.
5. Configure the system interrupt controller and system
DMA controller.
6. Start DMA.
Start the DMA transfer by sending the command for the
desired transfer type and data length. The
uncompressed modes are shown in Table 16. See
Table 28 for a description of the commands in addition
to the commands for DMA transfers of compressed
data.

Table 16 Uncompressed DAC Transfer Modes


DAC DMA Transfer Mode Data Length Command
Direct 8-bit 10h
16-bit 11h
DMA mode Normal 8-bit 14h
16-bit 15h
High-Speed 8-bit 91h
DMA mode Auto-Initialize 8-bit 1Ch
16-bit 1Dh
High-Speed 8-bit 90h

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Compatibility Mode ADC Operation 6. Set the block size. Only use this command (48h) with
ES1879 analog circuitry is switched from the DAC High-Speed DMA transfer modes (commands 98h and
direction to the ADC direction by the first direct or DMA 99h).
mode ADC command (2xh). Discard the first 25 to 100 7. Configure the system interrupt controller and system
milliseconds of samples because pops might occur in the DMA controller.
data due to the change from the DAC to ADC direction. In 8. Start DMA.
the ADC direction, the digital audio input to the mixer is
Start the DMA transfer by sending the command for the
automatically muted.
desired transfer type and data length. The
1. Reset uncompressed modes are shown in Table 17. See
Write 1h to port Audio_Base+6h. Table 28 for a description of the commands in addition
to the commands for DMA transfers of compressed
To play a new sound without resetting the ES1879 data.
beforehand when the status of the analog circuits is not
clear, mute the input to the mixer with command D3h to
prevent pops. Table 17 Uncompressed ADC Transfer Modes
ADC DMA Transfer Mode Data Length Command
2. Select the input source using register 0Ch
Direct 8-bit 20h
Sound Blaster Pro has three recording sources:
16-bit 21h
microphone, line, and auxiliary A (CD). Microphone
input is the default source after any reset. DMA mode Normal 8-bit 24h
16-bit 25h
The ES1879 has seven recording sources. Use mixer
register 1Ch to choose additional sources. High-Speed 8-bit 99h
DMA mode Auto-Initialize 8-bit 2Ch
3. Program the input volume.
16-bit 2Dh
The selected source passes through an input volume
stage that can be programmed with 16 levels of gain High-Speed 8-bit 98h
from 0 to +22.5 dB in steps of 1.5 dB. In 8-bit
recordings (other than High-Speed mode), the volume 9. Delay approximately 100 msec to allow the analog
stage is controlled by the ES1879 firmware for the circuits to settle, then enable the Audio 1 DAC input to
purposes of automatic gain control (AGC). In 16-bit mixer with command D1h.
recordings as well as High-Speed mode 8-bit 10.During DMA.
recordings, the input volume stage is controllable from
For Auto-Initialize mode, it is not necessary to send any
application software. Use command DDh to change
commands to the ES1879 at interrupt time, except to
the input volume level from 0 to 15. The reset default is
read Audio_Base+Eh to clear the interrupt request.
mid-range, 8.
For Normal mode, initialize the system DMA controller
4. Enable stereo mode (optional).
with the address and count of the next block size if it
Set bit 1 of mixer register 0Eh high. Use only DMA changes. Use command 48h. To start the next transfer,
mode. Clear bit 1 of mixer register 0Eh after the ADC use command D4h.
transfer.
To stop DMA after the current auto-initialize block is
5. Set sample rate and filter clock. finished, use command D0h.
Use commands 40h or 41h to set the sample rate and
Commands such as D0h, which suspends DMA, are
filter clock divider. If you want to set the filter clock to be
acceptable to send during DMA transfers. These
independent from the sample rate, use command 42h
commands can only be sent during certain windows of
in addition to 40h or 41h.
opportunity. See “Writing Commands to ES1879
For stereo transfers, set the timer divider to twice the Controller Registers” on page 52.
per-channel sample rate. The maximum stereo
11. After DMA is finished, restore the system interrupt
transfer rate for 8-bit data is 22 kHz per channel; so for
controller and DMA controller to their idle state. Monitor
this case, program the first timer divider as if you were
the FIFO Empty status flag in port Audio_Base+Ch to
transferring data at 44 kHz mono. The maximum stereo
be sure that data transfer is completed.
transfer rate for 16-bit data is 11 kHz per channel.
12.Issue another software reset to the ES1879 to initialize
the appropriate registers.

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The maximum sample rate for Direct mode ADC is 22 kHz. A4h, 00h; register A4h = 00h

The maximum sample rate for DMA ADC for both 8-bit and A5h, F8h; register A5h = F8h
16-bit is 22 kHz, using commands 24h, 25h, 2Ch, or 2Dh. NOTE: The port Audio_Base+Ch write buffer is shared
There is a special High-Speed mode for ADC that allows with Compatibility mode DMA write operations. When
DMA is active, the Busy flag is cleared during windows of
8-bit sampling up to 44 kHz. This mode uses commands
time when a command can be received. Normally, the only
98h (auto-initialize) and 99h (normal). No AGC is commands that should be sent during DMA operations are
performed as the input volume is controlled with command Dxh commands such as DMA pause/continue and Audio
DDh. 1 DAC enable/disable. In this situation, it is recommended
to disable interrupts between the time that the Busy bit is
Extended Mode Programming polled and the command is written. Also, minimize the time
This section describes Extended mode programming. between these instructions. See “Sending Commands
During DMA Operations” on page 49 for more information.
Commanding ES1879 Controller Registers Reading the Read Data Buffer of the ES1879
Controller registers are written to and read from using Command C0h is used to read the ES1879 controller
commands sent to ports Audio_Base+Ch and registers used for Extended mode. Send command C0h
Audio_Base+Ah. followed by the register number, Axh or Bxh. For example,
Commands of the format Axh, Bxh, and Cxh, where x is a to read register A4h, send the following command bytes:
numeric value, are used for Extended mode programming C0h, A4h
of the first audio channel.
Then poll the Read-Data-Buffer-Status bit, bit 7 of port
Commands of the format Ax and Bx are used to access Audio_Base+Eh, before reading the register contents of
the ES1879 controller registers. For convenience, the port Audio_Base+Ah.
registers are named after the commands used to access
The Read-Data-Buffer-Status flag can be polled by
them. For example “register A4h,” the Audio 1 Transfer
reading bit 7 of port Audio_Base+Eh. When a byte is
Count Reload (low-byte) register, is written to by
available, the bit is set high.
“command A4h.”
NOTE: Any read of port Audio_Base+Eh also clears any
Enabling Extended Mode Commands active interrupt request from the ES1879. An alternate
After any reset and before using any Extended mode way of polling the Read-Data-Buffer-Status bit is through
commands, first send command C6h to enable Extended bit 6 of port Audio_Base+Ch, which is the same flag. The
mode commands. Read-Data-Buffer-Status flag is cleared automatically by
reading the byte from port Audio_Base+Ah.
ES1879 Command/Data Handshaking Protocol
This section describes how to write commands to and read
data from the ES1879 controller registers.
Writing Commands to ES1879 Controller Registers
Commands written to the ES1879 enter a write buffer.
Before writing the command, make sure the buffer is not
busy.
Bit 7 of port Audio_Base+Ch is the ES1879 Busy flag. It is
set when the write buffer is full or when the ES1879 is
otherwise busy (for example, during initialization after
reset or during Compatibility mode DMA requests).
To write a command or data byte to the ES1879
microcontroller:
1. Poll bit 7 of port Audio_Base+Ch until it is clear.
2. Write the command/data byte to port Audio_Base+Ch.
The following is an example of writing to ES1879 controller
registers. To set up the Audio 1 Transfer Count Reload
register to F800h, send the following command/data
bytes:

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Extended Mode Audio 1 DAC Operation


Follow the steps below to program the first audio channel Table 18 Command Sequences for DMA Playback
for Extended mode DAC operation. Mono Stereo 8-bits 16-bits Unsigned Signed Sequence
1. Reset: X X X Reg B6h = 80h
Reg B7h = 51h
Write 3h to port Audio_Base+6h, instead of 1h as in Reg B7h = D0h
Compatibility mode. Bit 1 high specifically clears the
X X X Reg B6h = 00h
FIFO. The remainder of the software reset is identical
Reg B7h = 71h
to Compatibility mode. Reset disables the Audio 1 DAC Reg B7h = F0h
input to the mixer. This is intended to mask any pops
X X X Reg B6h = 80h
created during the setup of the DMA transfer.
Reg B7h = 51h
2. After the reset, send command C6h to enable Reg B7h = D4h
Extended mode commands. X X X Reg B6h = 00h
3. Program direction and type: registers B8h, A8h, and Reg B7h = 71h
Reg B7h = F4h
B9h:
X X X Reg B6h = 80h
Register B8h: Set bit 2 low for Normal DMA mode, high
Reg B7h = 51h
for Auto-Initialize DMA mode. Leave bit 3 low for the Reg B7h = 98h
CODEC to run in the DAC direction.
X X X Reg B6h = 00h
Register A8h: Read this register to preserve the bits Reg B7h = 71h
and then modify only bits 1 and 0: Reg B7h = B8h
X X X Reg B6h = 80h
Bits 1:0 10: Mono
Reg B7h = 51h
01: Stereo Reg B7h = 9Ch
X X X Reg B6h = 00h
Set register B9h:
Reg B7h = 71h
Bits 1:0 00: Single transfer DMA. Reg B7h = BCh

01: Demand transfer DMA:


2 bytes per DMA request. 6. Set DMA control registers B1h and B2h:
10: Demand transfer DMA: Register B1h: Interrupt Configuration register.
4 bytes per DMA request. Make sure bit 6 is high. Clear bits 7 and 5.

4. Clocks and counters: registers A1h, A2h, A4h and A5h: Register B2h: DRQ Configuration register.
Make sure bit 6 is high. Clear bits 7 and 5.
Register A1h: Audio 1 Sample Rate Generator.
Register A2h: Audio 1 Filter Clock Divider. 7. Configure system interrupt controller and DMA
Registers A4h/A5h: Audio 1 Transfer Count Reload controller.
register, low/high byte, two's complement. 8. To start DMA:
5. Initialize and configure DACs: registers B6h and B7h: Set bit 0 of register B8h high while preserving all other
See Table 18. bits.
Register B6h: Write 80h for signed data and 00h for 9. Delay approximately 100 milliseconds to allow analog
unsigned data. This also initializes the CODEC for circuits to settle, then enable the Audio 1 DAC input to
DAC transfer. mixer with command D1h.
Register B7h: Programs the FIFO (16-bit/8-bit, signed/ 10.During DMA:
unsigned, stereo/mono). The first command sent to For Auto-Initialize mode DMA transfers, read
register B7h prevents pops. Audio_Base+Eh to clear the interrupt request. Do not
send any other commands to the ES1879 at interrupt
time.

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For Normal mode, initialize the system DMA controller 5. Program direction and type: registers B8h, A8h, and
with the address and count of the next block to transfer. B9h:
Update the ES1879 Transfer Count registers if the Register B8h: Set bit 3 high to program the CODEC for
count is changed. To start the next transfer, clear bit 0 the ADC direction. Set bit 2 low for Normal DMA mode,
of register B8h, then set it high again. high for Auto-Initialize DMA mode.
To stop a DMA transaction in progress, clear bit 0 of At this point, the direction of the analog circuits is ADC
register B8h. To stop a DMA transaction after the rather than DAC. Unless the recording monitor is
current auto-initialize block is finished, clear bit 2 of enabled, there will be no output from AOUT_L or
register B8h, wait for the interrupt, and then clear bit 0 AOUT_R until the direction is restored to DAC.
of register B8h.
Register A8h: Read this register first to preserve the
11. After DMA is finished: bits and modify only bits 3, 1, and 0:
Restore the system interrupt controller and DMA
Bits 1:0 10: Mono
controller to their idle state. Monitor the FIFO Empty
status flag in port Audio_Base+Ch to be sure data 01: Stereo
transfer is completed. A delay of 25 milliseconds is
Bit 3 0: Disable Record Monitor for now.
required to let the filter outputs settle to DC levels, then
disable the first DMA DAC input to the mixer with Register B9h:
command D3h.
Bits 1:0 00: Single transfer DMA.
12.To conclude:
01: Demand transfer:
Issue another software reset to the ES1879 to initialize 2 bytes per DMA request.
the appropriate registers.
10: Demand Transfer:
Extended Mode Audio 1 ADC Operation 4 bytes per DMA request.
Follow the steps below to program the first audio channel 6. Clocks and counters: registers A1h, A2h, A4h, and
for Extended mode ADC operation: A5h:
NOTE: In Extended mode, there is no Automatic Gain Register A1h: Audio 1 Sample Rate Generator. Set bit
Control (AGC) performed while recording. If AGC is 7 high for sample rates greater than 22 kHz.
necessary, use 16-bit recordings and perform AGC in
system software. Register A2h: Audio 1 Filter Clock Divider.
1. Reset: Registers A4h/A5h: Audio 1 Transfer Count Reload
Write 3h to port Audio_Base+6h instead of 1h as in register (low/high byte, two's complement).
Compatibility mode. Bit 1 high specifically clears the 7. Enable Record Monitor if desired:
FIFO. The remainder of the software reset is identical
Register A8h bit 3 = 1: Enable Record Monitor
to Compatibility mode. Reset disables the Audio 1 DAC
(optional).
input to the mixer. This is intended to mask any pops
created during the setup of the DMA transfer. 8. Initialize and configure ADC: register B7h. See Table
19.
2. Send command C6h to enable Extended mode
commands. Register B7h: programs the FIFO (16-bit/8-bit, signed/
unsigned, stereo/mono). The first command sent to
3. Select the input source:
register B7h initializes the DAC and prevents pops.
The ES1879 has seven recording sources. Select the
source using the mixer control register 1Ch.
4. Program input volume register B4h.

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14.After DMA is finished:


Table 19 Command Sequences for DMA Record Restore the system interrupt controller and DMA
Mono Stereo 8-bits 16-bits Unsigned Signed Sequence controller to their idle state.
X X X Reg B7h = 51h 15.To conclude:
Reg B7h = D0h
Issue another software reset to the ES1879 to initialize
X X X Reg B7h = 71h
the appropriate registers. This returns the ES1879 to
Reg B7h = F0h
the DAC direction and turns off the record monitor.
X X X Reg B7h = 51h
Reg B7h = D4h Extended Mode Programmed I/O Operation
X X X Reg B7h = 71h The REP OUTSB instruction of the 80x86 family transfers
Reg B7h = F4h data from memory to an I/O port specified by the DX
X X X Reg B7h = 51h register. The REP INSB instruction is the complementary
Reg B7h = 98h function. Use ES1879 port Audio_Base+Fh for block
X X X Reg B7h = 71h transfers.
Reg B7h = B8h
I/O transfers to FIFO are nearly identical to the DMA
X X X Reg B7h = 51h
process, except that an I/O access to port Audio_Base+Fh
Reg B7h = 9Ch
replaces the DMA cycle. Some differences are described
X X X Reg B7h = 71h here.
Reg B7h = BCh
To program in this mode, it is useful to understand how the
9. Set DMA control registers B1h and B2h: FIFO Half-Empty flag generates an interrupt request. An
Register B1h: Interrupt Configuration register. interrupt request is generated on the rising edge of the
Verify that bit 6 is high. Clear bits 7 and 5. FIFO Half-Empty flag. This flag can be polled by reading
Register B2h: DRQ Configuration register. port Audio_Base+Ch. The meaning of this flag depends
Verify that bit 6 is high. Clear bits 7 and 5. on the direction of the transfer:

10.Configure system interrupt controller and DMA DAC FIFOHE flag is set high if 0-127 bytes in FIFO
controller. ADC FIFOHE flag is set high if 128-256 bytes in FIFO
11. To start DMA: Therefore, for DAC operations, an interrupt request is
Set bit 0 of register B8h high. Leave other bits generated when the number of bytes in the FIFO changes
unchanged. from >= 128 to < 128. This indicates to the system
processor that 128 bytes can be safely transferred without
12.Delay approximately 100 milliseconds to allow analog over filling the FIFO. Before the first interrupt can be
circuits to settle. generated, the FIFO needs to be primed, or filled, with
13.During DMA: more than 128 bytes. Keep in mind that data may be taken
For Auto-Initialize mode DMA transfers, do not send out of the FIFO while it is being filled by the system
any commands to the ES1879 at interrupt time, except processor. If that is the case, there may never be >= 128
for reading Audio_Base+Eh to clear the interrupt bytes in the FIFO unless somewhat more than 128 bytes
request. is transferred. Polling the ES1879 FIFOHE flag to be sure
it goes low in the interrupt handler (or when priming the
For Normal mode, initialize the system DMA controller FIFO) and perhaps sending a second block of 128 bytes
with the address and count of the next block to transfer. is a solution to this problem.
Update the ES1879 Transfer Count registers if the
count is changed. To start the next transfer, clear bit 0 For ADC, the interrupt request is generated when the
of register B8h, then set it high again. number of bytes in the FIFO changes from < 128 to >=
128, indicating that the system processor can safely read
To stop a DMA transaction in progress, clear bit 0 of 128 bytes from the FIFO. Before the first interrupt can be
register B8h. To stop a DMA transaction after the generated, the FIFO should be emptied (or mostly so) by
current auto-initialize block is finished, clear bit 2 of reading from Audio_Base+Fh and polling the FIFOHE
register B8h, wait for the interrupt, and then clear bit 0 flag. It is not safe to use FIFO reset bit 1 of port
of register B8h. Audio_Base+6h indiscriminately to clear the FIFO,
because it may get ADC data out of sync.
As in DMA mode, bit 0 of register B8h enables transfers
between the system and the FIFO inside the ES1879.

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PRELIMINARY ES1879 DATA SHEET
PROGRAMMING THE ES1879

NOTE: The ES1879 is designed for I/O block transfer up 3. Program transfer type: register 78h:
to an ISA bus speed of 8.33 MHz. Register 78h: Set bit 4 low for Normal DMA mode, high
Programmed I/O DAC Operation for Auto-Initialize DMA mode.
Programmed I/O DAC operation is done just as explained Bits 7:6 00: Single transfer DMA.
under “Extended Mode Audio 1 DAC Operation” on
page 53 with the following exceptions: 01: Demand transfer DMA:
2 bytes per DMA request.
‡ In step 3, programming register B9h is
unnecessary. 10: Demand transfer DMA:
4 bytes per DMA request.
‡ In step 6, leave bits 7:5 of register B2h low. Set bit
5 of register B1h high to enable an interrupt on FIFO 11: Demand transfer DMA:
half-empty transitions. Keep bit 6 of register B1h 8 bytes per DMA request.
low. 4. Clocks and counters: registers 70h, 72h, 74h, and 76h:
‡ In step 8, in addition to setting bit 0 of register B8h Register 70h: Audio 2 Sample Rate Generator.
high, send the REP OUTSB command. Register 72h: Audio 2 Filter Clock Divider.
Programmed I/O ADC Operation Registers 74h/76h: Audio 2 Transfer Count Reload
Programmed I/O ADC operation is done just as explained register ( low/high byte, two's complement).
under “Extended Mode Audio 1 ADC Operation” on NOTE: Registers 70h and 72h are slaved to registers A1h
page 54 with the following exceptions: and A2h unless Asynchronous mode is enabled (set bit 1
of register 71h).
‡ In step 5, programming register B9h is
unnecessary. 5. Initialize and configure DAC: register 7Ah:
‡ In step 9, leave bits 7:5 of register B2h low. Set bit Register 7Ah:
5 of register B1h high to enable an interrupt on FIFO Bit 2: Set high for signed, low for unsigned.
half-empty transitions. Keep bit 6 of register B1h
low. Bit 1: Set high for stereo data, low for mono.
‡ In step 11, in addition to setting bit 0 of register B8h Bit 0: Set high for 16-bit samples, low for 8-bit.
high, send the REP OUTSB command.
6. Set DMA and IRQ control registers B2h and 7Ah:
Second Audio Channel DAC Operation Register B2h: DRQ Configuration register.
Follow the steps below to program the second audio Verify that bit 6 is high. Clear bits 7 and 5.
channel for DAC operation. Register 7Ah: Audio 2 Control 2 register.
1. Reset: Bit 6 enables the audio 2 interrupt request.
Write 3h to port Audio_Base+6h, instead of 1h as in 7. Configure system interrupt controller and DMA
Compatibility mode. Bit 1 high specifically clears the controller.
FIFO. The remainder of the software reset is identical 8. To start DMA:
to Compatibility mode. On reset, the playback mixer
volume for the second audio channel is set to zero, Set bits 1:0 of register 78h high.
register 7Ch. This masks any pops that might occur 9. Delay approximately 100 milliseconds to allow analog
during the setup process. circuits to settle, then set the Audio 2 DAC playback
2. Send command C6h to enable Extended mode volume, register 7Ch.
commands. 10.During DMA:
For Auto-Initialize mode DMA transfers, read
Audio_Base+Eh to clear the interrupt request. Do not
send any other commands to the ES1879 at interrupt
time.
For Normal mode, initialize the system DMA controller
with the address and count of the next block to transfer.
Update the ES1879 Transfer Count registers if the
count is changed. To start the next transfer, clear bits
1:0 of register 78h, then set the bits high again.

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PROGRAMMING THE ES1879

To stop a DMA transaction in progress, clear bit 0 of The recommended method is as follows:
register B8h. To stop a DMA transaction after the
Program both DMA controllers for Auto-Initialize DMA
current auto-initialize block is finished, clear bit 4 of
within separate circular buffers of the same size, N.
register 78h, wait for the interrupt, and then clear bits
1:0 of register 78h. To exit full-duplex mode, clear bits 0 and 1 of mixer register
78h.
11. After DMA is finished:
Restore the system interrupt controller and DMA 1. Reset:
controller to their idle state. Monitor the FIFO Empty Write 3h to port Audio_Base+6h, instead of 1h as in
status flag in port Audio_Base+Ch to be sure data Compatibility mode. Bit 1 high specifically clears the
transfer is completed. A delay of 25 milliseconds is FIFO. The remainder of the software reset is identical
required to let the filter outputs settle to DC levels, then to Compatibility mode. Reset disables the Audio 1 DAC
disable the Audio 2 DAC input to the mixer. input to the mixer. This masks any pops created during
the setup of the DMA transfer.
12.To conclude:
Issue another software reset to the ES1879 to initialize 2. After the reset, send command C6h to enable
the appropriate registers. Extended mode commands.
3. Program direction and type: registers B8h, A8h, and
Full-Duplex DMA Mode (No DSP Serial Port) B9h:
The ES1879 supports stereo full-duplex DMA. In full- Register B8h: Set bit 2 high for Auto-Initialize DMA
duplex (FD) mode, a second audio channel has been mode. Leave bit 3 low to program the CODEC for the
added to the ES1879. The second audio channel is DAC direction.
programmed through mixer registers.
Register A8h: Read this register first to preserve the
Program the first audio channel as in “Extended Mode bits and modify only bits 3, 1, and 0:
Audio 1 ADC Operation” on page 54. Mixer registers A1h
and A2h can define the sample rate and filter frequency for Bits 1:0 10: Mono
both record and playback. In other words, the record and 01: Stereo
playback are at the same sample rate (synchronous). The
rate for playback can be set independently when bit 1 of Bit 3 0: Disable Record Monitor for now.
mixer register 71h is set high. This is Asynchronous mode. Register B9h:
Set the sample rate and filter frequency with mixer
registers 70h and 72h. When bit 1 of mixer register 71h is Bits 1:0 00: Single transfer DMA.
low, the default state, the converters are in Synchronous 01: Demand transfer DMA:
mode. 2 bytes per DMA request.
Program the second audio channel second. Mixer 10: Demand transfer DMA:
registers 74h and 76h are set to the two's complement 4 bytes per DMA request.
DMA transfer count. The second audio channel supports
both Auto-Initialize DMA and Normal DMA modes. The 4. Clocks and counters: registers A1h, A2h, A4h, and
playback buffer in system memory does not have to be the A5h:
same size as the record buffer. When the DMA transfer Register A1h: Audio 1 Sample Rate Generator.
count rolls over to zero, it can generate an interrupt that is Register A2h: Audio 1 Filter Clock Divider.
independent of the interrupt generated by the first audio Registers A4h/A5h: Audio 1 Transfer Count Reload
channel. register (low/high byte, two's complement).
If the record and playback buffers are the same size, then 5. Initialize and configure DAC: registers B6h and B7h:
a single interrupt can be used. Program the DMA Transfer Register B6h: Write 80h for signed data and 00h for
Count Reload registers (A4h, A5h, 74h, and 76h) with the unsigned data. This also initializes the CODEC for
same value for both channels. Enable the second audio DAC transfer.
channel before enabling the record channel. For example,
assume there are two half-buffers in a circular buffer. Register B7h: Set the data format for 16-bit mono. See
When the record channel completes filling the first half, it Table 18, “Command Sequences for DMA Playback”
generates an interrupt. To ensure that the playback on page 53.
channel is not accessing the first half at the time of the
interrupt, start the playback channel first. It has a 32-word
FIFO that fills quickly through DMA.

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PRELIMINARY ES1879 DATA SHEET
PROGRAMMING THE ES1879

6. Program transfer type: register 78h: 13.After bit 7 of register 7Ah goes high, enable recording
Register 78h: Set bit 4 high for Auto-Initialize DMA by setting bit 7 of register B7h and bit 0 of register B8h.
mode. 14.As usual, discard the first 50 to 100 milliseconds of
recorded data until analog circuits have settled. Set the
Bits 7:6 00: Single transfer DMA.
audio 2 playback volume, register 7Ch.
01: Demand transfer DMA:
15.During DMA:
2 bytes per DMA request.
For Auto-Initialize mode DMA transfers, read
10: Demand transfer DMA:
Audio_Base+Eh to clear the interrupt request. Do not
4 bytes per DMA request.
send any other commands to the ES1879 at interrupt
11: Demand transfer DMA: time.
8 bytes per DMA request.
For Normal mode, initialize the system DMA controller
7. Clocks and counters: registers 70h, 72h, 74h, and 76h:
with the address and count of the next block to transfer.
Set the sample rate the same as in A1h. Set the Update the ES1879 Transfer Count registers if the
Transfer Count Reload to 64 bytes. count is changed. To start the next transfer in the
Register 70h: Audio 2 Sample Rate Generator. playback channel (Audio 2), clear bits 1:0 of register
Register 72h: Audio 2 Filter Clock Divider. 78h, then set the bits high again. To start the next
Registers 74h/76h: Audio 2 Transfer Count Reload transfer in the record channel (Audio 1), clear bit 0 of
register (low/high byte, two's complement). register B8h, then set it high again

NOTE: Registers 70h and 72h are slaved to registers A1h To stop a DMA transaction in progress, clear bit 0 of
and A2h unless Asynchronous mode is enabled (set bit 1 register B8h. To stop a DMA transaction in the
of register 71h). playback channel (Audio 2) after the current auto-
initialize block is finished, clear bit 4 of register 78h,
8. Initialize and configure DAC: register 7Ah:
wait for the interrupt, and then clear bits 1:0 of register
Register 7Ah: 78h. To stop a DMA transaction in the record channel
Bit 2: Set high for signed, low for unsigned. (Audio 1) after the current auto-initialize block is
finished, clear bit 2 of register B8h, wait for the
Bit 1: Set high for stereo data, low for mono. interrupt, and then clear bit 0 of register B8h.
Bit 0: Set high for 16-bit samples, low for 8-bit. 16.After DMA is finished:
9. Set DMA and IRQ control registers B1h, B2h and 7Ah: Restore the system interrupt controller and DMA
Register B1h: Interrupt Configuration register. controller to their idle state. Monitor the FIFO Empty
Make sure bit 6 is high. Clear bits 7 and 5. status flag in port Audio_Base+Ch to be sure data
transfer is completed. A delay of 25 milliseconds is
Register B2h: DRQ Configuration register. required to let the filter outputs settle to DC levels, then
Verify that bit 6 is high. Clear bits 7 and 5. disable the Audio 2 DAC input to the mixer.
Register 7Ah: Audio 2 Control 2 register. 17.To conclude:
Bit 6 enables the audio 2 interrupt request.
Issue another software reset to the ES1879 to initialize
10.Configure system interrupt controller and DMA the appropriate registers.
controller.
11. Set bit 0 of register 78h. Since the playback FIFO is
presumably empty, the value zero is transferred to the
playback DAC at each sample clock. A click or pop
may be heard when full-duplex is enabled. To prevent
this, use command D1h to enable the Audio 1 DAC
input to the mixer after an approximate delay of 25
milliseconds.
12.Enable playback DMA by setting bit 1 of register 78h.
After 64 bytes are transferred, bit 7 of 7Ah should go
high. Poll this bit with a suitable time-out of 10
milliseconds.

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PROGRAMMING THE ES1879

Programming the ES1879 Mixer If you write or read using address 14h instead of 04h, you
have direct access to all 8 bits of this Mixer register.
The ES1879 has a set of mixer registers that are backward
compatible with the Sound Blaster Pro. However, some of Extended Access to Mic Mix Volume
the registers have an “extended” or “alternate” way of
If Sound Blaster Compatibility mode register address 0Ah
accessing the registers to provide for greater functionality.
is used to control Mic Mix Volume, only bits 2 and 1 are
Commanding the ES1879 Mixer Registers significant. Bit 0 is stuck high on reads and stuck low on
There are two I/O addresses used by the mixer: writes. Furthermore, this is a mono control, which prevents
Audio_Base+4h is the address port; Audio_Base+5h is panning.
the data port. In the Sound Blaster Pro, Audio_Base+4h is For extended access, use register address 1Ah instead.
write only, while Audio_Base+5h is read/write. Register 1Ah offers 4 bits/channel for pan control of the
Writing Data to the ES1879 Mixer Registers mono microphone input to the mixer.
To set a mixer register, write its address to Access to this register via address 0Ah is mapped as
Audio_Base+4h, then write the data to Audio_Base+5h. follows:
Reading Data from the ES1879 Mixer Registers
Write to 0Ah D2=0, D1=0 Mic Mix Volume = 00h
To read a mixer register, write its address to
D2=0, D1=1 Mic Mix Volume = 55h
Audio_Base+4h, then read the data from Audio_Base+5.
D2=1, D1=0 Mic Mix Volume = AAh
Resetting the Mixer Registers
D2=1, D1=1 Mic Mix Volume = FFh
The Mixer registers are not affected by software reset. To
Read from D2 = Mic Mix Volume register bit 3
reset the registers to initial conditions, write any value to
0Ah D1 = Mic Mix Volume register bit 2
mixer register 00h:
D0 = 1
1. Write 00h to Audio_Base+4h (select mixer register
00h). Others are undefined.
2. Write 00h to Audio_Base+5h (write 00h to the selected
mixer register).

Extended Access to SB Pro Mixer Volume Controls


The Sound Blaster Pro mixer volume controls are mostly
3 bits per channel. Bits 0 and 4 are always high when read.
The ES1879 offers an alternative way to write each Mixer
register. Use the “Extended Access” registers for volume
control of 4 bits/channel. If the Sound Blaster Pro-
compatible interface is used, bits 0 and 4 are cleared by a
write and forced high on all reads. See Table 20 for a list
of Sound Blaster Pro registers and the extended access
counterparts.

Table 20 Sound Blaster Pro/Extended Access Registers


Extended Access Register
Register Function
for 4 Bits/Channel
04h DAC Volume 14h
22h Master Volume 32h
26h FM Volume 36h
28h CD (Aux) Volume 38h
2Eh Line Volume 3Eh

For example, if you write 00h to Sound Blaster Pro register


04h, you will read back 11h because bits 0 and 4 are “stuck
high” on reads. Inside the register, these bits are “stuck
low,” so that writing 00h is the same as writing 11h.

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PRELIMINARY ES1879 DATA SHEET
PROGRAMMING THE ES1879

Extended Access to ADC Source Select Record and Playback Mixer


In Sound Blaster Compatibility mode in the Sound Blaster The ES1879 has stereo mixers for record and playback.
Pro mixer, there are three choices for recording source, Each stereo mixer has eight input sources, each with
set by bits 2 and 1 of Mixer register 0Ch. Note that bit 0 is independent 4-bit left and right volume controls, plus an
set to 0 upon any write to 0Ch and set to 1 upon any read input source from the ES978. For each 4-bit volume
from 0Ch: control, level 0 is mute and level 15 is maximum volume.
The ES1879 mixers use a dual-slope method for selecting
D2 D1 Source Selected volume. Each increase of one step in volume from settings
0 0 Microphone (default) 1 to 8 results in a +3 dB increase. Each increase of one
step in volume from settings 8 to 15 results in a +1.5 dB
0 1 CD (Aux) input
increase.
1 0 Microphone
Extended Access Mixer Volume Values
1 1 Line input
Volume in decibels (dB)
For extended access, use register address 1Ch to select
Mic,
recording from the mixer as follows: 4-bit Audio 1a, AuxA, AuxB,
Music DAC,
Value Audio 2b Line
I2Sc
D2 D1 D0 Source Selected
15 0 + 12.0 + 4.5
0 0 0 Microphone (default)
14 - 1.5 + 10.5 + 3.0
0 0 1 Left channel: microphone (not mixed with
ES978 mic). 13 - 3.0 + 9.0 + 1.5
Right channel: master volume inputsa (left 12 - 4.5 + 7.5 0
and right).
11 - 6.0 + 6.0 - 1.5
0 1 0 CD (Aux) input
10 - 7.5 + 4.5 - 3.0
0 1 1 Left channel: AOUTL
9 - 9.0 + 3.0 - 4.5
Right channel: AOUTR
8 - 10.5 + 1.5 - 6.0
1 0 0 Microphone
7 - 13.5 - 1.5 - 9.0
1 0 1 Record mixer
6 - 16.5 - 4.5 - 12.0
1 1 0 Line input
5 - 19.5 - 7.5 - 15.0
1 1 1 Master volume inputs.a
4 - 22.5 - 10.5 - 18.0
a.The master volume inputs are the outputs of 3 - 25.5 - 13.5 - 21.0
the Spatializer processor, before master vol-
2 - 28.5 - 16.5 - 24.0
ume is applied.
1 - 31.5 - 19.5 - 27.0
NOTE: Unless specifically stated, any of the above 0 mute mute mute
sources may have audio from the ES978 mixed in.
a.Audio 1 DAC mixer input is gated by Sound
In addition to mixer registers 0Ch and 1Ch, the ES1879 Blaster “Speaker On” control. This control bit is
has a separate mixer register for selecting the record toggled by the D1 (on) and D3 (off) Sound Blast-
source during DSP serial mode. er commands.
b.In Telegaming mode (enabled by bit 0 of mixer
register 48h when in serial mode), the audio 2
DAC mixer input volume is slaved to the audio 1
DAC mixer input volume.
c. Alternatively, the I2S DAC volume can be set by
the volume of the FM DAC at register 36h. This
is useful when the I2S interface is used for an ex-
ternal wavetable synthesizer. Bit 3 of Vendor-
Defined Card-Level register 2Bh when set high
will enable tracking with FM volume.

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PROGRAMMING THE ES1879

Table 21 Mixer Input Volume Registers If Sound Blaster Pro volume emulation is enabled, then a
mixer reset will cause both left and right channels to set to
Mixer Input
Playback Volume Record Volume their power-on default, namely 54 (or 36h).
Register Register
If Sound Blaster Pro volume emulation is enabled, then a
Audio 1 14h –
write to mixer register 22h (or 32h) will cause both the left
Audio 2 7Ch 69h and right master volume registers to be changed as
Microphone 1Ah 68h follows:
Music DAC (FM/ 36h 6Bh
689/69x) Table 23 SB Pro Write Volume Emulation
AuxA (CD) 38h 6Ah Value written to 22h or 32h Mute 6-bit Volume

AuxB 3Ah 6Ch 0 1 24

Line 3Eh 6Eh 1 0 24

I2 S 6Dh 6Fh 2 0 30
3 0 34
4 0 38
Sound Blaster Pro Master Volume Emulation
5 0 42
Using Sound Blaster Pro emulation for master volume
means that the 6-bit volume counters can be written via 6 0 46
the Sound Blaster Pro Mixer register 22h (or 32h). Sound 7 0 50
Blaster Pro emulation is enabled by default, and can be 8 0 54
disabled by setting bit 0 of Mixer register 64h.
9 0 55
The master volume registers 60h and 62h can always be 10 0 56
read, regardless of whether Sound Blaster Pro volume
11 0 58
emulation is enabled, using the Sound Blaster Pro mixer
register 22h (or 32h). The following 6-bit to 4-bit translation 12 0 59
table is used: 13 0 61
14 0 62
Table 22 SB Pro Read Volume Emulation 15 0 63
Value Read Value Read
Mute Master Volume
at 32h at 22h
1 xx 0 1
0 0-24 1 1
0 25-30 2 3
0 31-34 3 3
0 35-38 4 5
0 39-42 5 5
0 43-46 6 7
0 47-50 7 7
0 51-54 8 9
0 55 9 9
0 56-57 10 11
0 58 11 11
0 59-60 12 13
0 61 13 13
0 62 14 15
0 63 15 15

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PRELIMINARY ES1879 DATA SHEET
REGISTERS

REGISTERS
Types of Register Access
There are two types of audio registers in the ES1879:
‡ Mixer registers
These registers are accessed via I/O ports Audio_Base+4h and Audio_Base+5h. Audio_Base+4h is written with
the register address. Then the register can be read/written via Audio_Base+5h. These registers control many
functions other than the mixer.
‡ Controller registers
These registers are used to control Extended mode DMA playback and record through the first audio channel. Con-
troller registers are accessed via an extension to the Sound Blaster common interface. This interface uses I/O ports
Audio_Base+Ah, Audio_Base+Ch, and Audio_Base+Eh to transfer read data, write data/commands, and status,
respectively.

Mixer Registers
There are two types of mixer registers. Sound Blaster Pro-compatible mixer registers, as the name suggests are fully
compatible with the Sound Blaster Pro. ESS mixer registers are specific to ESS Technology, Inc.’s ES1879 AudioDrive®
chips, though many registers are shared throughout the AudioDrive® family of chips.
Sound Blaster Pro-Compatible Mixer Registers
This section provides a summary of Sound Blaster Pro-compatible mixer registers in the ES1879 and some comments
on the characteristics of these registers.

Table 24 Sound Blaster Pro-Compatible Register Summary


Reg D7 D6 D5 D4 D3 D2 D1 D0 Remark
00h Write: reset mixer Mixer reset
04h DAC play volume left x DAC play volume right x DAC playback volume
0Ah x x x x x Mic mix volume x Mic mix volume
0Ch x x F1 a
x F0 a
ADC Source x See note for F0, F1.
0Eh x x F2a x x x Stereo x See note for F2.
22h Master volume left x Master volume right x Master volume
26h FM volume left x FM volume right x Music DAC volume
28h CD (AuxA) volume left x CD (AuxA) volume right x CD (AuxA) volume
2Eh Line volume left x Line volume right x Line volume

a. Sound Blaster filter control bits F2, F1, and F0 have no function in the ES1879 and are ignored.

Filter Control Bits This bit enables stereo only for DMA transfer to the DAC
The Sound Blaster Pro mixer has three bits that control in Compatibility mode. It should not be used in Extended
input and output filters. They are labeled as F0, F1, and F2 mode.
in Table 24 and Table 25. They have no function in the
Clear this bit after completing the stereo DMA transfer,
ES1879 and their values are ignored.
because this bit is unaffected by software reset (only mixer
Mixer Stereo Control Bit reset).
Bit 1 of register 0Eh is the Mixer Stereo Control bit. It is See also “Stereo DMA Transfers in Compatibility Mode”
normally zero. Set this bit high to enable Sound Blaster on page 48.
Pro-compatible stereo DAC functions. Program the DAC
sample rate to be twice the sample rate of each channel.
For example, for 22 kHz stereo, program the “sample rate”
to be 44 kHz using command 40h.

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ES1879 DATA SHEET PRELIMINARY
REGISTERS

ESS Mixer Registers


This section provides a summary of the ESS mixer registers followed by a detailed description of each register.
Table 25 ESS Mixer Register Summary
Reg D7 D6 D5 D4 D3 D2 D1 D0 Remark
00h Write: reset mixer Reset mixer
14h Audio 1 playback volume left Audio 1 playback volume right Audio 1 playback volume
1Ah Mic mix volume left Mic mix volume right Mic mix volume
1Ch x x F1a x F0a Record source Record source select
1Eh x x F2 a
x x x Stereo x Stereo flag
32h Master volume left Master volume right Master volume
36h Music DAC volume left Music DAC volume right Music DAC volume
38h CD (AuxA) volume left CD (AuxA) volume right CD (AuxA) volume
3Ah AuxB volume left AuxB volume right AuxB volume
3Ch PC speaker volume PC speaker volume
3Eh Line volume left Line volume right Line volume
40h ES1879 identification value (read-only) ES1879 identification value
42h Input override Record source Record volume Serial mode input control
44h Output over-
Output signal Output volume Serial mode output control
ride
46h Analog con- Music mixer
Left ADC Right ADC Mono enable x FDXO enable FDXI enable
Serial mode miscellaneous analog
trol override test control
48h ES689/
Active low DSP test Telegaming
Serial enable Data format Serial reset ES69x inter- 0 Serial mode miscellaneous control
sync mode mode enable
face enable
4Ah 0 2’s complement filter divider Test register
4Ch Filter
0 2’s complement filter divider Serial mode filter divider control
override
4Eh Transmit source
Transmit Transmit
Receive target
Receive Receive Serial mode format/source/target con-
length mode length mode trol
50h Spatializer Reset Mono mode
Automatic
Spatializer enable and mode
0 effect limiter
enable release enable control
enable
52h 0 Spatializer level/limit Spatializer level/limit
54h 1 0 0 0 1 1 1 1 Spatializer auto-limit scale factor 1
56h 1 0 0 1 0 1 0 1 Spatializer auto-limit scale factor 2
58h Auto-limit increase rate Auto-limit decrease rate Spatializer auto-limit mode rate
5Ah Auto-limit low-level effect boost
Threshold
Auto-limit energy threshold
Spatializer auto-limit threshold and
enable offset
5Ch Left/Right
Signal
ADC test Accelerated Auto-limit test
processor THD flag DOWN flag UP flag Spatializer test control
state flag mode timing enable mode
test mode
5Dh ES978 mappable playback volume left ES978 mappable playback volume right ES978 mappable playback volume
5Eh Test data Spatializer test data
5Fh ES978 mappable record volume left ES978 mappable record volume right ES978 mappable playback volume
60h 0 Mute Left master volume Left master volume counter
61h 0 Mute Left volume counter Left hardware volume counter
62h 0 Mute Right master volume Right master volume counter
63h 0 Mute Right volume counter Right hardware volume counter
64h Split mode MPU-401 HWV IRQ HWV inter-
SB Pro mas-
Volume count HWV operation mode ter volume Master volume control
enable IRQ mask flag rupt mask
disable

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PRELIMINARY ES1879 DATA SHEET
REGISTERS

Table 25 ESS Mixer Register Summary (Continued)


Reg D7 D6 D5 D4 D3 D2 D1 D0 Remark
65h 0
Opamp
Opamp calibration control
calibration
66h Write: Reset hardware volume interrupt request Hardware volume interrupt request
67h ES978 record
ES978 mix mixer track-
ES978 mix volume 0 Interface mode select ES978 interface mode control
into playback ing mode
select
68h Mic mix volume left Mic mix volume right Mic record volume
69h Audio 2 volume left Audio 2 volume right Audio 2 record volume
6Ah CD (AuxA) volume left CD (AuxA) volume right CD (AuxA) record volume
6Bh Music DAC volume left Music DAC volume right Music DAC record volume
6Ch AuxB volume left AuxB volume right AuxB record volume
6Dh I2S volume left I2S volume right I2S volume
6Eh Line volume left Line volume right Line record volume
6Fh I2S volume left I2S volume right I2S record volume
70h Clock source Sample rate generator Audio 2 sample rate generator
71h Controller Audio 2 over- Audio 2 SCF Audio 1 SCF Asynchro-
FM mix
0 I2S enable register A1h sampling bypass bypass nous mode Audio 2 mode
enable
mode select enable enable enable enable
72h Filter clock divider Audio 2 filter clock divider
74h 2’s complement transfer count – low byte
Audio 2 transfer count reload
76h 2’s complement transfer count – high byte
78h DMA transfer type 0
Auto-Initial-
0
Enable trans- Enable trans-
Audio 2 control 1
ize enable fer into FIFO fer to DAC
7Ah IRQ latch IRQ mask 0
FIFO signed FIFO stereo FIFO 16-bit
Audio 2 control 2
mode mode mode
7Ch Audio 2 volume left Audio 2 volume right Audio 2 playback volume
7Dh 0
Mic preamp
FDXO source select
FDXI mix
Audio 2 configuration
enable enable
7Eh ADC test
Test bus enable
MIDI loop- FM test DSP loop- 2nd DMA test
0 Test register
enable back test enable back test enable

a. Sound Blaster filter control bits F2, F1, and F0 have Mic Mix Volume (1Ah, R/W)
no function in the ES1879 and are ignored.
Mic mix volume left Mic mix volume right
Register Detailed Descriptions 7 6 5 4 3 2 1 0

Reset Mixer (00h, R/W) This register controls the playback volume of the Mic input.
Write: Reset mixer
On reset, this register assumes the value of 00h.
7 6 5 4 3 2 1 0

A write to this register resets the mixer registers to their


default values.

Audio 1 Playback Volume (14h, R/W)


Audio 1 play volume left Audio 1 play volume right
7 6 5 4 3 2 1 0

This register controls the playback volume of the first


audio channel. On reset, this register assumes the value
of 88h.

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ES1879 DATA SHEET PRELIMINARY
REGISTERS

Record Source Select (1Ch, W) Stereo Flag (1Eh, R/W)


x x F1 x F0 Record Source Stereo
x x F2 x x x x
flag
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
On reset, this register assumes the value of 00h.
On reset, this register assumes the value of 00h.
Bits Definitions:
Bits Definitions:
Bits Name Description
Bits Name Description
7:6 – No function.
7:6 – No function.
5 F1 Sound Blaster Pro filter control bit. Has no
function in the ES1879 and is ignored. 5 F2 Sound Blaster Pro filter control bit. Has no
function in the ES1879 and is ignored.
4 – No function.
4:2 – No function.
3 F0 Sound Blaster Pro filter control bit. Has no
function in the ES1879 and is ignored. 1 Stereo 1 = Enable Sound Blaster Pro-compatible ste-
Flag reo DAC functions.
2:0 Record For extended access, use register address
0 = Disable Sound Blaster Pro-compatible ste-
Source 1Ch to select recording from the mixer as fol-
reo DAC functions.
lows:
bit 2 bit 1 bit 0 record source selected 0 – No function.
0 0 0 Microphone (default).
0 0 1 Left channel: mic (not mixed Master Volume (32h, R/W)
with ES978 mic).
Master volume left Master volume right
Right channel: master
volume inputsa (left + right). 7 6 5 4 3 2 1 0
0 1 0 CD (AuxA) input.
0 1 1 Left channel: AOUTL On reset, this register assumes the value of 88h.
Right channel: AOUTR.
This register provides backward-compatible access to
1 0 0 Microphone.
1 0 1 Record mixer. master volume. New applications can also use registers
1 1 0 Line input. 60h and 62h, which have more resolution.
1 1 1 Master volume inputs. a
Music DAC Volume (36h, R/W)
a.The master volume inputs are the outputs of the Music DAC volume left Music DAC volume right
Spatializer processor, before master volume is
7 6 5 4 3 2 1 0
applied.
This register controls the playback volume of the music
DAC. On reset, this register assumes the value of 88h.

CD (AuxA) Volume (38h, R/W)


CD (AuxA) volume left CD (AuxA) volume right
7 6 5 4 3 2 1 0

This register controls the playback volume of the CD audio


input. On reset, this register assumes the value of 00h.

AuxB Volume (3Ah, R/W)


AuxB volume left AuxB volume right
7 6 5 4 3 2 1 0

This register controls the playback volume of the auxiliary


line input. On reset, this register assumes the value of 00h.

ESS Technology, Inc. SAM0025A-062397 65


PRELIMINARY ES1879 DATA SHEET
REGISTERS

PC Speaker Volume (3Ch, R/W) Serial Interface Registers


PC speaker volume This section describes registers related to the DSP and
7 6 5 4 3 2 1 0 ES689/ES69x serial interface.

This register controls the PC speaker volume. Bits 2:0 Serial Mode Input Control (42h, R/W)
select the attenuation level in steps of -3 dB. The Input
Record source Record volume
maximum setting of 08h corresponds to 0 dB attenuation. override
On reset, this register assumes the value of 04h. 7 6 5 4 3 2 1 0

Line Volume (3Eh, R/W) This register can be used to gain independent control of
Line volume left Line volume right the record source and record volume, while in serial mode.
7 6 5 4 3 2 1 0
When in serial mode, mixer registers 0Ch/1Ch and
controller register B4h can still be used to control record
This registers controls the playback volume of the line source and record volume if desired. Mixer register 42h
input. On reset, this register assumes the value of 00h. enables the ES1879 to have two different values set for
record source and record volume dependent on whether
ES1879 Identification Value (40h, R) the ES1879 is in serial mode or not. This register only
takes control of record source and volume while the
ES1879 identification value
ES1879 is in serial mode and bit 7 is high.
7 6 5 4 3 2 1 0
Bits Definitions:
To identify the ES1879, mixer register 40h returns the Bits Name Description
following values on four successive reads: 7 Input 1 = Input source and input volume replace nor-
18h, 79h, A[11:8], A[7:0] override mal values as programmed by the application
when the ES1879 is in serial mode.
where 18h and 79h are data reads indicating the part 0 = Input source and input volume are
number (1879) and A[11:0] is the base address of the unchanged during serial mode.
configuration device. 6:4 Record Record source selects the record source dur-
source ing serial mode if bit 7 is high. The values
below override the normal mixer settings (reg-
ister 0Ch or 1Ch):
bit 6 bit 5 bit 4 record source selected
0 0 0 Microphone (default).
0 0 1 CD (AuxA) input.
0 1 0 Microphone.
1 0 0 Left channel: mic (not mixed
with ES978 mic).
Right channel: master vol-
ume inputs (left + right).
1 0 1 Left channel: AOUTL
Right channel: AOUTR.
1 1 0 Record mixer.
1 1 1 Record source discon-
nected from filters
(muted). Record source
is unchanged in serial
mode.
3:0 Record If bit 7 is high during serial mode, this value
volume overrides the record volume settings set via
controller register B4h. For microphone
source, the record gain is from 0 to +22 dB in
steps of 1.5 dB. For other sources, the record
gain is from -6 to +16.5 dB in steps of 1.5 dB.

66 SAM0025A-062397 ESS Technology, Inc.


ES1879 DATA SHEET PRELIMINARY
REGISTERS

Serial Mode Output Control (44h, R/W) Serial Mode Miscellaneous Analog Control (46h, R/W)
Output Analog Music
Output signal Output volume Left Right Mono FDXO FDXI
override control mixer x
ADC ADC enable enable enable
override test
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Bits Definitions:
Bits Definitions:
Bits Name Description
Bits Name Description
7 Output 1 = Output volume during serial mode is from
override this register rather than from the Mixer Master 7 Analog 1 = Bits 6:0 take effect during serial mode.
Volume register. Output signal control is control 0 = Bits 6:0 do not take effect during serial
always in force during serial mode regardless override mode.
of the state of this bit. 6 Music Test feature.
0 = Output volume is unchanged during serial mixer test 1 = Music DAC mixer inputs replaced with
mode. AUXBL/AUXBR inputs.
6:4 Output Controls the signal routed to speaker outputs 0 = Music DAC mixer inputs normal.
signal AOUT_L and AOUT_R: 5 Left ADC 1 = Left channel combined ADC and DAC is in
bit 6 bit 5 bit 4 signal ADC mode.
0 0 0 Mute. 0 = Left channel combined ADC and DAC is in
0 0 1 No change from normal DAC mode.
operation. 4 Right 1 = Right channel combined ADC and DAC is
0 1 0 Audio 1 only – playback ADC in ADC mode.
mixer bypassed (over- 0 = Right channel combined ADC and DAC is
rides record monitor and in DAC mode.
record mute features).
0 1 1 No change from normal 3 Mono This bit should be set appropriately for the
operation. enable application as follows:
1 0 0 Playback mixer with audio 1 = Mono record, mono playback, or mono full-
1 DAC set to 0 dB attenu- duplex.
ation (overrides record 0 = Stereo record or stereo playback.
monitor and record mute 2 – Don’t care.
features). 1 FDXO 1 = Enables AUXBR as an output. The output
1 0 1 Playback mixer output with enable source is determined by mixer register 7Dh
audio 1 DAC playback bits [2:1]. AUXBL replaces AUXBR as an input
muted (overrides record to the record and playback mixers.
monitor and record mute 0 = AUXBR is an input to the record and play-
features). back mixers.
1 1 0 Reserved.
0 FDXI 1 = Enables FDXI input connection from left
1 1 1 Reserved.
enable channel filter input and thus to the input of the
3:0 Output Replaces normal master volume setting if bit 7 left channel ADC.
volume is high during serial mode. 0 is mute. 15 is max- 0 = FDXI input has 50K pull-up to CMR. The
imum (0 dB). left channel filter input and ADC comes from
the input volume stage as usual.

ESS Technology, Inc. SAM0025A-062397 67


PRELIMINARY ES1879 DATA SHEET
REGISTERS

Serial Mode Miscellaneous Control (48h, R/W) FS Rate Control (4Ah, R/W)
ES689/ 0 2’s complement filter divider
DSP
Serial Data Serial ES69x Active Telegaming
7 6 5 4 3 2 1 0
test 0
enable format reset interface low sync mode enable
mode
enable
7 6 5 4 3 2 1 0 This register is used in a test mode enabled by bit 2 of
mixer register 48h.
Bits Definitions: Bits Definitions:
Bits Name Description Bits Name Description
7 Serial 1 = Enable DSP serial port. This signal is syn- 7 – Reserved. Always write 0.
enable chronized with DCLK input rising edge. If
6:0 2’s com- These bits are a 2's complement (signed)
DCLK is not running, enabling Serial enable
plement value that divides DCLK. DCLK is a clock out-
has no effect.
filter put of 1.5876 MHz. FS is an active-high frame
0 = Disable DSP serial port.
divider sync output at a rate determined by bits 6:0 of
6 Data 1 = Data format is 2's complement (signed). this register.
format 0 = Data format is unsigned (offset binary). For example, if this register is programmed
5 Serial 1 = Reset Serial register left/right toggle flags. with the value 5Ch (-36 decimal), then the
reset 0 = Release reset. frame rate is 44.1 KHz.
4 ES689/ 1 = Enable ES689/ES69x serial interface to
ES69x use the music DAC. MCLK must also go high
interface at least once every 20 µsecs or the DAC will
enable revert to FM. The mixer volume for the music
DAC is controller by mixer register 36h.
0 = Disable ES689/ES69x serial interface.
3 Active 1 = Active-low frame sync pulse.
low sync 0 = Active-high frame sync pulse.
2 DSP test 1 = Test mode: FS and DCLK become outputs.
mode DCLK is 1.5876 MHz. FS is an active-high
frame sync at a rate determined by mixer reg-
ister 4Ah.
0 = Disable DSP test mode.
1 – Reserved. Always write 0.
0 Telegam- 1 = Enables telegaming mode. In serial mode,
ing mode connect first channel DMA (otherwise known
enable as game-compatible DMA) to the system DAC.
This allows game-compatible audio to be
heard when in serial mode. The system DAC
gets its filter clock and volume control from the
first channel.
0 = In serial mode, the first channel DMA is not
played. The second channel is connected to
the system DAC.

68 SAM0025A-062397 ESS Technology, Inc.


ES1879 DATA SHEET PRELIMINARY
REGISTERS

Serial Mode Filter Divider Control (4Ch, R/W) Serial Mode Format/Source/Target Control (4Eh, R/W)
Filter Transmit Transmit Transmit Receive Receive
0 2’s complement filter divider Receive target
override source length mode length mode
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

This register controls the filter clock rate during serial The ES1879 serial port can interface with an external DSP
mode. in several formats and various applications. The format
choices include 8- or 16-bit and mono or stereo. Note that
Bits Definitions:
signed vs. unsigned is controlled by bit 6 of mixer register
Bits Name Description 48h. The receive and transmit channels can have different
7 Filter 1 = During serial mode, the filter clock is gener- formats, though this is not common.
override ated by dividing down the serial clock.
0 = During serial mode, the filter clock is gener- For receive, there are two choices for the target of the
ated as follows: data:
Generally, the filter roll-off should be positioned
at 80% - 90% of the Sample_Rate/2 frequency.
‡ First channel DMA FIFO
The ratio of the roll-off frequency to the filter ‡ First channel DAC
clock frequency is 1:82. In other words, first
For the transmit, there are two choices for the source of
determine the desired roll-off frequency by tak-
the data:
ing 80% of the Sample_Rate divided by 2, then
multiply by 82 to find the desired Filter Clock ‡ First channel DMA FIFO
frequency. Use the formula below to determine
the closest divider: ‡ First channel ADC
Filter_Clock_Frequency = 7.16 MHz / (256- Bits Definitions:
Filter_Divider_Register)
Bits Name Description
6:4 – Reserved. Always write 0.
7:6 Transmit Transmit register source:
3:0 2’s com- These bits are a 2's complement (signed) source bit 7 bit 6 source
plement value that divides the serial clock. The ratio of 0 0 None: Transmit register held at
filter the filter -3 dB frequency to the filter clock is zero.
divider about 1:41. 0 1 Audio 1 FIFO (audio 1 in mono
Examples: or stereo playback direction).
02h (-14) External Serial Clock 2.048 MHz / 1 0 Audio 1 ADC (left channel ADC
14 / 41 = 3568 Hz for 8000 Hz if mono).
sample rate. 1 1 Reserved.
0Eh (-2) Internal Serial Clock 1.591 MHz / 2 5 Transmit 1 = Transmit length is 16 bits, unsigned.
/ 41 = 19.4 kHz for 44,100 Hz length 0 = Transmit length is 8 bits, unsigned.
sample rate. Note that the sample
4 Transmit 1 = Transmit mode is stereo. Left and right
rate divider is an integer multiple of
mode channels alternate, with left channel data pre-
the filter divider for 44,100, which
ceding right channel data.
gives maximum performance of
0 = Transmit mode is mono.
DACs and ADCs.
3:2 Receive Receive register target:
target bit 3 bit 2 target
0 0 None: Receive register held at
zero.
0 1 Audio 1 FIFO (audio 1 in mono
or stereo record direction).
1 0 Audio 1 DAC (right channel DAC
if mono).
1 1 Reserved.
1 Receive 1 = Receive length is 16 bits, unsigned.
length 0 = Receive length is 8 bits, unsigned.
0 Receive 1 = Receive mode is stereo. Left and right
mode channels alternate, with left channel data pre-
ceding right channel data.
0 = Receive mode is mono.

ESS Technology, Inc. SAM0025A-062397 69


PRELIMINARY ES1879 DATA SHEET
REGISTERS

Spatializer Audio Processor Registers Spatializer Auto-Limit Scale Factor 2 (56h, R/W)
This section describes registers related to the Spatializer 1 0 0 1 0 1 0 1
3-D audio processor. 7 6 5 4 3 2 1 0

Spatializer Enable and Mode Control (50h, R/W) This register, along with mixer register 54h, is used to set
0 0 0 0 Spatializer enable Reset Mono mode Auto-limit scale factors used by the automatic limit mechanism.
7 6 5 4 3 2 1 0
Program this register to 95h (149 decimal) as shown.
Recommended values are subject to change in the future.
Reset to zero by hardware reset. Reset to zero by hardware reset.
Bit Definitions:
Spatializer Auto-Limit Mode Rate (58h, R/W)
Bits Name Description
Auto-limit increase rate Auto-limit decrease rate
7:4 0 Reserved. Always write 0.
7 6 5 4 3 2 1 0
3 Spatial- 1 = Enable Spatializer effect.
izer 0 = Disable Spatializer effect (effect unit
The recommended value for this register is 94h:
enable bypassed).
2 Reset 1 = Release from reset. Max_Decrease_Rate = 276 Hz
Max_Increase_Rate = 2480 Hz
0 = Reset Spatializer.
1 Mono 1 = Mono-in, stereo-out mode. Reset to zero by hardware reset.
mode 0 = Stereo-in, stereo-out mode. Bit Definitions:
0 Auto-limit 1 = Enable automatic effect limiter.
Bits Name Description
0 = Disable automatic effect limiter.
7:4 Auto- Specifies the rate at which gain can be
limit increased, relative to the decrease rate:
Spatializer Level/Limit (52h, R/W)
increase Max_Increase_Rate =
0 0 Spatializer level/limit rate Max_Decrease_Rate/(N+1); N is bits 7:4 of this
7 6 5 4 3 2 1 0 register.
3:0 Auto- Specifies the rate at which gain can be
Reset to zero by hardware reset. limit decreased:
decrease Max_Decrease_Rate = 1378 Hz / (N+1)
Bit Definitions:
rate N is bits 3:0 of this register.
Bits Name Description
7:6 0 Reserved. Always write 0. Spatializer Auto-Limit Threshold and Offset(5Ah,R/W)
5:0 Spatializer 0 is minimum effect; 3Fh is maximum effect. If Threshold
Auto-limit low-level effect boost Auto-limit energy threshold
level/ the auto-limit function is enabled (mixer regis- enable
limit ter 50h bit 0), then this register specifies the 7 6 5 4 3 2 1 0
maximum effect level (actual effect determined
by automatic level setting mechanism). If the Reset to zero by hardware reset.
auto-limit function is disabled, then this register
sets the current effect level. Bit Definitions:
Bits Name Description
Spatializer Auto-Limit Scale Factor 1 (54h, R/W) 7:4 Auto-limit Increases Spatialization effect for low-level
1 0 0 0 1 1 1 1 low-level signals.
7 6 5 4 3 2 1 0 effect boost
3 Threshold 1 = Enable auto-limit energy threshold
This register, along with mixer register 56h, is used to set enable requirement.
scale factors used by the automatic limit mechanism. 0 = Disable auto-limit energy threshold
Program this register to 8Fh (143 decimal) as shown. requirement.
Recommended values are subject to change in the future. 2:0 Auto-limit 1 = Enable minimum energy level setting of
energy input signal to make auto-limit decisions.
Reset to zero by hardware reset. threshold 0 = Disable minimum energy level setting of
input signal.

70 SAM0025A-062397 ESS Technology, Inc.


ES1879 DATA SHEET PRELIMINARY
REGISTERS

Spatializer Test Control (5Ch, R/W) ES978 Mappable Volume Registers 5Dh and 5Fh
Signal Accelerated This section describes registers related to the ES978
Left/Right ADC test Auto-Limit THD Down Up
processor timing
state flag
test mode
mode
enable
test mode flag flag flag mappable volume registers. These registers are accessed
via I/O addresses Audio_Base+4h and Audio_Base+5h.
7 6 5 4 3 2 1 0

In ADC or signal processor test mode, four reads or writes are ES978 Mappable Playback Volume (5Dh, R/W)
needed to access all four bytes. The sequence is controlled ES978 mappable playback volume left ES978 mappable playback volume right
by an internal 2-bit counter. This counter is incremented after 7 6 5 4 3 2 1 0
every I/O read or write to mixer register 5Eh. The counter is
reset by an I/O read from mixer register 5Ch. The mappable volume registers can be assigned to any
single ES978 mixer source. Usually the mixer registers in
Reset to zero by hardware reset. the ES978 are slaved to the corresponding register in the
Bit Definitions: ES1879. Assigning a ES978 mixer register to this register
Bits Name Description enables the ES978 mixer source volume to be controlled
independently of the corresponding ES1879 mixer
7 Left/ Read-only. Left/right state flag. This flag indi-
register. Bits 2:0 of PnP register 2Bh assigns the
Right cates which channel the test data is being sam-
state flag pled from. mappable volume register to a mixer input of the ES978.
6 Signal 1 = Enable signal processor test mode. This
Spatializer Test Data (5Eh, R/W)
proces- mode enables the input to the signal processing
sor test logic to be written from the host for test pur- D D D D D D D D
mode poses. Poll bit 7 of this register to synchronize. 7 6 5 4 3 2 1 0
When it goes high, write to register 5Eh four
times successively to write left low, left high, Except in ADC test mode, this register returns the current
right low, right high. 8-bit gain setting. In ADC test mode, it is used to read back
5 ADC test Poll bit 7 of this register to synchronize, then the ADC values. In signal processor test mode, it is used
mode read register 5Eh four times successively to to write test pattern data.
read left low, left high, right low, right high.
In ADC test mode or signal processor test mode, four reads
4 Acceler- 1 = Accelerated timing.
ated or writes are needed to access all four bytes in series. The
timing sequence is controlled by an internal 2-bit counter. This
enable counter is incremented after every I/O read or write to
3 Auto-limit 1 = Auto-limit test mode. mixer register 5Eh. The counter is reset by an I/O read from
test mixer register 5Ch.
mode
2 THD flag THD flag in auto-limit test mode. ES978 Mappable Record Volume (5Fh, R/W)
1 Down Down flag in auto-limit test mode. ES978 mappable record volume left ES978 mappable record volume right
flag 7 6 5 4 3 2 1 0

0 Up flag Up flag in auto-limit test mode.


The mappable volume registers can be assigned to any
single ES978 mixer source. Usually the mixer registers in
the ES978 are slaved to the corresponding register in the
ES1879. Assigning an ES978 mixer register to this
register enables the ES978 mixer source volume to be
controlled independently of the corresponding ES1879
mixer register. Bits 2:0 of PnP register 2Bh assigns the
mappable volume register to a mixer input of the ES978.

ESS Technology, Inc. SAM0025A-062397 71


PRELIMINARY ES1879 DATA SHEET
REGISTERS

Extended Mode Master Volume Control Registers Right Master Volume and Mute (62h, R/W)
This section describes registers related to the master 0 Mute Right master volume
volume control in Extended mode. These registers are 7 6 5 4 3 2 1 0
accessed via I/O addresses Audio_Base+4h and
Audio_Base+5h. This register determines the master volume level for the
right channel.
Left Master Volume and Mute (60h, R/W)
When in Sound Blaster Pro Compatibility mode, writes to
0 Mute Left master volume registers 22h or 32h are translated into writes to 60h and
7 6 5 4 3 2 1 0 62h. See “Sound Blaster Pro Master Volume Emulation”
on page 61. Writes to this register when in Compatibility
This register determines the master volume level for the mode run the risk of being overwritten.
left channel.
On hardware reset, this register is set to 36h.
When in Sound Blaster Pro Compatibility mode, writes to
Bits Definitions:
registers 22h or 32h are translated into writes to 60h and
62h. See “Sound Blaster Pro Master Volume Emulation” Bits Name Description
on page 61. Writes to this register when in Compatibility 7 – Reserved. Always write 0.
mode run the risk of being overwritten. 6 Mute 1 = Enable right channel mute.
0 = Disable right channel mute.
On hardware reset, this register is set to 36h.
5:0 Right Bits 5:0 select the attenuation level in steps of
Bits Definitions: master -1.5 dB. The maximum setting of 3Fh corre-
Bits Name Description volume sponds to 0 dB attenuation.
7 – Reserved. Always write 0.
6 Mute 1 = Enable left channel mute. Right Hardware Volume Counter (63h, R/W)
0 = Disable left channel mute. 0 Mute Right volume counter
5:0 Left Bits 5:0 select the attenuation level in steps of 7 6 5 4 3 2 1 0
master -1.5 dB. The maximum setting of 3Fh corre-
volume sponds to 0 dB attenuation. Normally, the hardware volume controls change the
master volume registers 60h and 62h directly, producing
Left Hardware Volume Counter (61h, R/W) an interrupt at each change. In Split mode, the hardware
0 Mute Left volume counter volume counters are split from the master volume
7 6 5 4 3 2 1 0
counters. Pressing a hardware volume control button
changes the hardware volume counters and produces an
Normally, the hardware volume controls change the interrupt. The host software can read the counters and
master volume registers 60h and 62h directly, producing update the master volume registers as needed. Split mode
an interrupt at each change. In Split mode, the hardware is enabled by bit 7 of mixer register 64h. If bit 7 is low, this
volume counters are split from the master volume register is combined with register 62h and cannot be
counters. Pressing a hardware volume control button independently read or written.
changes the hardware volume counters and produces an Bits Definitions:
interrupt. The host software can read the counters and Bits Name Description
update the master volume registers as needed. Split mode
7 – Reserved. Always write 0.
is enabled by bit 7 of mixer register 64h. If bit 7 is low, this
register is combined with register 60h and cannot be 6 Mute 1 = Enable right channel mute.
0 = Disable right channel mute.
independently read or written.
5:0 Right Bits 5:0 select the attenuation level in steps of
Bits Definitions: volume -1.5 dB. The maximum setting of 3Fh corre-
Bits Name Description counter sponds to 0 dB attenuation.
7 – Reserved. Always write 0.
6 Mute 1 = Enable left channel mute.
0 = Disable left channel mute.
5:0 Left Bits 5:0 select the attenuation level in steps of
volume -1.5 dB. The maximum setting of 3Fh corre-
counter sponds to 0 dB attenuation.

72 SAM0025A-062397 ESS Technology, Inc.


ES1879 DATA SHEET PRELIMINARY
REGISTERS

Master Volume Control (64h, R/W) Bits Name Description


SB Pro 0 SB Pro When low, a write to legacy master volume
Split HWV
MPU-401 Volume HWV HWV opera- master master registers 22h or 32h is translated into a write
mode interrupt
IRQ mask count IRQ flag tion mode volume
enable mask
disable
volume to the hardware master volume counters,
disable Mixer registers 60h and 62h. If high, the SB
7 6 5 4 3 2 1 0
Pro Master Volume registers are, in effect,
read-only. This bit is cleared by hardware
Bits Definitions: reset.
Bits Name Description
7 Split 1 = Enable Split mode for hardware volume Opamp Calibration Control (65h, R/W)
mode control. This mode splits hardware volume 0 Opamp calibration
enable counters (61h and 63h) from the master vol-
7 6 5 4 3 2 1 0
ume control registers (60h and 62h). The host
software is responsible for reading the
counter register and updating the master vol- In the analog circuitry of the ES1879, operational
ume registers. amplifiers that require calibration go through a calibration
0 = Disable Split mode. Hardware volume and procedure that takes about 200 msec to perform. During
master volume registers are slaved together. this period, the analog outputs of the chip (AOUT_L,
Registers 61h and 63h cannot be indepen- AOUT_R, and FDXO) are muted.
dently accessed.
The calibration procedure occurs automatically after
6 MPU-401 This bit is AND’d with the MPU-401 interrupt
hardware reset and can be started at any time thereafter
IRQ mask request. If this bit is low, the MPU-401 inter-
by writing 01h to mixer register 65h.
rupt request stays low. This bit is cleared by
hardware reset. Bits Definitions:
5 Volume 1 = Count up and down by 3 for each push of Bits Name Description
count UP or DOWN button.
7:1 – Reserved. Always write 0.
0 = Count up and down by 1 for each push of
UP or DOWN button. 0 Opamp Read:
This bit is cleared by hardware reset. calibra- 1 = Opamp calibration in progress. Opamp cal-
tion ibration occurs if a one is written to this bit after
4 HWV IRQ Read-only interrupt request from hardware
a hardware reset. Calibration can take up to
flag volume event.
200 msec, during which the analog outputs
3:2 HWV Selects hardware volume operation (AOUTL/AOUTR and FDXO) of the ES1879
operation mode: are muted.
mode bit 3 bit 2 mode Write:
0 0 Normal 3-wire mode (hard- 1 = Start opamp calibration.
ware reset default). 0 = Stop opamp calibration immediately. This
0 1 2-wire mode: UP and DOWN is not recommended.
inputs low together act as a
MUTE input low. Hardware Volume Interrupt Request Reset (66h, W)
1 0 2-wire enabled, debounce
reduced (40 msec to 10 Write: Reset hardware volume interrupt request
µsecs), auto-increment/-decre- 7 6 5 4 3 2 1 0
ment disabled.
1 1 Hardware volume control dis- Any write to this register resets the hardware volume
abled. interrupt request. This register is write-only.
1 HWV inter- This bit is AND’d with the hardware volume
rupt mask interrupt request before being OR’d with the
audio 1 interrupt request. If this bit is low, the
hardware volume interrupt request does not
get OR’d with the audio 1 interrupt request.
This bit is cleared by hardware reset. When
high, enables the hardware volume control to
be shared with the audio interrupt.

ESS Technology, Inc. SAM0025A-062397 73


PRELIMINARY ES1879 DATA SHEET
REGISTERS

ES978 Interface Mode Control (67h, R/W) Mic Record Volume (68h, R/W)
ES978 audio ES978 record Mic record volume left Mic record volume right
ES978 mix Interface mode
0 mix into play- mixer tracking
volume select 7 6 5 4 3 2 1 0
back enable mode select
7 6 5 4 3 2 1 0
This registers controls the record volume for the Mic input.
Set low by hardware reset but not by mixer reset.
In the ES1878, the mode of the interface to the ES978
(playback vs record, mono vs full-duplex) was determined
by the state of the CODEC inside the ES1878 Audio 2 Record Volume (69h, R/W)
automatically. In the ES1879, the mode of the interface is Audio 2 record volume left Audio 2 record volume right
determined by mixer register 67h. 7 6 5 4 3 2 1 0

Bit 2, the ES978 record mixer tracking mode select bit,


This register controls the record volume for the second
determines which mixer (playback or record) in the
audio channel. Set low by hardware reset but not by mixer
ES1879 is tracked (mirrored) by the ES978 record mixer.
reset.
It is useful to have the ES978 record mixer track the
ES1879 playback mixer in two situaions. First, if there are
CD (AuxA) Record Volume (6Ah, R/W)
no speakers in the docking station (ES978), the ES978
record mixer is used to collect audio sources from the CD record volume left CD record volume right
docking station and sent to the ES1879 playback mixer. 7 6 5 4 3 2 1 0
Second, Spatializer 3-D effects can be added to docking
station audio sources by means of this mode. If bit 2 is set This register controls the record volume for the CD input.
high, bits 2:0 of mixer register 1Ch must be set to 101. Set low by hardware reset but not by mixer reset.

This register is set to E3h by hardware reset.


Music DAC Record Volume (6Bh, R/W)
Bits Definitions: Music DAC record volume left Music DAC record volume right
Bits Name Description 7 6 5 4 3 2 1 0
7:5 ES978 Select mix volume of audio received from
mix vol- ES978 into playback mixer of the ES1879 This register controls the record volume for the music DAC
ume when bit 3 of this register is set high. (FM or wavetable). Set low by hardware reset but not by
4 – Reserved. Always write 0. mixer reset.
3 ES978 1 = Enable audio received from ES978 to mix
audio into playback mixer of ES1879. AuxB Record Volume (6Ch, R/W)
mix into 0 = No audio is mixed into the playback mixer AuxB record volume left AuxB record volume right
playback of the ES1879 from the ES978.
7 6 5 4 3 2 1 0
enable
2 ES978 1 = Record mixer in ES978 tracks playback This register controls the record volume for the auxiliary
record mixer in ES1879. ES978 playback mixer is
line input. Set low by hardware reset but not by mixer
mixer muted except for ES1879 audio.
reset.
tracking 0 = Record mixer in ES978 tracks record mixer
mode in ES1879 (default).
select. I2S Volume (6Dh, R/W)
1:0 Interface Selects the ES978–ES1879 interface mode. 2
I S volume left 2
I S volume right
mode bit 1 bit 0 mode 7 6 5 4 3 2 1 0
select 0 0 Differential stereo playback to
ES978. This register controls the playback volume for the I2S input.
0 1 Differential stereo record from Set low by hardware reset but not by mixer reset.
ES978.
1 0 Mono full-duplex.
1 1 Stereo full-duplex (default). Line Record Volume (6Eh, R/W)
Line record volume left Line record volume right
7 6 5 4 3 2 1 0

This register controls the record volume for the line input.
Set low by hardware reset but not by mixer reset.

74 SAM0025A-062397 ESS Technology, Inc.


ES1879 DATA SHEET PRELIMINARY
REGISTERS

I2S Record Volume (6Fh, R/W) Audio 1 and Audio 2 Mode (71h, R/W)
I S record volume left
2
I S record volume right
2
Audio 2 Audio 2 Audio 1 Asynchro-
Controller FM
I2S oversam- SCF SCF nous
7 6 5 4 3 2 1 0 0 register A1h mix
enable pling bypass bypass mode
mode select enable
enable enable enable enable
This register controls the record volume for the I2S input. 7 6 5 4 3 2 1 0
Set low by hardware reset but not by mixer reset.
This register controls a variety of modes for the first and
Audio 2 Mixer Registers
second audio channels.
This section describes registers related to the second
audio channel. These registers are accessed via I/O This register is reset to zero by hardware reset.
addresses Audio_Base+4h and Audio_Base+5h. Bits Definitions:
Bits Name Description
Audio 2 Sample Rate Generator (70h, R/W)
7 – Reserved. Always write 0.
Clock
source
Sample rate divider 6 I2 S 1 = Enable I2S source input.
enable 0 = Disable I2S source input.
7 6 5 4 3 2 1 0
5 Control- 1 = Enable controller register A1h to behave
ler regis- just as mixer register 70h. This gives more
This register should be programmed for the sample rate
ter A1h accurate sample rates that are divisors of 48
for all DAC operations in extended mode.
mode kHz..
The sample rate is determined by the two’s complement select 0 = Controller register A1h behaves as
divider in bits 6:0. described under that register’s description.
4 Audio 2 1 = enable 4x oversampling mode for the
Sample_Rate = Clock_Source / (256 - Sample_Rate_Divider)
oversam- Audio 2 DAC. This mode bypasses the switch
This register is reset to zero by hardware reset. pling capacitor filter.
enable 0 = Disable oversampling for the Audio 2 DAC.
Bits Definitions:
3 Audio 2 1 = Enable bypass of the switch capacitor filter
Bits Name Description SCF for the Audio 2 DAC. This filter is bypassed
7 Clock 1 = 768 kHz (used to generate 48 kHz, 32 kHz, bypass automatically when bit 4 of this register is set
source 16 kHz, 8 kHz, etc.). enable high.
0 = 793.8 kHz (used to generate 44.1 kHz, 0 = Disable bypass of the switch capacitor filter
22.05 kHz, etc.). for the Audio 2 DAC.
6:0 Sample Signed sample rate divider of master clock. 2 Audio 1 1 = Enable bypass of the switch capacitor filter
rate For example: SCF for the Audio 1 CODEC.
divider value sample rate bypass 0 = Disable bypass of the switch capacitor filter
A0h 8000 enable for the Audio 1 CODEC.
F0h 48000 1 Asyn- 1 = The sample rate for Audio 2 may be asyn-
6Eh 44100 chronous chronous to Audio 1.
mode 0 = the Audio 2 sample rate is slaved to the
enable sample rate for Audio 1.
0 FM mix 1 = Audio 2 is slaved to the FM synthesizer
enable sample rate and digitally mixed with the FM
synthesizer output.
0 = Audio 2 is not slaved to the FM synthe-
sizer.

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PRELIMINARY ES1879 DATA SHEET
REGISTERS

Audio 2 Filter Clock Divider (72h, R/W) Audio 2 Control 1 (78h, R/W)
Filter clock divider Enable
DMA Enable
Auto-Initialize transfer
7 6 5 4 3 2 1 0 transfer 0 0 0 transfer
enable into
type to DAC
FIFO
This register controls the low-pass frequency of the 7 6 5 4 3 2 1 0
switch-capacitor filters inside the ES1879. Generally, the
filter roll-off should be positioned at 80% - 90% of the This register is reset to zero by hardware or software reset
Sample_Rate/2 frequency. The ratio of the roll-off via bit 0 of port Audio_Base+6h.
frequency to the filter clock frequency is 1:82. In other
words, first determine the desired roll-off frequency by Bits Definitions:
taking 80% of the Sample_Rate divided by 2, then multiply Bits Name Description
by 82 to find the desired Filter Clock frequency. Use the 7:6 DMA Selects single or demand transfer for the
formula below to determine the closest divider: transfer second audio channel:
type bit 7 bit 6 transfer type bytes/DMA request
Filter_Clock_Frequency = 7.16 MHz / (256-Filter_Divider_Register)
0 0 single 1
0 1 demand 2
Audio 2 Transfer Count Reload (74h, R/W)
1 0 demand 4
2’s complement transfer count – low byte 1 1 demand 8
7 6 5 4 3 2 1 0 5 – Reserved. Always write 0.
4 Auto-Ini- 1 = Auto-Initialize mode. After the transfer
NOTE: When suspend/resume bit is set, reading this tialize counter rolls over to 0, it is automatically
register returns the current counter contents. enable reloaded and DMA continues. The second
channel interrupt flag is set high.
Audio 2 Transfer Count Reload (76h, R/W) 0 = Normal mode. After the transfer counter
2’s complement transfer count – high byte rolls over to 0, it is reloaded but DMA stops. Bit
7 6 5 4 3 2 1 0
1 of this register is cleared. The second chan-
nel interrupt flag is set high.
NOTE: When suspend/resume bit is set, reading this 3:2 – Reserved. Always write 0.
register returns the current counter contents. 1 Enable 1 = Enable DMA transfer into Audio 2 FIFO (32
transfer words deep).
into FIFO 0 = Disable DMA transfer into FIFO. This
causes the DMA counter to be reloaded from
the reload register.
This bit is cleared automatically at the comple-
tion of a non auto-initialize transfer.
0 Enable 1 = Enable transfer from FIFO to Audio 2 DAC
transfer (or in special cases from the FIFO to either the
to DAC DSP serial port or to be mixed with the FM syn-
thesizer output).
0 = Disable transfer from FIFO to DAC. DAC
receives code 0 and FIFO is flushed.

76 SAM0025A-062397 ESS Technology, Inc.


ES1879 DATA SHEET PRELIMINARY
REGISTERS

Audio 2 Control 2 (7Ah, R/W) Audio 2 Configuration (7Dh, R/W)


FIFO FIFO FIFO Mic
IRQ FDXI mix
IRQ mask 0 signed stereo 16-bit 0 preamp FDXO source select
latch enable
mode mode mode enable
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

This register is reset to zero by hardware or software reset. This register is reset to 08h by hardware reset.
Bits Definitions: Bits Definitions:
Bits Name Description Bits Name Description
7 IRQ latch Audio 2 Interrupt Request Latch. This latch is 7:4 – Reserved. Always write 0.
set high when the DMA counter rolls over to 0 3 Mic 1 = Enable +26 dB microphone preamp gain.
or when a 1 is written to this bit. The latch is preamp 0 = Microphone preamp is 0 dB.
cleared by writing a 0 to this bit or by hardware enable
or software reset.
2:1 FDXO Selects the FDXO source:
6 IRQ This bit is AND’d with bit 7 to produce the source bit 2 bit 1 source
mask audio 2 interrupt request. select 0 0 Mute (CMR).
5:3 – Reserved. Always write 0. 0 1 CINR pin (audio 1 DAC, right
2 FIFO 1 = Audio 2 FIFO 2's complement mode. channel playback, after filter
signed 0 = Audio 2 FIFO unsigned (offset 8000). stage).
mode 1 0 Audio 2 DAC, right channel out-
put.
1 FIFO 1 = Audio 2 FIFO stereo mode.
1 1 Mono mix of left and right record
stereo 0 = Mono data.
level stage outputs. FDXO is
mode
controlled by record source
0 FIFO 1 = Audio 2 FIFO 16-bit mode. select (0Ch/1Ch) and record
16-bit 0 = Audio 2 FIFO 8-bit mode. level (B4h) registers.
mode
0 FDXI mix 1 = FDXI is mixed with AOUTL and AOUTR
enable after the playback mixer, Spatializer audio pro-
Audio 2 Playback Volume (7Ch, R/W) cessor, and master volume stages. Mix is unity
Audio 2 volume left Audio 2 volume right gain (no gain).
0 = FDXI is not mixed with AOUTL and
7 6 5 4 3 2 1 0
AOUTR.
This register controls the playback volume for the second
audio channel. This register is reset to zero by hardware
reset.

ESS Technology, Inc. SAM0025A-062397 77


PRELIMINARY ES1879 DATA SHEET
REGISTERS

Test Register (7Eh, R/W) Table 26 Test Bus Assignments


ADC test Test bus MIDI loop- FM test DSP loop- 2nd DMA SEL[3:0] TST[7:0] in Test Mode 1 TST[7:0] in Test Mode 2
0
enable enable back test enable back test test enable
0 DAC/ADC1 data left [7:0] DAC2 data left [7:0]
7 6 5 4 3 2 1 0
1 DAC/ADC1 data left [15:8] DAC2 data left [15:8]
This register is a test register. 2 DAC/ADC1 data right [7:0] DAC2 data right [7:0]

Bits Definitions: 3 DAC/ADC1 data right [15:8] DAC2 data right [15:8]

Bits Name Description 4 Music DAC data left [7:0] Spatializer ADC data [7:0]
7 ADC test 1 = ADC logic test mode: 5 Music DAC data left [15:8] Spatializer ADC data [15:8]
enable GPI replaces left ADC comparator input and 6 Music DAC data right [7:0] 7:4 XSEL[3:0]
Spatializer ADC comparator input; inverted 3:2 XMIX[1:0]
GPI replaces right ADC comparator input. 1 IETPG
6:5 Test bus When either of these bits is high, signals 0 IHOLD
enable between the digital and analog parts of the 7 Music DAC data right [15:8] SPGAIN [7:0]
chip are available via an e-bit output bus con-
8 7 MOEN 7 ENSPZR
sisting of:
6 EN26DB 6 SPCLK
TST[7:0] = {DRQB, IRQE, IRQD, IRQC, IRQB,
5:4 SRCSEL[1:0] 5 SPMONO
GPO2, GPO1, GPO0}
4 SPEVIN
The data on the bus is selected by a 4-bit
3 PDN 3–
select code:
2 CCK 2 SPETPG
SEL[3:0] = {SWD, SWC, SWB, SWA}
1 FILTCLK2 1 SPADCLK
See Table 26 below.
0 FILTCLK1 0 SPLR
4 MIDI 1 = MSO is internally connected to MSI, loop-
loopback ing back the MIDI transmitted from either the 9 7 CAL FBC[7:0]
test MPU-401 port or the Sound Blaster-compatible 6:5 MOSEL[1:0]
method. 4 ADCMODE1
0 = Disable MIDI loopback test. 3 ADCMODE0
2 MONOE
3 FM test 1 = The four normal FM registers can only be 1 SCFBYP2
enable accessed via Audio_Base+0h to 0 SCFBYP1
Audio_Base+3h. Four FM test registers are
accessed via 388h to 38Bh. 10 7 ADCLK FBC[15:8]
6 EVIN1R
2 DSP 1 = DSP loopback test mode enabled.
5 HOLD1R
loopback 1. Internally, data that would normally be
4 ETPG1R
test transmitted out DX is looped back to
3 EVIN1L
replace data normally received by DR.
2 HOLD1L
2. The ES689/69x serial interface data 1 ETPG1L
has a 32-bit shift register. The shift out 0 MISEL
data from the last stage appears on the
11 7:6 FSELR[1:0] FBC[23:16]
DX pin.
5:4 FSELL[1:0]
3. The 125 Hz clock used by hardware 3 HOLD2
volume control and the DRQ latch 2 ETPG2
circuits is sped up by a factor of four. 1 FMHOLD
0 = DSP loopback test mode disabled. 0 FMETPG
1 2nd 1 = Enable second DMA test mode. Reading 12 7:4 IVOLR[3:0] I2S data left[7:0]
DMA test mixer register 74h returns data from the audio 3:0 IVOLL[3:0]
enable 2 FIFO and acts as a sample rate strobe to the
13 7 OVOLR[8] I2S data left[15:8]
FIFO in place of the normal sample rate gener-
6 OVOLL[8]
ator.
5:4 MIXSEL[1:0]
0 = Disable second DMA test mode.
3:2 OSELR[1:0]
0 – Reserved. Always write zero. 1:0 OSELL[1:0]
14 OVOLL[7:0] I2S data right[7:0]
15 OVOLR[7:0] I2S data right[15:8]

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ES1879 DATA SHEET PRELIMINARY
REGISTERS

Controller Registers
This is a summary and description of the controller registers. These registers are written to and read from using
commands of the format Axh or Bxh. To enable access to these registers, send the command C6h.

Table 27 ESS Controller Registers Summary


Reg D7 D6 D5 D4 D3 D2 D1 D0 Description
A1h Clock source Sample rate divider S/W reset, unknown
S/W reset, setup for 8 kHz
A2h Filter clock divider
sampling
A4h Low byte Audio 1 transfer counter reload
A5h High byte Audio 1 transfer counter reload
Enable
Mono/stereo
A8h 0 0 0 1 record 0 Analog control
select
monitor
Enable IRQ Enable IRQ for
Game-com-
B1h ovf Ext mode FIFO1 HE status x Audio 1 interrupt Legacy audio interrupt control
patible IRQ
DMA cntr edge
Enable DRQ Enable DRQ
Game-com-
B2h for Ext mode game-compatible x Audio 1 DRQ Audio DRQ control
patible DRQ
DMA DMA
B4h Left Channel Record Level Right Channel Record Level Record Level
B5h Low byte DAC direct access holding
B6h High byte DAC direct access holding
Stereo/
Enable FIFO Reserved. Set 16-bit/8-bit Gener-
Mono
B7h to/from opposite Data type select 1 mode 0 ate load Audio 1 control 1
mode
CODEC polarity of bit 3 select signal
select
DMA Trans-
CODEC
B8h 0 0 0 0 DMA mode read/ fer Audio 1 control 2
mode
write enable
B9h 0 0 0 0 0 0 Transfer type Audio 1 transfer type
Disable time delay
BAh 0 Sign Adjust magnitude Left channel ADC offset adjust
on analog wake-up
Right channel ADC offset
BBh 0 Sign Adjust magnitude
adjust

Controller Register Descriptions

Audio 1 Sample Rate Generator (A1h, R/W) Bit Definitions:


Clock source Sample rate divider Bits Name Description
7 6 5 4 3 2 1 0 7 Clock 1 = clock source is 795.5 kHz for sample
source rates higher than 22 kHz.
This register should be programmed for the sample rate 0 = clock source is 397.7 kHz for sample
for all DAC operations in Extended mode. rates lower than or equal to 22 kHz.
6:0 Sample Signed sample rate divider.
The clock source for the sample rate generator is rate divider
397.7 kHz if bit 7 is 0 and 795.5 kHz if bit 7 is 1.
The sample rate is determined by the two’s complement
divider in bits 7:0:
Sample_Rate = 397.7 kHz / (128-x) if bit 7 = 0.
= 795.5 kHz / (256-x) if bit 7 = 1.

where x = value in bits 6:0 of register A1h.

ESS Technology, Inc. SAM0025A-062397 79


PRELIMINARY ES1879 DATA SHEET
REGISTERS

Audio 1 Filter Clock Divider (A2h, R/W) Analog Control (A8h, R/W)
Filter clock divider Record monitor Stereo/mono
0 0 0 1 0
enable select
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
This register controls the low-pass frequency of the
switch-capacitor filters inside the ES1879. Generally, the When programming the FIFO for DMA playback, modify
filter roll-off should be positioned at 80%-90% of the only bits 1:0. When programming the FIFO for DMA
Sample_Rate/2 frequency. The ratio of the roll-off record, modify only bits 3, 1, and 0. Read this register first
frequency to the filter clock frequency is 1:82. In other to preserve the remaining bits.
words, first determine the desired roll-off frequency by
taking 80% of the Sample_Rate divided by 2, then multiply Bit Definitions:
by 82 to find the desired filter clock frequency. Use the Bits Name Description
formula below to determine the closest divider: 7:5 – Reserved. Always write 0.
Filter_Clock_Frequency = 7.16 MHz / (256-Filter_Divider_Register) 4 – Reserved. Always write 1.
3 Record 1 = Enable record monitor.
Audio 1 Transfer Count Reload (A4h, R/W) monitor 0 = Disable record monitor.
DMA transfer count reload – low byte enable
7 6 5 4 3 2 1 0 2 – Reserved. Always write 0.
1:0 Stereo/ Select operation mode of first DMA converters.
On reset, this register assumes the value of 00h. mono bit 1 bit 0 Mode
select 0 0 Reserved.
Audio 1 Transfer Count Reload (A5h, R/W) 0 1 Stereo.
1 0 Mono.
DMA transfer count reload – high byte
1 1 Reserved.
7 6 5 4 3 2 1 0

On reset, this register assumes the value of F8h.


The FIFO control logic of the ES1879 has a 16-bit counter
for controlling transfers to and from the FIFO. These
registers are the reload value for that counter, which is the
value that gets copied into the counter after each overflow
(plus at the beginning of the initial DMA transfer). The
counter is incremented after each byte is successfully
transferred by DMA. Since the counter counts up towards
FFFFh and then overflows, the reload value is in two’s
complement form.
For Auto-Initialize mode DMA, the counter is used to
generate interrupt requests to the system processor. In
this mode, the ES1879 allows continuous DMA. In a
typical application, the counter is programmed to be one-
half of the DMA buffer maintained by the system
processor. In this application, an interrupt is generated
whenever DMA switches from one half of the circular
buffer to the other.
For Normal mode DMA, DMA requests are halted at the
time that the counter overflows, until a new DMA transfer
is commanded by the system processor. An interrupt
request is generated to the system processor if bit 6 of
register B1h is set high.

80 SAM0025A-062397 ESS Technology, Inc.


ES1879 DATA SHEET PRELIMINARY
REGISTERS

Legacy Audio Interrupt Control (B1h, R/W) DRQ Control (B2h, R/W)
Game- Enable IRQ for Game- Enable DRQ for Enable DRQ
Enable IRQ ovf Ext
compatible FIFO1 HE status x Audio 1 interrupt compatible Extended mode game compatible x Audio 1 DRQ
mode DMA cntr
IRQ edge DRQ DMA DMA
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Bit Definitions: Bit Definitions:


Bits Name Description Bits Name Description
7 Game-com- Reserved for Compatibility mode. Leave zero 7 Game Reserved for Compatibility mode. Leave zero
patible IRQ for Extended mode. compatible for Extended mode.
6 Enable Set high to receive interrupts for each over- DRQ
IRQ ovf Ext flow of the ES1879 DMA counter in Extended 6 Enable 1 = Enable DRQ outputs and DACKB inputs
mode DMA mode. DRQ for for DMA transfers in Extended mode.
cntr Extended 0 = Enable block I/O to/from the FIFO in
5 Enable Set high to receive interrupts for FIFO Half- mode DMA Extended mode.
IRQ for Empty transitions when doing block I/O 5 Enable Reserved for Compatibility mode. Leave zero
FIFO1 HE to/from the FIFO in Extended mode. DRQ game for Extended mode.
status edge compatible
4 – No function. The audio device activate bit DMA
serves the purpose of enabling the interrupt 4 – No function. The DRQ lines always drive
pin (PnP register 30h for LDN 1). (there is no enable). If neither bit 5 nor bit 6 is
3:0 Audio 1 Read-only. Decode the selected interrupt set high, the first audio DRQ is always low.
interrupt number for the first audio interrupt as follows: The pull-down feature of DRQ pins in previous
bit 3 bit 2 bit 1 bit 0 Audio 1 Interrupt parts was discontinued in the ES1879.
0 0 0 0 2, 9, all others 3:0 Audio 1 Read-only. The selected DMA channel num-
0 1 0 1 5 DRQ ber for the first audio DMA channel are
1 0 1 0 7 decoded to set these bits as follows:
1 1 1 1 10 bit 3 bit 2 bit 1 bit 0 Audio 1 DRQ
0 1 0 1 0
1 0 1 0 1
1 1 1 1 3
0 0 0 0 all others

ESS Technology, Inc. SAM0025A-062397 81


PRELIMINARY ES1879 DATA SHEET
REGISTERS

Record Level (B4h, R/W) Audio 1 Control 1 (B7h, R/W)


Left channel record level Right channel record level Set
Enable FIFO FIFO FIFO FIFO
oppo- Generate
7 6 5 4 3 2 1 0 to/from signed 1 stereo 16-bit 0
site bit load signal
CODEC mode mode mode
3
Register B4h allows for independent left and right record 7 6 5 4 3 2 1 0
levels. Each channel has 16 levels (excluding mute). The
amount of gain or attenuation for each level is different for Bit Definitions:
microphone than for all other sources. The record levels Bits Name Description
are listed in the following table.
7 Enable 1 = Enable first DMA FIFO connection to
FIFO to/ DAC or ADC. This allows transfers to/from
Gain for Other from the FIFO and the analog circuitry.
Record Level Gain for Mic
Sources CODEC 0 = Disable first DMA FIFO connection to
0 +0 dB -6.0 dB DAC or ADC.
6 Set opposite Reserved function. This bit must be set to
1 +1.5 dB -4.5 dB
bit 3 the opposite polarity of bit 3: high for mono
2 +3.0 dB -3.0 dB and low for stereo.
3 +4.5 dB -1.5 dB 5 FIFO signed 1 = First DMA FIFO 2’s complement mode
4 +6.0 dB 0 dB mode (signed data).
0 = First DMA FIFO unsigned (offset 8000).
5 +7.5 dB +1.5 dB
4 – Reserved. Always write 1.
6 +9.0 dB +3.0 dB
3 FIFO stereo 1 = First DMA FIFO stereo mode.
7 +10.5 dB +4.5 dB mode 0 = First DMA FIFO mono mode.
8 +12.0 dB +6.0 dB Bit 6 must be set at the opposite polarity of
this bit: high for mono, low for stereo.
9 +13.5 dB +7.5 dB
2 FIFO 16-bit 1 = First DMA FIFO 16-bit mode.
10 +15.0 dB +9.0 dB mode 0 = First DMA FIFO 8-bit mode.
11 +16.5 dB +10.5 dB 1 – Reserved. Always write 0.
12 +18.0 dB +12.0 dB 0 Generate Write 1. Generates a load signal that copies
13 +19.5 dB +13.5 dB load signal DAC Direct Access Holding register to DAC
on the next sample rate clock edge (sample
14 +21.0 dB +15.0 dB
rate is determined by Extended mode regis-
15 +22.5 dB +16.5 dB ter A1h). This bit is cleared after the holding
register is copied to the DAC.
DAC Direct Access Holding (B5h, R/W)
DAC direct access holding – low byte Audio 1 Control 2 (B8h, R/W)
7 6 5 4 3 2 1 0 CODEC DMA DMA read DMA transfer
0 0 0 0
mode mode enable enable

Low byte of DAC direct access holding register. Because 7 6 5 4 3 2 1 0


the bus between the ISA bus and the FIFO is only 8 bits
wide, the ES1879 needs a location for storage of 16-bit Bit Definitions:
data. Registers B5h and B6h serve this function. Bits Name Description
7:4 – Reserved. Always write 0.
DAC Direct Access Holding (B6h, R/W) 3 CODEC 1 = first DMA converters in ADC mode.
DAC direct access holding – high byte mode 0 = first DMA converters in DAC mode.
7 6 5 4 3 2 1 0 2 DMA mode 1 = Auto-Initialize DMA mode.
0 = Normal DMA mode.
High byte of DAC direct access holding register. Because 1 DMA read 1 = first DMA is read (e.g., for ADC opera-
the bus between the ISA bus and the FIFO is only 8 bits enable tion).
wide, the ES1879 needs a location for storage of 16-bit 0 = first DMA is write (e.g., for DAC opera-
data. Registers B5h and B6h serve this function. tion).
0 DMA First DMA active-low reset. When low, first
transfer DMA is allowed to proceed.
enable

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ES1879 DATA SHEET PRELIMINARY
REGISTERS

Audio 1 Transfer Type (B9h, R/W)


0 DMA transfer type select
Code Offset Code Offset
7 6 5 4 3 2 1 0 00h 0 10h -64
01h +64 11h -128
Bit Definitions: 02h +128 12h -192
Bits Name Description
03h +192 13h -256
7:2 – Reserved. Always write 0.
04h +256 14h -320
1:0 DMA Selects the DMA transfer type for the first
transfer DMA: 05h +320 15h -384
type select bit 1 bit 0 Transfer Type Bytes/DMA Request 06h +384 16h -448
0 0 Single –
07h +448 17h -512
0 1 Demand 2
1 0 Demand 4 08h +512 18h -576
1 1 Reserved – 09h +576 19h -640
0Ah +640 1Ah -704
Left Channel ADC Offset Adjust (BAh, R/W)
0Bh +704 1Bh -768
Disable time delay on
0 Sign Adjust magnitude
analog wake up 0Ch +768 1Ch -832
7 6 5 4 3 2 1 0 0Dh +832 1Dh -896
0Eh +896 1Eh -960
This register is reset to zero by hardware reset and is
unaffected by software reset. 0Fh +960 1Fh -1024

Bit Definitions: Formula:


Bits Name Description bit 4 = 0: offset = 64 * bits[3:0]
7:6 – Reserved. Always write 0. bit 4 = 1: offset = -64 * (bits[3:0] +1)
5 Disable time Normally, the AOUT_L and AOUT_R pins To calculate the offset adjust code, first measure the ADC
delay on are muted for 100 msec ± 20 msec after offset for both right and left channels before adjustment by
analog hardware reset or after the analog sub- following these steps:
wake up systems wake from power-down. Set high to
disable delay. 1. Program Extended mode registers BAh and BBh
This bit is cleared by hardware reset. bits 4:0 to be zero (no digital offset).
4:0 Sign/Adjust See the explanation for bits 4:0 following 2. Select a zero-amplitude (or low amplitude)
magnitude register BBh. recording source.
3. Set the recording volume to minimum by setting
Right Channel ADC Offset Adjust (BBh, R/W)
Extended mode register B4h to zero.
0 Sign Adjust magnitude
4. Make a stereo 16-bit two’s complement recording
7 6 5 4 3 2 1 0
at 11 kHz sample rate of 2048 stereo samples
(2048 stereo samples = 4096 words = 8192 bytes,
This register is reset to zero by hardware reset and is
which is about 190 msec).
unaffected by software reset.
5. Use the last 1024 stereo samples to calculate a
Bit Definitions: long-term average for both left and right channels.
Bits Name Description 6. With this average DC offset, calculate the best
7:5 0 Reserved. Always write 0. digital offset to bring the sum closest to zero, using
the codes and offsets listed in the table above.
4:0 Sign/Adjust See the following explanation for bits 4:0.
magnitude
Bits 4 (sign) and 3:0 (adjust magnitude) of the ADC Offset
Adjust register cause a constant value to be added to the
ADC converter output, as shown in the following:

ESS Technology, Inc. SAM0025A-062397 83


PRELIMINARY ES1879 DATA SHEET
AUDIO MICROCONTROLLER COMMAND SUMMARY

AUDIO MICROCONTROLLER COMMAND SUMMARY


Table 28 Command Summary
Data Byte(s)
Command Function
Write/Read
10h 1 write Direct write 8-bit DAC. Data is 8-bit unsigned format.
11h 2 writes Direct write 16-bit DAC. Data is 16-bit unsigned format, first low byte then high byte.
14h 2 writes Start Normal mode DMA for 8-bit DAC transfer. Data is transfer count-1, least byte first. Stereo DAC
transfer if Stereo flag is set in Mixer register 0Eh. Maximum sample rate is 44 kHz mono, 22 kHz ste-
reo.
15h 2 writes Start Normal mode DMA for 16-bit DAC transfer. Data is transfer count-1, least byte first. Stereo
DAC transfer if Stereo flag is set in Mixer register 0Eh. Maximum sample rate is 22 kHz mono,
11 kHz stereo.
1Ch Start Auto-Initialize mode DMA for 8-bit DAC transfer. Block size must be previously set by com-
mand 48h. Stereo DAC transfer if Stereo flag is set in Mixer register 0Eh. Maximum sample rate is
44 kHz mono, 22 kHz stereo.
1Dh Start Auto-Initialize mode DMA for 16-bit DAC transfer. Block size must be previously set by com-
mand 48h. Stereo DAC transfer if Stereo flag is set in Mixer register 0Eh. Maximum sample rate is
22 kHz mono, 11 kHz stereo.
20h 1 read Direct mode 8-bit ADC. Data is 8-bit unsigned. Firmware-controlled input volume for AGC.
21h 2 read Direct mode 16-bit ADC, returns least byte first. Data is 16-bit unsigned format. Input volume con-
trolled via command DDh.
24h 2 writes Start Normal mode DMA for 8-bit ADC transfer. Data is transfer count-1, least byte first. Firmware-
controlled input volume for AGC. Maximum sample rate is 22 kHz: use command 99h for higher
rates up to 44 kHz.
25h 2 writes Start Normal mode DMA for 16-bit ADC transfer. Data is transfer count-1, least byte first. Input vol-
ume controlled via command DDh. Maximum sample rate is 22 kHz.
2Ch Start Auto-Initialize mode DMA for 8-bit ADC transfer. Block size must be previously set by com-
mand 48h. Firmware-controlled input volume for AGC. Maximum sample rate is 22 kHz: use com-
mand 98h for higher rates up to 44 kHz.
2Dh Start Auto-Initialize mode DMA for 16-bit ADC transfer. Block size must be previously set by com-
mand 48h. Input volume is controlled via command DDh. Maximum sample rate is 22 kHz.
30h/31h MIDI input mode. Detects MIDI serial input data and transfers to Data register, setting Data-Available
flag in register Audio_Base+Eh. Command 31h will also generate an interrupt request for each byte
received.
Exit MIDI input mode by executing a write to port Audio_Base+Ch. The data written is ignored. A
software reset will also exit this mode.
34h/35h MIDI UART mode. Acts like commands 30h and 31h, except that any data written to Audio_Base+Ch
will be transmitted as MIDI serial output data. The only way to exit this mode is a software reset.
38h 1 write MIDI output. Transmit one byte.
40h 1 write Set time constant, X, for timer used for DMA mode DAC/ADC transfers: rate = 1 MHz / (256-X). X
must be less than or equal to 233. For stereo DAC, program sample rate for twice the per-channel
rate.
41h 1 write Alternate set time constant, X: rate = 1.5 MHz / (256-X). This command provides more accurate tim-
ing for certain rates such as 22,050. X must be less than or equal to 222. For stereo DAC, program
sample rate for twice the per-channel rate.
42h 1 write Set filter clock independently of timer rate. (Note that the filter clock is automatically set by com-
mands 40h/41h.) Filter clock rate = 7.16E6 / (256-X).
The relationship between the low-pass filter -3 dB point and the filter clock rate is approximately
1:82.
48h 2 writes Set block size to -1 for High-Speed mode and Auto-Initialize mode transfer, least byte first.

84 SAM0025A-062397 ESS Technology, Inc.


ES1879 DATA SHEET PRELIMINARY
AUDIO MICROCONTROLLER COMMAND SUMMARY

Table 28 Command Summary (Continued)


Data Byte(s)
Command Function
Write/Read
64h 2 writes Start ESPCM® 4.3-bit (low compression) format DMA transfer to DAC. Data is transfer count-1, least
byte first.
65h 2 writes Same as command 64h, except with Reference Byte flag.
66h 2 writes Start ESPCM® 3.4-bit (medium compression) format DMA transfer to DAC. Data is transfer count-1,
least byte first.
67h 2 writes Same as command 66h, except with Reference Byte flag.
6Ah 2 writes Start ESPCM® 2.5-bit (high compression) format DMA transfer to DAC. Data is transfer count-1, least
byte first.
6Bh 2 writes Same as command 6Ah, except with Reference Byte flag.
6Eh 2 writes Start ESPCM® 4.3-bit (low compression) format ADC, compression, and DMA transfer. Data is trans-
fer count-1, least byte first.
6Fh 2 writes Same as command 6Eh, except with Reference Byte flag.
74h 2 writes Start ADPCM 4-bit format DMA transfer to DAC. Data is transfer count-1, least byte first.
75h 2 writes Same as command 74h, except with Reference Byte flag.
76h 2 writes Start ADPCM 2.6-bit format DMA transfer to DAC. Data is transfer count-1, least byte first.
77h 2 writes Same as command 76h, except with Reference Byte flag.
7Ah 2 writes Start ADPCM 2-bit format DMA transfer to DAC. Data is transfer count-1, least byte first.
7Bh 2 writes Same as command 7Ah, except with Reference Byte flag.
80h 2 writes Generate silence period. Data is number of samples-1.
90h Start Auto-Initialize, DMA 8-bit transfer to DAC. Transfer count must be previously set by command
48h.
91h Start DMA 8-bit transfer to DAC. Transfer count must be previously set by command 48h.
98h Start High-Speed mode, Auto-Initialize, DMA 8-bit transfer from ADC. Transfer count must be previ-
ously set by command 48h. There is no AGC. Input volume is controlled with command DDh. Maxi-
mum sample rate is 44 kHz.
99h Start High-Speed mode, DMA 8-bit transfer from ADC. Transfer count must be previously set by
command 48h. There is no AGC. Input volume is controlled with command DDh. Maximum sample
rate is 44 kHz.
Axh, Bxh, (where x = 00h to 0Fh) ES1879 Extension commands. Many of the Extension commands are used
Cxh to access the ES1879’s controller registers. For information on these registers, see the register
descriptions.
C0h Enable reads of ES1879 registers used for Extended Mode: Axh, Bxh.
C1h Resume after suspend.
C6h Enable ES1879 Extension commands Axh, Bxh. Must be issued after every reset.
C7h Disable ES1879 Extension commands Axh, Bxh.
D0h Pause DMA. Internal FIFO operations will continue until the FIFO is empty (DAC transfer) or full
(ADC transfer). It is not necessary to use this command to stop DMA if the transfer is completed nor-
mally and the end-of-DMA interrupt is generated.
D1h Enable voice DAC input to mixer.
D3h Disable voice DAC input to mixer.
D4h Continue DMA after command D0h.
D8h 1 read Return voice DAC enable status:
0 = disabled
FFh = enabled

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PRELIMINARY ES1879 DATA SHEET
AUDIO MICROCONTROLLER COMMAND SUMMARY

Table 28 Command Summary (Continued)


Data Byte(s)
Command Function
Write/Read
DCh 1 read Return current input gain, 0-15 (valid during 16-bit ADC and 8-bit “High-Speed mode” ADC).
DDh 1 write Write current input gain, 0-15 (valid during 16-bit ADC and 8-bit “High-Speed mode” ADC).
E1h 2 reads Return version number high (3), followed by version number low (1). This indicates Sound Blaster
Pro compatibility.

86 SAM0025A-062397 ESS Technology, Inc.


ES1879 DATA SHEET PRELIMINARY
POWER MANAGEMENT

POWER MANAGEMENT
Power management in the ES1879 is controlled by PnP 2. Idle power-down. The microcontroller is stopped or
Configuration register 2Dh. In previous AudioDrive® chips, slowed. Application software is not running. The
power management was controlled by I/O port ES1879 is put in full power-down mode by BIOS. The
Audio_Base+7h. Only bit 5 (FM reset) and bit 7 (suspend power supply is still connected to the chip. Later, the
request) of I/O port Audio_Base+7h are supported in the BIOS returns the ES1879 to full power up.
ES1879. 3. Power reduction. If the system can generate an
GPO, XSD, and XSC are not affected during power-down. System Management Interrupt (SMI) upon I/O access
XA[3:0] are high-impedance during power-down Modes 0 to the audio and FM addresses, then the BIOS can
and 1. implement a power reduction technique: the BIOS
periodically polls the activity flags of the ES1879 in
Power Management Characteristics order to determine if the chip is in use. If not in use for
some period, it can power down the chip and enable
The ES1879 has four power modes. The mode is
the SMI. The first application to access the audio or FM
determined by bits 1 and 0 of Vendor-Defined Card-Level
address space will trigger the SMI, which causes the
register 2Dh.
BIOS to power up the ES1879, and deactivate the SMI.
In any mode, the configuration device can always be read BIOS power management is well suited to a DOS
and written. environment. It must also work with the ES1879 Windows
driver which implements power management as well.
Mode Transitions
The mode can be changed at any time with only one Suspend-to-Disk / Resume-from-Disk
restriction: if a crystal is connected to XI/XO, and the chip Suspend-to-Disk is the name given to the procedure
is in mode 0, then the chip must be placed in mode 1 for a where the entire context of the ES1879 is uploaded to be
period of 25 milliseconds or more to allow the oscillator to saved on disk. After saving the context, power can be
settle, before changing to mode 2 or mode 3. removed entirely from the ES1879. When power is re-
applied (and a hardware reset is given), the ES1879 state
Table 29 Power Mode Description must be restored from the saved context.
Mode Description Notes
The suspend procedure consists of the following tasks:
0 Full power-down. Crystal oscillator dis- All inputs
abled. AOUT_L/R held at approximately static at 1. Upload PnP configuration information.
CMR by high value resistors. VDDD or 2. Upload FM registers.
GND.
3. Upload mixer registers.
1 Crystal oscillator enabled. Analog pow- All inputs
ered down. other than
4. Upload MPU-401 state.
XI are 5. Upload audio state (using suspend request: bit 7 of
static. port "Audio_Base+7h").
2 Analog powered up. ES978 interface Digital An example DOS assembly language program is available
up. Joystick, MPU-401 up. I2S up. standby. demonstrating suspend-to-disk, followed by resume-from-
Audio, FM, ES689/ES690 interface, and disk, from a TSR that hooks the system timer interrupt.
DSP serial interface down. This program demonstrates how a DOS application such
3 Full power on. This is the state after Normal as a game can be suspended in the middle of audio
hardware reset. operating playback.
conditions.
DMA and Interrupts During Suspend-to-Disk
BIOS Power Management The ES1879 cannot properly suspend and resume during
audio playback unless the DMA and interrupt controller
There are at least three types of BIOS power
are also properly suspended. Alternatively, the DMA and
management:
interrupt controllers should not have power removed. In
1. Suspend-to-Disk. Here the context of the ES1879 is the latter case, it is important that all DRQ and IRQ lines
uploaded to disk, then power is removed from the are held low. All bus lines should be low if power is
ES1879. Later, power is applied to the ES1879 along removed from a device connected to the bus that has its
with a hardware reset, and the context of the chip is power supply removed. Also, during and after reset, the
downloaded.

ESS Technology, Inc. SAM0025A-062397 87


PRELIMINARY ES1879 DATA SHEET
POWER MANAGEMENT

ES1879 DRQ and IRQ lines are high-impedance. If a DRQ


or IRQ line floats high, it can produce a false DMA cycle or
interrupt.

88 SAM0025A-062397 ESS Technology, Inc.


ES1879 DATA SHEET PRELIMINARY
ELECTRICAL CHARACTERISTICS

ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings The ES1879 is designed to operate at case temperatures
of less than 78 °C.
WARNING: Stressing the device beyond the Absolute
Rating Symbol Value Maximum Ratings may cause permanent damage. These
Analog supply voltage range VDDA -0.3 to 7.0 V are stress ratings only. Operation beyond the Operating
Digital supply voltage range VDDD -0.3 to 7.0 V Conditions is not recommended, and extended exposure
beyond the Operating Conditions may affect device
Input voltage VIN -0.3 to 7.0 V
reliability.
Operating temperature range TA 0 to 70 °C
Storage temperature range TSTG -50 to 125 °C Operating Conditions
Digital supply voltage 3.0 V to 5.50 V
Thermal Characteristics
Analog supply voltage 4.75 V to 5.25 V

DC Electrical Characteristics

Table 30 Digital Characteristics


Symbol Parameter Min Typ Max Unit (conditions)
VIH1 Input high voltage: all inputs except XI 2.0 V VDDD = min
VIH2 Input high voltage: XI 3.0 V VDDD = min
VIL Input low voltage 0.8 V VDDD = max
VOL1 Output low voltage: all outputs except 0.4 V IOL = 4 mA,
D[7:0], IRQ(A-E), DRQ(A-C), XSC, XSD VDDD = min
VOH1 Output high voltage: all outputs except 2.4 V IOH = -3 mA,
D[7:0], IRQ(A-E), DRQ(A-C), XSC, XSD VDDD = max
VOL2 Output low voltage: D[7:0], IRQ(A-E), DRQ(A-D), XSC, XSD 0.4 V IOL = 16 mA,
VDDD = min
VOH2 Output high voltage: D[7:0], IRQ(A-E), DRQ(A-D), XSC, XSD 2.4 V IOH = -12 mA,
VDDD = max
VOL3 Output low voltage 0.4 V IOL = 0.8 mA

Table 31 Analog Characteristics


(VDDA = 5.0 V ± 5%; TA = 25 °C)
Pins Parameter Min Typ Max Units
CMR Reference voltage 2.25 volts
LINE_L, LINE_R, Input impedance 30k 70k 100k Ω
AUXA_L, AUXA_R,
AUXB_L, AUXB_R,
MIC
CIN_L, CIN_R 35k 50k 65k Ω
FDXI 30k 70k 100k Ω
FOUT_L, FOUT_R Output impedance 3.5k 5k 6.5k Ω
AOUT_L, 10k 10k Ω
AOUT_R max load for full-scale output range
FDXO 5k 6.5k Ω

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PRELIMINARY ES1879 DATA SHEET
ELECTRICAL CHARACTERISTICS

Table 31 Analog Characteristics


(VDDA = 5.0 V ± 5%; TA = 25 °C) (Continued)
Pins Parameter Min Typ Max Units
MIC Input voltage range 10 125 mVp-p
LINE_L, LINE_R, 0.5 VDDA - 1.0 volts
AUXA_L, AUXA_R,
AUXB_L, AUXB_R
FDXI 3.5 Vp-p
AOUT_L, Output voltage range 0.5 VDDA - 1.0 volts
AOUT_R full-scale output range
FDXO 2.0 Vp-p
MIC Mic preamp gain 26 decibels

Power Management Characteristics

Table 32 Current Consumption for Power Modes


Typical IDDD Typical IDDD Typical IDDA
Mode
at 3.3V at 5.0V at 5.0V
0 10 µA 10 µA 10 µA
1 1 mA 3 mA 10 µA
2 2 mA 5 mA 70 mA
3 20 mA 30 mA 70 mA

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ES1879 DATA SHEET PRELIMINARY
ES1879 TIMING DIAGRAMS

ES1879 TIMING DIAGRAMS

t1

RESET

Figure 18 Reset Timing

AEN, A[11:0]

t2

IORB
t3
t4

D[7:0]

t5

Figure 19 I/O Read Cycle

AEN, A[11:0]

t2

IOWB
t3

t6 t7

D[7:0]

Figure 20 I/O Write Cycle

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PRELIMINARY ES1879 DATA SHEET
ES1879 TIMING DIAGRAMS

DRQ

t8

AEN
t10 t11

DACKB
t9

IOWB
t12
t6 t7

D[7:0]

Figure 21 Compatibility Mode DMA Write Cycle1

DRQ

t10

AEN
t11

t13
DACKB

IORB
t12
t5

D[7:0]
t4

Figure 22 Compatibility Mode DMA Read Cycle

1.
In Compatibility mode DMA, the DMA request is reset by the acknowledge signal going low. In Extended mode DMA, the DMA request
is reset when the acknowledge signal is low AND the correct command signal is low – either IORB (for DMA read from I/O device) or
IOWB (for DMA write to I/O device). For Extended mode DMA, the time t10 is relative to the later of the falling edge of the acknowledge
signal or the command signal.

92 SAM0025A-062397 ESS Technology, Inc.


ES1879 DATA SHEET PRELIMINARY
ES1879 TIMING DIAGRAMS

DCLK

t15

FS

t16

t19
t16

DR D15 D14 D0

t15

t16

Figure 23 Serial Mode Receive Operation

t20

DCLK

t15

FS

t16

t19
t18

DX D15 D14 D1 D0

t17

Figure 24 Serial Mode Transmit Operation

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PRELIMINARY ES1879 DATA SHEET
ES1879 TIMING DIAGRAMS

IILR
t22

t21 t23 t24

IISCLK

t25 t26

IIDATA

Figure 25 Serial Input Timing for I2S Interface

IISCLK

IILR LEFT RIGHT

IIDATA R0* L15 L14 L13 L12 L0 R15 R14 R13 R12 R11 R10 R0

* Note: LSB of right channel, previous sample.

Figure 26 I2S Digital Input Format with 16 SCLK Periods

94 SAM0025A-062397 ESS Technology, Inc.


ES1879 DATA SHEET PRELIMINARY
TIMING CHARACTERISTICS

TIMING CHARACTERISTICS
Symbol Parameter Min Typ Max Unit
t1 Reset pulse width 300 ns
t2 IORB, IOWB pulse width 100 ns
t3 IORB, IOWB address setup time 10 ns
t4 Read data access time 70 ns
t5 Read data hold time 10 ns
t6 Write data setup time 5 ns
t7 Write data hold time 10 ns
t8 DMA request to AEN high 0 ns
t9 DMA request to DMA ACK low 10 ns
t10 DMA ACK to request release a
30 ns
t11 DMA ACK high to AEN low 0 ns
t12 DMA ACK to IOWB, IORB low 0 ns
t13 IOWB, IORB to DMA ACK release 20 ns
t14 Crystal frequency, XI/XO 14.318 MHz
t15 FS, DS setup time to DCLK falling edge 15 ns
t16 FS, DR hold time from DCLK falling edge 10 ns
t17 DX delay time from DCLK rising edge 20 ns
t18 DX hold time from DCLK rising edge 10 ns
t19 FS pulse width 60 500 ns
t20 DCLK clock frequency 2.048 MHz
t21 IISCLK delay 2 ns
t22 IISCLK setup 32 ns
t23 Bit clock low 22 ns
t24 Bit clock high 22 ns
t25 Data setup time 32 ns
t26 Data hold time 2 ns

a. In Compatibility mode DMA, the DMA request is reset by the acknowledge signal going low. In Extended mode DMA, the DMA request
is reset when the acknowledge signal is low AND the correct command signal is low – either IORB (for DMA read from I/O device) or
IOWB (for DMA write to I/O device). For Extended mode DMA, the time t10 is relative to the later of the falling edge of the acknowledge
signal or the command signal.

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PRELIMINARY ES1879 DATA SHEET
MECHANICAL DIMENSIONS

MECHANICAL DIMENSIONS

D1

A2 A1

E E1
ES1879
e e1
L b L1

Figure 27 ES1879 Physical Dimensions

Millimeters
Symbol Description
Min Nom Max
D Lead-to-lead, X-axis 15.75 16.00 16.25
D1 Package's outside, X-axis 13.90 14.00 14.10
E Lead-to-lead, Y-axis 15.75 16.00 16.25
E1 Package's outside, Y-axis 13.90 14.00 14.10
A1 Board standoff 0.05 0.10 0.15
A2 Package thickness 1.35 1.40 1.45
b Lead width 0.17 0.22 0.27
e Lead pitch 0.50
e1 Lead gap
L Foot length 0.45 0.60 0.75
L1 Lead length
Foot angle
Coplanarity 0.102
Leads in X-axis 25
Leads in Y-axis 25
Total leads 100
Package type SQFP

96 SAM0025A-062397 ESS Technology, Inc.


ES1879 DATA SHEET PRELIMINARY
APPENDIX A: ES1879 INTERNAL PNP RESOURCE ROM

APPENDIX A: ES1879 INTERNAL PNP RESOURCE ROM


; system00.DAT
; PnP Resource ROM for ES1879
;
; LDN0 Control Interface
; LDN1 Audio/FM/MPU-401
; LDN2 Joystick
; *********************************************************
;
; Start of ESS Proprietary Header (8 bytes)
;
; *********************************************************
0A5H ; PNP OK byte
059H ; IRQA = 9 IRQB = 5
0A7H ; IRQC = 7 IRQD = 10
00BH ; IRQE = 11 no more IRQF on ES1879
010H ; DRQA = 0 DRQB = 1
023H ; DRQC = 3 DRQD = 2 (not used)
000H ; MPU-401 part of audio, DRQ latching off
000H ; reserved
; *********************************************************
;
; Start of PNP Resource Header
;
; *********************************************************
016H, 073H, 018H, 079H ; "ESS1879" product id for ES1879
0FFH, 0FFH, 0FFH, 0FFH ; serial number FFFFFFFF (not supported)
02FH ; header checksum
00AH, 010H, 010H ; PNP 1.0, ESS version 1.0
082H, 023H, 000H, "ESS ES1879 Plug and Play AudioDrive"
; *******************************************************
;
; LOGICAL DEVICE 0 -- Configuration Ports
; 8 bytes at any I/O address that is a multiple of 8
;
; *******************************************************
015H, 016H, 073H, 000H, 009H, 000H ; ESS0009
047H, 001H, 000H, 008H, 0F8H, 00FH, 008H, 008H ; 800H-FF8H 8 bytes
; *******************************************************
;
; LOGICAL DEVICE 1 -- Audio Controller w/FM and MPU-401
;
; *******************************************************
015H, 016H, 073H, 018H, 079H, 000H ; ESS1879
; Basic configuration 0000
031H, 000H
02AH, 002H, 008H ; DMA 0: DRQ 1
02AH, 009H, 008H ; DMA 1: DRQ 0 3
022H, 020H, 000H ; INT 0: IRQ 5
047H, 001H, 020H, 002H, 020H, 002H, 000H, 010H ; 220 16 bytes
047H, 001H, 088H, 003H, 088H, 003H, 000H, 004H ; 388 4 bytes
047H, 001H, 030H, 003H, 030H, 003H, 000H, 002H ; 330 2 bytes
; Basic configuration 0001
031H, 001H

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PRELIMINARY ES1879 DATA SHEET
APPENDIX A: ES1879 INTERNAL PNP RESOURCE ROM

02AH, 002H, 008H ; DMA 0: DRQ 1


02AH, 009H, 008H ; DMA 1: DRQ 0 3
022H, 0A0H, 006H ; INT 0: IRQ 5 7 9 10
047H, 001H, 020H, 002H, 040H, 002H, 020H, 010H ; 220 240 16 bytes
047H, 001H, 088H, 003H, 088H, 003H, 000H, 004H ; 388 4 bytes
047H, 001H, 000H, 003H, 030H, 003H, 030H, 002H ; 300 or 330 2 bytes
; Basic configuration 0002
031H, 001H
02AH, 00BH, 008H ; DMA 0: DRQ 0 1 3
02AH, 00BH, 008H ; DMA 1: DRQ 0 1 3
022H, 0A0H, 00EH ; INT 0: IRQ 5 7 9 10 11
047H, 001H, 020H, 002H, 080H, 002H, 020H, 010H ; 220 240 260 280 16 bytes
047H, 001H, 088H, 003H, 088H, 003H, 000H, 004H ; 388 4 bytes
047H, 001H, 000H, 003H, 030H, 003H, 030H, 002H ; 300 or 330 2 bytes
; Basic configuration 0003
031H, 001H
02AH, 00BH, 008H ; DMA 0: DRQ 0 1 3
02AH, 00BH, 008H ; DMA 1: DRQ 0 1 3
022H, 0A0H, 00EH ; INT 0: IRQ 5 7 9 10 11
047H, 001H, 020H, 002H, 080H, 002H, 020H, 010H ; 220 240 260 280 16 bytes
047H, 001H, 088H, 003H, 088H, 003H, 000H, 004H ; 388 4 bytes
047H, 001H, 000H, 008H, 0FEH, 00FH, 002H, 002H ; 800/801-FFE/FFF 2 bytes
; Basic configuration 0004
031H, 002H
02AH, 00BH, 008H ; DMA 0: DRQ 0 1 3
02AH, 00BH, 008H ; DMA 1: DRQ 0 1 3
022H, 0A0H, 00EH ; INT 0: IRQ 5 7 9 10 11
047H, 001H, 020H, 002H, 080H, 002H, 020H, 010H ; 220 240 260 280 16 bytes
047H, 001H, 000H, 008H, 0FCH, 00FH, 004H, 004H ; 800/804-FFC/FFF 4 bytes
047H, 001H, 000H, 008H, 0FEH, 00FH, 002H, 002H ; 800/801-FFE/FFF 2 bytes
038H ; end configurations
; *******************************************************
;
; LOGICAL DEVICE 2 -- Joystick
; Only choice is one address at 201.
;
; *******************************************************
015H, 016H, 073H, 000H, 001H, 000H ; ESS0001
031H, 000H ; Basic configuration 0000
047H, 001H, 001H, 002H, 001H, 002H, 000H, 001H ; 201 1 byte
; Windows 95 Joystick driver will only allow 200-20F!!!
031H, 001H ; Basic configuration 0001
047H, 001H, 000H, 002H, 00FH, 002H, 001H, 001H ; 200/200-20F/20F 1 byte
038H ; end dependent functions
01CH, 041H, 0D0H, 0B0H, 02FH ; Compatible ID: PNPB02F
079H, 0BFH ; end tag + checksum

98 SAM0025A-062397 ESS Technology, Inc.


ES1879 DATA SHEET PRELIMINARY
APPENDIX B: ES689/ES69X DIGITAL SERIAL INTERFACE

APPENDIX B: ES689/ES69X DIGITAL SERIAL INTERFACE


In order for the ES689/ES69x to acquire the FM DAC, bit DAC. The ES689/ES69x can be programmed to enter
4 of mixer register 48h inside the ES1879 must be set Activity-Detect mode using system exclusive command 4.
high. When bit 4 is set high, activity on the MCLK signal In this mode, the ES689/ES69x blocks the serial port
causes the FM DAC to be connected to the ES689/ES69x. output (i.e., sets MSD and MCLK low) if no MIDI input is
If MCLK stays low for more than a few sample periods, the detected on the MSI pin for a period of 5 seconds. It will
ES1879 reconnects the FM DAC to the FM synthesizer. resume output of data on the serial port as soon as a MIDI
input is detected on the MSI pin. This is the recommended
After reset, the ES689/ES69x transmits samples
mode of operation.
continuously. In this mode, bit 4 of mixer register 48h must
be set or cleared to assign the current owner of the FM

00 01 02 14 15 16 17 29 30 31 32 33 62 63 00
MCLK

MSB MSB
MSD L15 L14 L13 L1 L0 R15 R14 R2 R1 R0
Left Data Right Data

Figure 28 MIDI Interface Data Format

Bit Clock Rate (MCLK): 2.75 MHz


Sample Rate: 42,968.75 Hz
MCLK Clocks per Sample: 33 clocks (+ 31 missing clocks)
MSD Format: 16 bits, unsigned (offset 8000h), MSB first
MSD changes after rising edge of MCLK. Hold time
relative to MCLK rising edge is 0-25 nanoseconds.

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PRELIMINARY ES1879 DATA SHEET
APPENDIX C: I2S ZV INTERFACE REFERENCE

APPENDIX C: I2S ZV INTERFACE REFERENCE


(Excerpted from “PCMCIA Document Number 0135 – Release 010 1/15/96”)

Overview
The following diagram shows the system-level concept of the ZV port. The diagram demonstrates how TV in a window
could be achieved in a portable computer with a low-cost PC card. An MPEG or teleconferencing card could also be
plugged into the PC Card slot.

TV LCD CRT

256K x 16
DRAM ANALOG SPEAKERS
ENCODER

AMP

PC CARD
PC CARD
PCI LOCAL BUS

VGA
SLOT
AUDIO 4 AUDIO AUDIO
CODEC PCM INPUT
ZV PORT CONVERTER
(VIDEO) 19 PCM
AUDIO
INPUT
4

PC CARD VIDEO
PC CARD
HOST VIDEO INPUT
INTERFACE DECODER
ADAPTER NTSC/PAL
RF SIGNAL
19
MOTHERBOARD VIDEO & CONTROL

Figure 29 Example ZV Port Implementation

The Audio Interface of data. There Serial Clock (SCLK) clocks the audio data
The ZV Port compliant PC card sends audio data to the into the input data buffer. The master clock (MCLK) is used
host computer using Pulse Code Modulation (PCM). The to operate the digital interpolation filter and the delta-
audio data is transferred using the serial I2S format. The sigma modulator.
audio circuitry in the host system is primarily a PCM DAC. Table 33 Common Clock Frequencies
The PCM audio DAC is a complete stereo digital-to- MCLK (MHz)
analog system including digital-interpolation, delta-sigma
LRCLK (KHz) 256x 384x
digital-to-analog conversion, digital de-emphasis, and
analog filtering. Only the normal power supply decoupling 22 5.632 8.448
components and one resistor and capacitor per channel 32 8.192 12.2880
for analog signal reconstruction are required. 44.1 11.2896 16.9344
The DAC accepts data at standard audio frequencies 48 12.2880 18.4320
including 48 kHz, 44.1 kHz, 32 kHz, and 22 kHz. Audio
data is input via the serial data input pin, SDATA. The Left/
Right Clock (LRCLK) defines the channel and delineation

100 SAM0025A-062397 ESS Technology, Inc.


ES1879 DATA SHEET PRELIMINARY
APPENDIX C: I2S ZV INTERFACE REFERENCE

LAPTOP / NOTEBOOK

+5 V
0.1 µF +10 µF
PC CARD VA+

SDATA
Audio *1.0 µF 600 Ω
Left Audio
Data SCLK AOUTL
Output
Processor LRCLK
56 kΩ **C

*1.0 µF 600 Ω
External MCLK
Right Audio
AOUTR
Clock Output
56 kΩ **C
GNDA

* Required for AC coupling only.


** C = 1/(2Π)(600)(IWR)(2)

Figure 30 Typical ZV Port Audio Implementation

ESS Technology, Inc. SAM0025A-062397 101


PRELIMINARY ES1879 DATA SHEET
APPENDIX C: I2S ZV INTERFACE REFERENCE

Audio Interface Timing

LRCLK
tslrs

tslrd tSCLKl tSCLKh

SCLK

tsdlrs tsdh

SDATA

Figure 31 Audio Interface Timing

Table 34 AC Parameters for Audio Signals


Symbol Parameter Min
tslrd LRCLK delay 2ns
tslrs LRCLK setup 32ns
tSCLKl bit clock low 22ns
tSCLKh bit clock high 22ns
tsdlrs data setup 32ns
tsdh data hold 2ns

LRCLK MCLK must be either 256 times or 384 times the desired
This signal determines which audio channel (left/right) is Input Word Rate (IWR). IWR is the frequency at which
currently being input on the audio serial data input line. words for each channel are input to the DAC and is equal
LRCLK is low to indicate the left channel and high to to the LRCLK frequency. The following table illustrates
indicate the right channel. Typical frequency values for this several standard audio word rates and the required SCLK
signal are 48 kHz, 44.1 kHz, 32 kHz, and 22 kHz. and MCLK frequencies. Typically, most devices operate
with 384 x Fs master clock.
The ZV Port audio DAC should support an MCLK
SCLK frequency of 384 x Fs. This results in the frequencies
This signal is the serial digital audio PCM clock. shown below.

LRCLK (kHz) SCLK (MHz) MCLK (MHz)


SDATA Sample Frequency 32 x Fs 384 x Fs
This signal is the digital PCM signal that carries the audio 22 0.704 8.448
information. Digital audio data is transferred using the I 2S
32 1.0240 12.2880
format.
44.1 1.4112 16.9344
48 1.5360 18.4320
MCLK
This signal is the master clock for the digital audio. MCLK
is asynchronous to LRCLK, SDATA, and SCLK.

102 SAM0025A-062397 ESS Technology, Inc.


ES1879 DATA SHEET PRELIMINARY
APPENDIX C: I2S ZV INTERFACE REFERENCE

I2S Format
The I2S format is shown in Figure 32 below. The digital
audio data is left channel-MSB justified to the high-to-low
going edge of the LRCLK plus one SCLK delay.

LRCLK Left Channel Right Channel

... ...
SCLK

SDATA 15 14 ... 3 2 1 0 15 14 13 12 ... 2 1 0

Figure 32 I2S Digital Input Format with 16 SCLK Periods

ESS Technology, Inc. SAM0025A-062397 103


PRELIMINARY ES1879 DATA SHEET
APPENDIX C: I2S ZV INTERFACE REFERENCE

ZV Port Pin Assignments


Table 35 shows the function of various PC card signals
when the ZV Port custom interface mode is set in the PC
Card Host Adapter. PC card signals not mentioned in the
table below, remain unchanged from the 16-bit PC card
I/O and Memory interface.
Table 35 ZV Port Interface Pin Assignments
PC Card I/O and Memory I/O and ZV Port Interface ZV Port
Comments
Pin Number Interface Signal Name Memory I/Oa Signal Name I/Oa
8 A10 I HREF O Horizontal Sync to ZV Port
10 A11 I VSYNC O Vertical Sync to ZV Port
11 A9 I Y0 O Video Data to ZV Port YUV:4:2:2 format
12 A8 I Y2 O Video Data to ZV Port YUV:4:2:2 format
13 A13 I Y4 O Video Data to ZV Port YUV:4:2:2 format
14 A14 I Y6 O Video Data to ZV Port YUV:4:2:2 format
19 A16 I UV2 O Video Data to ZV Port YUV:4:2:2 format
20 A15 I UV4 O Video Data to ZV Port YUV:4:2:2 format
21 A12 I UV6 O Video Data to ZV Port YUV:4:2:2 format
22 A7 I SCLK O Audio SCLK PCM Signal
23 A6 I MCLK O Audio MCLK PCM Signal
24:25 A[5:4] I RESERVED RFU Put in three state by Host Adapter
No connection in PC Card
26:29 A[3:0] I ADDRESS[3:0] I Used for accessing PC Card
33 IOIS16# O PCLK O Pixel Clock to ZV Port
46 A17 I Y1 O Video Data to ZV Port YUV:4:2:2 format
47 A18 I Y3 O Video Data to ZV Port YUV:4:2:2 format
48 A19 I Y5 O Video Data to ZV Port YUV:4:2:2 format
49 A20 I Y7 O Video Data to ZV Port YUV:4:2:2 format
50 A21 I UV0 O Video Data to ZV Port YUV:4:2:2 format
53 A22 I UV1 O Video Data to ZV Port YUV:4:2:2 format
54 A23 I UV3 O Video Data to ZV Port YUV:4:2:2 format
55 A24 I UV5 O Video Data to ZV Port YUV:4:2:2 format
56 A25 I UV7 O Video Data to ZV Port YUV:4:2:2 format
60 INPACK# O LRCLK O Audio LRCLK PCM Signal
62 SPKR# O SDATA O Audio PCM Data Signal

a. “I” indicates signal is input to PC card, “O” indi-


cates signal is output from PC card.

104 SAM0025A-062397 ESS Technology, Inc.


V CC
V CC V CC V CC V CC V CC V CC +12V

ESS Technology, Inc.


| LINK
ES1879 DATA SHEET

V DDA U3 | SWITCH.SCH
78L05 | 1 8 7 9 A MP . S CH
C3 C4 C5 C6 C4 4 C4 5 C5 0 1 3 | P CB US . S CH
OUT IN
. 1 . 1 . 1 . 1 . 1 . 1 R3 6 . 1
0 ohm G
N C8
D . 1
V DDA
1 U1
1 7 0 ES1 8 7 9 2
D[ 7 . . 0 ] 5 4 0
R3 R2
D0 16 41
A[ 1 5 . . 0 ] D1 D0 VVV V DDA
17 DDD C7 C2 3
V CC D2 D1 7. 5K 7. 5K A GND
18 D2 DDD GNDA 39 . 1 10
D3 19 DDD 55 C2 2
D4 D3 GNDA
20 10
NOT E : U2 D5 21 D4 33 C2 1 C9 A UX B L
INSTALL THIS A1 5 D6 D5 A UX B L
1 15 22 34
APPENDIX D: SCHEMATIC EXAMPLES

A Y0 D6 A UX B R
RESISTOR IF A1 4 2 14 D7 23 . 22 C1 0 DGND
T HE 7 4 L S 1 3 8 A1 3 B Y1 D7 A UX B R
3 13 35 . 22 C1 1
IS NOT C Y2 A UX A L
Y3 12 14 AEN A UX A R 36
INSTALLED 11 A0 2 . 22
Y4 A0
6 10 A1 3 37 . 22
A1 2 G1 Y5 A2 A1 CMR
4 9 4
G2 A Y6 A3 A2 C1 4
AEN 5 G2 B Y7 7 5 A3 MIC 38 C1 2 C1 3
A4 6 . 1 J2
A5 A4 C1 6 . 047 . 1 47
R2 0 0 ohm 7 4 L S1 3 8 7 A5 CA P 3 D 40 1
A6 8
A7 A6 C1 5 . 22 2 C D
9 42
A8 A7 F OUT R 3 V CC
10 A8 4
A9 11 45 C2 4 . 001
A1 0 A9 CINR 2. 2K 2. 2K
12 MITSUMI
APPENDIX D: SCHEMATIC EXAMPLES

A1 1 A1 0 C1 7 . 22
13 43
A1 1 F OUT L
RE S E T 73 RE S E T 5 J4
98 44 C2 5 . 001 4 L I NE R11 R12
IORB IORB CINL R1 0
99 3 R1 3
IOWB IOWB C1 8 . 22 2. 2K 2. 2K
DA CK B C 85 DACKBC/GPI3 LINEL 46 2
DA CK B B 87 DA CK B B 1
89 47 C1 9
DA CK B A DA CK B A LINER 3 . 5 mm S T E RE O J A CK
84 . 22
DRQC DRQC/GPI2
DRQB 86 DRQB A OUT L 48 A OUT L
88 V CC
DRQA DRQA
A OUT R 49 A OUT R 5 J3
IRQE 93 IRQ E/G PO 6 4
IRQD 94 IRQD/GPO5 P CS P K O 50 P CS P K O 3
95 2 MIC L1
IRQC IRQC/GPO4 R4 2. 2K
96 59 1
IRQB IRQ B/G PO 3 MS O MS O
IRQA 97 IRQA MS OUT R5 2 . 2 K MSI 3 . 5 mm S T E RE O J A CK
60
XSC MS I
XSD 56 XSD MSIC
57 XSC SWD 25
51 FERRITE BEAD
PRELIMINARY

XA3 XA3
XA2 52 XA2 SWC 26
XA1 53 XA1 8
54 27 MS I 15
XA0 XA0 SWB
7
68 28 14

Figure 33 ES1879 Schematic


IDATA IIDATA SWA
I S CL K 69 IISCLK 2. 2K 6
70 29 R6 13
ILR I I L R TD
2. 2K 5
30 R7 MS O 12
TC
MCL K 66 MCL K 2. 2K 4
67 31 R8 11
MS D MS D TB
J1 DX 2. 2K 3
62 32 10
1 DX TA
2 R1 DR 63 DR C2 6 C2 7 C2 8 C2 9 2
64 79 . 01 . 01 . 01 . 01 R9 9
DCL K DCL K GPI0
2 X1 HE A DE R 65 80 1
FS FS DRQD/GPI1 90 C3 0 C3 1 C3 2 C3 3
10K DACKBD/M UT E/GPI
PC-SPEAKER-IN 77 91 C2 0 . 0 1 . 0 1 . 0 1 P1
PSKI SEDI/VU/GPI5
SEDO/VD/GPI6 92 . 01
72 83
DOCK E D DOCK E D S E CL K / GP O2
S E CS 71 150pF
58 IP ROM G G G G GP O0 81
R2 1 75 XI NNNN GP O1 82
10K 76 DDDD CONNE CT OR DB 1 5
V CC XO DDDD
R1 8 R1 4 R1 5 R1 6 R1 7
Y1 10K 1M 1M 1M 1M
J P1 2 6 7 V CC
1 4 1 8
1
H 2 1 4 . 3 1 8 MHz U5
L 3 DRQD
8 V CC CS 1 DA CK B D
J P1 C2 C1 7 2 R3 4 1K
S MD P A DS L 9 3 L C6 6 NU CL K
22pF 22pF 6 3
H I N T ROM C5 5 5 ORG DI 4 V OL UP 1 8 7 8
GND DO V OL DN1 8 7 8
. 1 R3 5 1 K
US E 0 o h m R E S I S T O R 9 3 L C6 6
T O CONNE CT P A DS

SAM0025A-062397
105
106
DACKBA
DACKBD
DACKBB
DACKBC
IORB
IOWB
+12V
RESET
- 12V
C5 1
10

SAM0025A-062397
C5 3
VCC . 1

J 11
D[ 7 . . 0 ]
B1 A1
GN D -IOCHCK
B2 A2 D7
RESDRV D7
B3 A3 D6
+5V D6
B4 A4 D5
IRQA IRQ9 D5
B5 A5 D4
- 5V D4
B6 A6 D3
D R E Q2 D3
B7 A7 D2
- 12V D2
B8 A8 D1
- 0 WS D1
B9 A9 D0
+12V D0
B1 0 A1 0
GN D IOCHRDY
B1 1 A1 1
- S ME MW AEN AEN
B1 2 A1 2
- S ME MR A1 9
B1 3 A1 3
- I O W A1 8 A[ 1 5 . . 0 ]
B1 4 A1 4
- I O R A1 7
B1 5 A1 5
- DACK3 A1 6
B1 6 A1 6 A1 5
D R QC D R E Q3 A1 5
B1 7 A1 7 A1 4
- DACK1 A1 4
B1 8 A1 8 A1 3
D R QB D R E Q1 A1 3
B1 9 A1 9 A1 2
- REF SH A1 2
B2 0 A2 0 A1 1
SYSCL K A1 1 VCC
B2 1 A2 1 A1 0
IRQC IRQ7 A1 0
B2 2 A2 2 A9
IRQ6 A9
B2 3 A2 3 A8
IRQB IRQ5 A8
B2 4 A2 4 A7
IRQ4 A7
B2 5 A2 5 A6 R3 3
I R Q3 A6
B2 6 A2 6 A5 10K
- DACK2 A5
B2 7 A2 7 A4
TC A4
B2 8 A2 8 A3
AL E A3
B2 9 A2 9 A2
+5V A2 RST B
B3 0 A3 0 A1
1 4 . 3 MH Z A1
B3 1 A3 1 A0 D1 R3 2
GN D A0
RESET Q1
AT6 2 NPN
PRELIMINARY

C5 2 1 N4 1 4 8 100K

Figure 34 PC Interface
10

J 12
D1 C1
- ME MC S 1 6 - S B H E
D2 C2
-IOCS16 SA2 3
D3 C3
IRQD IRQ10 SA2 2
D4 C4
IRQE IRQ11 SA2 1
D5 C5
IRQ12 SA2 0
D6 C6
IRQ15 SA1 9
D7 C7
IRQ14 SA1 8
D8 C8
- DACK0 SA1 7
D9 C9
D R QA D R E Q0 - ME MR
D1 0 C1 0
- DACK5 - ME MW
D1 1 C1 1
D R QD D R E Q5 SD8
D1 2 C1 2
- DACK6 SD9
D1 3 C1 3
D R E Q6 SD1 0
D1 4 C1 4
- DACK7 SD1 1
D1 5 C1 5
D R E Q7 SD1 2
D1 6 C1 6
+5V SD1 3
D1 7 C1 7
- MA S T E R SD1 4
D1 8 C1 8
GN D SD1 5
AT3 6
C5 4
10
ES1879 DATA SHEET
APPENDIX D: SCHEMATIC EXAMPLES

ESS Technology, Inc.


ESS Technology, Inc.
ES1879 DATA SHEET

/
9
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5 

APPENDIX D: SCHEMATIC EXAMPLES

5  5  & 
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3 & 6 3 .2
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5  &  5      PP 6 7 ( 5 ( 2 - $ & .
  
$ 287 /
5  &  
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5  5 
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PRELIMINARY

5 

Figure 35 Amplifier Section


.

5  & 

.  

-
&  

&   / , 1( 287

   PP 6 7 ( 5 ( 2 - $ & .

SAM0025A-062397
107
PRELIMINARY ES1879 DATA SHEET
APPENDIX D: SCHEMATIC EXAMPLES

VCC D2

S1
J 7 1 N4 1 4 8 S W P U S H B U T T ON
D3
XA0 1 2
XA1 3 4
XA2 5 6 S W P U S H B U T T ON
1 N4 1 4 8 S2
XA3 7 8
XSC 9 1 0 V OL U P 1 8 7 8
XSD 1 1 1 2
D OC K E D 1 3 1 4
1 5 1 6 V OL D N 1 8 7 8
- 12V 1 7 1 8
S3
+12V 1 9 2 0
S W P U S H B U T T ON
HEADER 1 0 X2

J 6
IDATA 1 2
ISCLK 3 4
I L R 5 6
I2S_INTF_CONN

VCC
J 5
1 2 MC L K
R2 2
3 4 MS O U T
10K
5 6 R4 2
7 8 MSIC
9 1 0 0 ohm
1 1 1 2 MS D
1 3 1 4
1 5 1 6
+12V
1 7 1 8
J 8
1 9 2 0 AUXBL
- 12V
2 1 2 2 DX 1 2
2 3 2 4 AUXBR DR 3 4
2 5 2 6 DCL K 5 6
FS 7 8
13x 2 HEADER RST B
DSP_INTF_CONN

Figure 36 Switch and Connector Section

108 SAM0025A-062397 ESS Technology, Inc.


ES1879 DATA SHEET PRELIMINARY
APPENDIX E: LAYOUT GUIDELINES

APPENDIX E: LAYOUT GUIDELINES


PCB Layout A grouped on one side of the PCB.
Notebook, Motherboard, Pen-based, and PDA portable B separated on both sides of the PCB.
computers have the following similarity in PCB layout
design: In Case B, audio component grouping will take less space.

6. Multi-layer (usually 4 to 8 layer). Analog Ground Plane


7. Double-sided SMT. Audio circuits require two layers of analog ground planes
8. CPU, corelogic (chip set), system memory, VGA for use as shielding for all analog traces.
controller, and video memory reside in the same
PCB. In component placement case A (Figure 37), the first layer
of analog ground plane is on the analog component side,
This is a very noisy environment for adding an audio the second analog ground plane is on the inner layer, and
circuit. The following are the guidelines for PCB layout for the analog traces are embedded between these two
ESS AudioDrive® chip application. planes.

Component Placement In component placement case B (Figure 38), the analog


ground planes are on both sides of the PCB, with the
The audio circuit-related components must be grouped in analog traces shielded in the middle.
the same area. The audio I/O jack and connector are
considered audio-related components as well. There are
two possible placements for these audio components:

Case A:

Components
Analog ground plane on analog component side

Inner one or two layer(s) for analog traces

Inner layer analog ground plane

Other layer(s) for digital traces

Figure 37 Analog Components on One Side of the PCB


Case B:

Components
Analog ground plane on component side

Inner layer(s) for analog traces

Analog ground plane on component side


Components

Figure 38 Analog Components on Both Sides of the PCB.

Special Notes The MIC-IN circuit is the most sensitive of the audio
The analog traces should be places as short as possible. circuits, and requires proper and complete shielding.

ESS Technology, Inc. SAM0025A-062397 109


PRELIMINARY ES1879 DATA SHEET
APPENDIX F: ES1879 BILL OF MATERIALS

APPENDIX F: ES1879 BILL OF MATERIALS

Table 36 ES1879 Bill of Materials (BOM)


Item Quantity Reference Part
1 2 C1, C2 22 pF
2 15 C3, C4, C5, C6, C7, C8, C12, C14, C40, C41, C44, C45, C50, C53, 0.1 µF
C55
3 10 C9, C10, C11, C15, C17, C18, C19, C21, C47, C48 0.22 µF
4 2 C13, C43 47 µF
5 1 C16 0.047 µF
6 10 C20, C26, C27, C28, C29, C30, C31, C32, C38, C39 0.01 µF
7 7 C22, C23, C36, C37, C51, C52, C54 10 µF
8 2 C24, C25 0.001 µF
9 1 C33 150 pF
10 2 C34, C35 470 µF
11 1 C42 100 µF
12 1 C56 0.01 µF
13 1 C57 0.1 µF
14 3 D1, D2, D3 1N4148
15 1 J1 2X1 HEADER
16 1 J2 MITSUMI
17 4 J3, J4, J9, J10 3.5mm STEREO JACK
18 1 J5 13x2 HEADER
19 1 J6 4X2 HEADER I2S_INTF_CONN
20 1 J7 HEADER 10X2
21 1 J8 4X2 HEADER DSP_INTF_CONN
22 2 L1, L2 FERRITE BEAD
23 1 P1 CONNECTOR DB15
24 1 Q1 NPN
25 1 R37 470 ohm
26 7 R1, R18, R19, R21, R22, R33, R41 10K
27 2 R2, R3 7.5K
28 10 R4, R5, R6, R7, R8, R9, R10, R11, R12, R13 2.2K
29 4 R14, R15, R16, R17 1M
30 1 R36, R42 0 ohm
31 2 R23, R40 33K
32 4 R24, R25, R26, R27 820K
33 2 R28, R29 2.7 ohm
34 3 R30, R31, R32 100K
35 2 R34, R35 1K
36 2 R38, R39 220K
37 3 S1, S2, S3 SW PUSHBUTTON
38 1 U1 ES1879
39 1 U2 74LS138

110 SAM0025A-062397 ESS Technology, Inc.


ES1879 DATA SHEET PRELIMINARY
APPENDIX F: ES1879 BILL OF MATERIALS

Table 36 ES1879 Bill of Materials (BOM)


Item Quantity Reference Part
40 1 U3 78L05
41 1 U5 93LC66
42 1 U7 LM1877
43 1 Y1 14.318 MHz
44 1 JP1 (H = Internal ROM) (L = External EEPROM) 0 ohm Resistor

ESS Technology, Inc. SAM0025A-062397 111


PRELIMINARY ES1879 DATA SHEET
APPENDIX F: ES1879 BILL OF MATERIALS

No part of this publication may be reproduced, stored in a (P) U.S. Patent 4,214,125 and others, other patents
retrieval system, transmitted, or translated in any form or pending.
by any means, electronic, mechanical, manual, optical, or
AudioDrive® and ESPCM® are registered trademarks of ESS
otherwise, without the prior written permission of ESS
Technology, Inc.
Technology, Inc.
ESFM™ is a trademark of ESS Technology, Inc.
ESS Technology, Inc. makes no representations or
warranties regarding the content of this document. All other trademarks are owned by their respective
holders and are used for identification purposes only.
All specifications are subject to change without prior
notice.
ESS Technology, Inc. assumes no responsibility for any
errors contained herein.

112 © 1997 ESS Technology, Inc. All rights reserved. SAM0025A-062397

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