Verilog HDL 18EC56

Module 1
Overview of Digital Design
with Verilog HDL
Dinesh M.A.
[email protected]
•
/dinesh.ajay
/prof.dineshma
 VISION OF THE DEPARTMENT

• To be recognized by the society at large as

offering Value based Quality Education to
groom the next generation entrepreneurs,
leaders and researchers in the field of
Electronics and Communication to meet the
challenges at global level.

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 MISSION OF THE DEPARTMENT

• To groom the students with strong foundations of Electronics and

Communication Engineering and to facilitate them to pursue higher education
and research.
• To educate and prepare the students to be competent to face the challenges of
the industry/society and /or to become successful entrepreneurs.
• To provide ethical and value-based education by promoting activities addressing
the societal needs.
• Enable students to develop skills to solve complex technological problems of
current times and also provide a framework for promoting collaborative and
multidisciplinary activities.

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 Program Educational Objectives (PEOs)

• Be able to have a successful career in dynamic industry that

is global, multidisciplinary, and evolving.
• Solve problems, design and innovate while they work
individually or in teams with sense of professional ethics
and social responsibility.
• Communicate effectively and manage resources skillfully as
members and leaders of the profession

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 Program Specific Outcomes (PSOs)

• An ability to apply the basic concepts of engineering

science into various areas of Electronics Communication
Engineering.
• An ability to solve complex Electronics and
Communication Engineering problems, using state of the
art hardware and software tools, along with analytical skills
to arrive at cost effective and efficient solutions.

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 CO’s DESCRIPTION OF THE OUTCOMES

Present the comprehension of the IC Design flow, syntax, lexical

18EC56.1 conventions, data types, system tasks compiler directives and logic
synthesis in Verilog HDL.
Develop Verilog modules for digital circuits using gate level and data
18EC56.2 flow modeling, behavioral modeling using different control structures
and related statements and for system tasks as well.
Analyze the behavior of structural, dataflow and behavior modeling
18EC56.3
procedures written in Verilog.
Design digital functional blocks for a given set of specifications using
18EC56.4
hierarchical modeling concepts in Verilog.

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 RBT
Module – 1
Level

Overview of Digital Design with Verilog HDL:

Evolution of CAD, emergence of HDLs,
typical HDL-flow, why Verilog HDL?, trends in HDLs.
L1, L2,
L3
Hierarchical Modeling Concepts: Top-down and
bottom-up design methodology, differences
between modules and module instances, parts of a
simulation, design block, stimulus block.

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 Evolution of CAD (Computer Aided Digital Design)
• Digital circuits were designed with
• Vacuum tubes
• Transistors
• Integrated circuits (ICs)
• SSI
• MSI : hundreds of gates
• LSI : thousands of gates
• CAD techniques began to evolve
• circuit and Logic simulation about 100 transistors
• VLSI : more than 100,000 transistors
• ULSI : Ultra Large Scale Integration
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 Overview of Digital Design with Verilog HDL

• Evolution of computer aided digital circuit design

• Emergence of HDLs
• Typical design flow
• Importance of HDLs
• Popularity of Verilog HDL
• Trends in HDLs

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 Emergence of HDLs
• Hardware Description Language (HDL)
• Allowed designers to model the concurrency of processes found in hardware elements
• Verilog HDL originated in 1983 at Gateway Design Automation
• VHDL was developed under contract from DARPA
• Though HDLs were popular for logic verification, designers had to manually translate the
HDL-based design into a schematic circuit with interconnections between gates.
• Could be used to describe digital circuits at a register transfer level (RTL)
• Specify how the data flows between registers and how the design processes the data
• Logic synthesis tools can be used to produce gate-level netlist from the RTL description
automatically

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 An Example of Verilog HDL

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 Overview of Digital Design with Verilog HDL

• Evolution of computer aided digital circuit design

• Emergence of HDLs
• Typical design flow
• Importance of HDLs
• Popularity of Verilog HDL
• Trends in HDLs

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 Typical Design Flow
Design
Logical Verification
Specification
and Testing

Behavioral
Description Floor Planning Automatic
Place & Route

RTL Description
(HDL)
Physical Layout

Functional Verification
and Testing
Layout Verification

Logic Synthesis
Implementation

Gate-level Netlist
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 Overview of Digital Design with Verilog HDL

• Evolution of computer aided digital circuit design

• Emergence of HDLs
• Typical design flow
• Importance of HDLs
• Popularity of Verilog HDL
• Trends in HDLs

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 Why use the HDL ?

• Difficult to design directly on hardware

• Mixed-level modeling and simulation
• Easier to explore different design options
• Reduce design time and cost

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 Advantages of HDLs
• Advantages compared to traditional schematic-based design
• Design with RTL description + logic synthesis tool
• Abstract level
• Independent to fabrication technology
• Reuse when fabrication technology changing
• Functional verification can be done early
• Optimized to meet the desired functionality
• Analogous to computer programming
• Textual description with comments

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 Overview of Digital Design with Verilog HDL

• Evolution of computer aided digital circuit design

• Emergence of HDLs
• Typical design flow
• Importance of HDLs
• Popularity of Verilog HDL
• Trends in HDLs

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 History of the Verilog HDL

• 1984: Gateway Design Automation introduced the Verilog-XL digital

logic simulator
• The Verilog language was part of the Verilog-XL simulator
• The language was mostly created by 1 person, Phil Moorby
• The language was intended to be used with only 1 product
• 1989: Gateway merged into Cadence Design Systems
• 1990: Cadence made the Verilog HDL public domain
• Open Verilog International (OVI) controlled the language

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 History of the Verilog HDL (Cont’d)

• 1995: The IEEE standardized the Verilog HDL (IEEE 1364)

• 2001: The IEEE enhanced the Verilog HDL for modeling scalable designs,
deep sub-micron accuracy, etc.

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 Useful Features of the Verilog HDL
• A general-purpose HDL
• Easy to learn and use
• Syntax is similar to C (VHDL is similar to PASCAL)
• Allows different levels of abstraction to be mixed in the same model
• In terms of switches, gates, RTL, or behavioral code
• Need to learn only for stimulus and hierarchical design
• Most popular logic synthesis tools support Verilog
• Rich of Verilog HDL libraries
• Provided by fabrication vendors for postlogic synthesis simulation
• Allows the widest choice of vendors while designing a chip
• With powerful PLI (Programming Language Interface)
• Write custom C code to interact with internal data structure

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 Overview of Digital Design with Verilog HDL

• Evolution of computer aided digital circuit design

• Emergence of HDLs
• Typical design flow
• Importance of HDLs
• Popularity of Verilog HDL
• Trends in HDLs

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 Trends in HDLs
• Higher levels of abstraction
• Think only in terms of functionality for designers
• CAD tools take care of the implementation details
• Behavioral modeling
• Design directly in terms of algorithms and
• the behavior of the circuit
• Formal verification
• Supports for Mixed-level design
• Ex: very high speed and timing-critical circuits like μPs
• Mix gate-level description directly into the RTL description
• System-level design in a mixed bottom-up methodology
• Use either existing Verilog modules, basic building blocks, or IPs
• Ex: SystemC for SoC designs

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 Chapter 2
Hierarchical Modeling Concepts

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Design Methodologies

• There are two basic types of digital design

methodologies:
• a top-down design methodology
• a bottom-up design methodology

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 Top-down Design Methodology
• In a top-down design methodology, we define the top-level
block and identify the sub-blocks necessary to build the top-
level block. We further subdivide the sub-blocks until we come
to leaf cells, which are the cells that cannot further be divided

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 Bottom-up Design Methodology
• In a bottom-up design methodology, we first identify the building
blocks that are available to us. We build bigger cells, using these
building blocks. These cells are then used for higher-level blocks
until we build the top-level block in the design

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combination of top-down and bottom-up

• Typically, a combination of top-down and bottom-up flows is used.

• Design architects define the specifications of the top-level block
• Logic designers decide how the design should be structured by breaking
up the functionality into blocks and sub-blocks
• Circuit designers are designing optimized circuits for leaf-level cells
• They build higher-level cells by using these leaf cells. The flow meets at an
intermediate point where the switch-level circuit designers have created a
library of leaf cells by using switches, and the logic level designers have
designed from top-down until all modules are defined in terms of leaf
cells
• To illustrate these hierarchical modeling concepts, let us consider
the design of a negative edge-triggered 4-bit ripple carry counter.
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4-bit Ripple Carry Counter
• The ripple carry counter shown is made up of negative edge-triggered toggle flipflops
(T_FF).
• Each of the T_FFs can be made up from negative edge-triggered D-flipflops (D_FF) and
inverters (assuming q_bar output is not available on the D_FF)

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The diagram for the design hierarchy

• In a top-down design methodology,

• we first have to specify the functionality of the ripple carry counter, which is the top-level block.
• Then, we implement the counter with T_FFs. We build the T_FFs from the D_FF and an additional inverter gate.
• Thus, we break bigger blocks into smaller building sub-blocks until we decide that we cannot break up the blocks
any further.
• A bottom-up methodology flows in the opposite direction.
• We combine small building blocks and build bigger blocks;
• e.g., we could build D_FF from ‘and’ and ‘or’ gates, or we could build a custom D_FF from transistors.
• Thus, the bottom-up flow meets the top-down flow at the level of the D_FF.
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Modules

• A module is the basic building block in Verilog.

• A module can be an element or a collection of lower-level design
blocks.
• Typically, elements are grouped into modules to provide common
functionality that is used at many places in the design.
• A module provides the necessary functionality to the higher-level
block through its port interface (inputs and outputs), but hides the
internal implementation. This allows the designer to modify module
internals without affecting the rest of the design.

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• In Verilog, a module is declared by the keyword module. A corresponding keyword endmodule must
appear at the end of the module definition.
• Each module must have a module_name, which is the identifier for the module, and a
module_terminal_list, which describes the input and output terminals of the module.

module <module_name> (<module_terminal_list>);

...
<module internals>
...
endmodule

• Specifically, the T-flipflop could be defined as a module as follows:

module T_FF (q, clock, reset);

...
<functionality of T-flipflop>
...
endmodule

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Levels of abstraction

• Verilog is both a behavioral and a structural

language.
• Internals of each module can be defined at four
levels of abstraction, depending on the needs of
the design.
• The module behaves identically with the external
environment irrespective of the level of
abstraction at which the module is described.
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Four levels of abstraction
• Behavioral or algorithmic level
• Dataflow level
• Gate level
• Switch level

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 Four levels of abstraction
Behavioral or algorithmic level
This is the highest level of
abstraction provided by
Verilog HDL. A module can
be implemented in terms of the
desired design algorithm without
concern for the hardware
implementation details. Designing
at this level is very similar to C
programming.
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 Four levels of abstraction
Dataflow-level
At this level, the module
is designed by specifying the
data flow. The designer is
aware of how data flows
between hardware
registers and how the
data is processed in the
design.

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Four levels of abstraction
Gate-level
The module is
implemented in terms of logic
gates and interconnections
between these gates. Design at
this level is similar to
describing a design in
terms of a gate-level logic
diagram.
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 Four levels of abstraction
Switch-level
This is the lowest level of
abstraction provided by
Verilog. A module can be
implemented in terms of switches,
storage nodes, and the
interconnections between them.
Design at this level requires
knowledge of switch-level
implementation details.
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 levels of abstraction (why)
• Normally, the higher the level of
• Verilog allows the designer to mix abstraction, the more flexible and
and match all four levels of technology-independent the design.
abstractions in a design
• As one goes lower toward switch-level
• In the digital design community, the design, the design becomes technology-
term register transfer level (RTL) is dependent and inflexible.
frequently used for a Verilog
description that uses a combination
• A small modification can cause a significant
number of changes in the design.
of behavioral and dataflow
constructs and is acceptable to logic • Consider the analogy with C programming
synthesis tools. and assembly language programming. It is
easier to program in a higher-level language
• If a design contains four modules,
such as C. The program can be easily ported
Verilog allows each of the modules
to any machine. However, if you design at
to be written at a different level of
the assembly level, the program is specific
abstraction.
for that machine and cannot be easily
ported to another machine.
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Instances
• A module provides a template from which you can create actual objects.

• When a module is invoked, Verilog creates a unique object from the template.

• Each object has its own name, variables, parameters, and I/O interface.

• The process of creating objects from a module template is called instantiation, and the objects
are called instances.

• In Example 2-1, the top-level block creates four instances from the T-flipflop (T_FF) template.
Each T_FF instantiates a D_FF and an inverter gate. Each instance must be given a unique
name.

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Example 2-1 Module Instantiation
module ripple_carry_counter(q, clk, reset);
output [3:0] q; //I/O signals and vector declarations
input clk, reset; //I/O signals will be explained later.
T_FF tff0(q[0],clk, reset);
T_FF tff1(q[1],q[0], reset);
T_FF tff2(q[2],q[1], reset);
T_FF tff3(q[3],q[2], reset);
endmodule

module T_FF(q, clk, reset);

output q;
input clk, reset;
wire d;
D_FF dff0(q, d, clk, reset); // Instantiate D_FF. Call it dff0.
not n1(d, q); // not gate is a Verilog primitive. Explained later.
endmodule

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 Example 2-2 Illegal Module Nesting
In Verilog, it is illegal to nest modules. One module definition cannot contain another module
definition within the module and endmodule statements.
Instead, a module definition can incorporate copies of other modules by instantiating them.
It is important not to confuse module definitions and instances of a module. Module definitions
simply specify how the module will work, its internals, and its interface. Modules must be
instantiated for use in the design.

Example 2-2 Illegal Module Nesting

module ripple_carry_counter(q, clk, reset);
output [3:0] q;
input clk, reset;
module T_FF(q, clock, reset); //Illegal Module Nesting
...
<module T_FF internals>
...
endmodule // End Of Illegal Module Nesting
endmodule
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 2.5 Components of a Simulation

• Once a design block is completed, it must be tested.

• The functionality of the design block can be tested by applying
stimulus and checking results. We call such a block the stimulus block.
• It is good practice to keep the stimulus and design blocks separate.
• The stimulus block can be written in Verilog. A separate language is
not required to describe stimulus.
• The stimulus block is also commonly called a test bench.
• Different test benches can be used to thoroughly test the design
block.

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 Two styles of stimulus application

• In the first style, the stimulus block instantiates the design block and
directly drives the signals in the design block.
• The stimulus block becomes the top-level block. It manipulates
signals clk and reset, and it checks and displays output signal q.

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 Two styles of stimulus application
• The second style of applying stimulus is to instantiate both the stimulus and
design blocks in a top-level dummy module. The stimulus block interacts
with the design block only through the interface.
• The stimulus module drives the signals d_clk and d_reset, which are connected
to the signals clk and reset in the design block. It also checks and displays signal
c_q, which is connected to the signal q in the design block. The function of
top-level block is simply to instantiate the design and stimulus blocks.

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2.6 Example
• Design Block
• We use a top-down design methodology.
First, we write the Verilog description of the top-level design block, which
is the ripple carry counter.
module ripple_carry_counter(q, clk, reset);
output [3:0] q;
input clk, reset;
//4 instances of the module T_FF are created.
T_FF tff0(q[0],clk, reset);
T_FF tff1(q[1],q[0], reset);
T_FF tff2(q[2],q[1], reset);
T_FF tff3(q[3],q[2], reset);
endmodule
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• In the above module, four instances of the module T_FF (T-
flipflop) are used.
• Therefore, we must now define the internals of the module
T_FF
module T_FF(q, clk, reset);
output q;
input clk, reset;
wire d;
D_FF dff0(q, d, clk, reset);
not n1(d, q); // not is a Verilog-provided primitive. case sensitive

endmodule

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 • Since T_FF instantiates D_FF, we must now define the internals of
module D_FF. We assume asynchronous reset for the D_FFF.

module D_FF(q, d, clk, reset);

output q;
input d, clk, reset;
reg q;
// Lots of new constructs. Ignore the functionality of the constructs.
// Concentrate on how the design block is built in a top-down fashion.
always @(posedge reset or negedge clk)
if (reset)
q <= 1'b0;
else
q <= d;
Endmodule

• All modules have been defined down to the lowest-level leaf cells in the
design methodology. The design block is now complete.
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• Stimulus Block
• We must now write the stimulus block to check if the ripple carry counter design is
functioning correctly.
• In this case, we must control the signals clk and reset so that the regular function of
the ripple carry counter and the asynchronous reset mechanism are both tested.
• We use the waveforms shown below to test the design. Waveforms for clk, reset,
and 4-bit output q are shown.
• The cycle time for clk is 10 units; the reset signal stays up from time 0 to 15
and then goes up again from time 195 to 205. Output q counts from 0 to 15.

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module stimulus; // Control the reset signal that drives the design block
reg clk; // reset is asserted from 0 to 20 and from 200 to 220.
reg reset; initial
wire[3:0] q; begin
ripple_carry_counter r1(q, clk, reset); // reset = 1'b1;
instantiate the design block #15 reset = 1'b0;
#180 reset = 1'b1;
// Control the clk signal that drives the design #10 reset = 1'b0;
block. Cycle time = 10
#20 $finish; //terminate the simulation
initial
end
clk = 1'b0; //set clk to 0
// Monitor the outputs
always
initial
#5 clk = ~clk; //toggle clk every 5 time
units $monitor($time, " Output q = %d", q);
endmodule

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• Once the stimulus block is completed, we are ready to run the simulation and verify the
functional correctness of the design block.
• The output obtained when stimulus and design blocks are simulated is shown

0 Output q = 0 120 Output q = 11

20 Output q = 1 130 Output q = 12
30 Output q = 2 140 Output q = 13
40 Output q = 3 150 Output q = 14
50 Output q = 4 160 Output q = 15
60 Output q = 5 170 Output q = 0
70 Output q = 6 180 Output q = 1
80 Output q = 7 190 Output q = 2
90 Output q = 8 195 Output q = 0
100 Output q = 9 210 Output q = 1
110 Output q = 10 220 Output q = 2

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Summary
• In this chapter we discussed the following concepts.
• Two kinds of design methodologies are used for digital design: top-down and bottom-up. A
combination of these two methodologies is used in today's digital designs. As designs
become very complex, it is important to follow these structured approaches to manage the
design process.
• Modules are the basic building blocks in Verilog. Modules are used in a design by
instantiation. An instance of a module has a unique identity and is different from other
instances of the same module. Each instance has an independent copy of the internals of
the module. It is important to understand the difference between modules and instances.
• There are two distinct components in a simulation: a design block and a stimulus block. A
stimulus block is used to test the design block. The stimulus block is usually the top-level
block. There are two different styles of applying stimulus to a design block.
• The example of the ripple carry counter explains the step-by-step process of building all the
blocks required in a simulation.

• This chapter is intended to give an understanding of the design process and how
Verilog fits into the design process. The details of Verilog syntax are not important at
this stage and will be dealt with in later chapters.

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 Text

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