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Educational Practice Board C5515 Workbook

Chapter 2
Introduction to TMS320C5515

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Introduction to TMS320C5515:

The device is a member of TI's TMS320C5000™ fixed-point Digital Signal Processor (DSP) product
family and is designed for low-power applications.

The fixed-point DSP is based on the TMS320C55x™ DSP generation CPU processor core. The C55x™
DSP architecture achieves high performance and low power through increased parallelism and total
focus on power savings. The CPU supports an internal bus structure that is composed of one
program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses,
and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to
perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also
includes four DMA controllers, each with 4 channels, providing data movement for 16-independent
channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data
transfer per cycle, in parallel and independent of the CPU activity.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit
multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is
supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the
ability to optimize parallel activity and power consumption. These resources are managed in the
Address Unit (AU) and Data Unit (DU) of the C55x CPU.
The C55x CPU supports a variable byte width instruction set for improved code density. The
Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues
instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to
the Address Unit (AU) and Data Unit (DU) resources, and manages the fully protected pipeline.
Predictive branching capability avoids pipeline flushes on execution of conditional instructions.

The general-purpose input and output functions along with the 10-bit SAR ADC provide sufficient
pins for status, interrupts, and bit I/O for LCD displays, keyboards, and media interfaces. Serial
media is supported through two MultiMedia Card/Secure Digital (MMC/SD) peripherals, four Inter-IC
Sound (I2S Bus™) modules, one Serial-Port Interface (SPI) with up to 4 chip selects, one I2C multi-
master and slave interface, and a Universal Asynchronous Receiver/Transmitter (UART) interface.

The device peripheral set includes an external memory interface (EMIF) that provides glueless
access to asynchronous memories like EPROM, NOR, NAND, and SRAM, as well as to high-speed,
high-density memories such as synchronous DRAM (SDRAM) and mobile SDRAM (mSDRAM).
Additional peripherals include: a high-speed Universal Serial Bus (USB2.0) device mode only, and a
real-time clock (RTC). This device also includes three general-purpose timers with one configurable
as a watchdog timer, and an analog phase-locked loop (APLL) clock generator.

In addition, the device includes a tightly-coupled FFT Hardware Accelerator. The tightly-coupled FFT
Hardware Accelerator supports 8 to 1024-point (in power of 2) real and complex-valued FFTs.

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Furthermore, the device includes three integrated LDOs (DSP_LDO, ANA_LDO, and USB_LDO) to
power different sections of the device. The DSP_LDO can provide 1.3 V or 1.05 V to the DSP core
(CVDD), selectable on-the-fly by software as long as operating frequency ranges are observed. To
allow for lowest power operation, the programmer can shutdown the internal DSP_LDO cutting
power to the DSP core (CV DD) while an external supply provides power to the RTC (CV DDRTC and
DVDDRTC). The ANA_LDO is designed to provide 1.3 V to the DSP PLL (V DDA_PLL), SAR, and power
management circuits (VDDA_ANA). The USB_LDO provides 1.3 V to USB core digital (USB_V DD1P3) and
PHY circuits (USB_VDDA1P3). The RTC alarm interrupt or the WAKEUP pin can re-enable the internal
DSP_LDO and re-apply power to the DSP core.

The device is supported by the industry’s award-winning eXpressDSP™, Code Composer Studio™
Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments’ algorithm standard,
and the industry’s largest third-party network. Code Composer Studio IDE features code generation
tools including a C Compiler and Linker, RTDX™, XDS100™, XDS510™, XDS560™ emulation device
drivers, and evaluation modules. The device is also supported by the C55x DSP Library which
features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math
functions) as well as chip support libraries.

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Features:
 High-Performance, Low-Power, TMS320C55x™ Fixed-Point Digital Signal Processor
o 16.67-, 13.33-, 10-, 8.33-ns Instruction Cycle Time

o 60-, 75-, 100-, 120-MHz Clock Rate

o One/Two Instructions Executed per Cycle

o Dual Multipliers [Up to 200 or 240 Million Multiply-Accumulates per Second (MMACS)]

o Two Arithmetic/Logic Units (ALUs)

o Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses

o Software-Compatible With C55x Devices

o Industrial Temperature Devices Available

 320K Bytes Zero-Wait State On-Chip RAM, Composed of:

o 64K Bytes of Dual-Access RAM (DARAM), 8 Blocks of 4K x 16-Bit

o 256K Bytes of Single-Access RAM (SARAM), 32 Blocks of 4K x 16-Bit

 128K Bytes of Zero Wait-State On-Chip ROM

 4M x 16-Bit Maximum Addressable External Memory Space (SDRAM/mSDRAM)

 16-/8-Bit External Memory Interface (EMIF) with Glueless Interface to:

o 8-/16-Bit NAND Flash, 1- and 4-Bit ECC

o 8-/16-Bit NOR Flash

o Asynchronous Static RAM (SRAM)

o SDRAM/mSDRAM (1.8-, 2.5-, 2.75-, and 3.3-V)

 Direct Memory Access (DMA) Controller

o Four DMA With 4 Channels Each (16-Channels Total)

 Three 32-Bit General-Purpose Timers

o One Selectable as a Watchdog and/or GP

 Two MultiMedia Card/Secure Digital (MMC/SD) Interfaces

 Universal Asynchronous Receiver/Transmitter (UART)

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 Serial-Port Interface (SPI) With Four Chip-Selects

 Master/Slave Inter-Integrated Circuit (I2C Bus™)

 Four Inter-IC Sound (I2S Bus™) for Data Transport

 Device USB Port With Integrated 2.0 High-Speed PHY that Supports:

o USB 2.0 Full- and High-Speed Device

 LCD Bridge With Asynchronous Interface

 Tightly-Coupled FFT Hardware Accelerator

 10-Bit 4-Input Successive Approximation (SAR) ADC

 Real-Time Clock (RTC) With Crystal Input, With Separate Clock Domain and Power Supply

 Four Core Isolated Power Supply Domains: Analog, RTC, CPU and Peripherals, and USB

 Four I/O Isolated Power Supply Domains: RTC I/O, EMIF I/O, USB PHY, and DV DDIO

 Three integrated LDOs (DSP_LDO, ANA_LDO, and USB_LDO) to power the isolated domains: DSP
Core, Analog, and USB Core, respectively

 Low-Power S/W Programmable Phase-Locked Loop (PLL) Clock Generator

 On-Chip ROM Bootloader (RBL) to Boot From NAND Flash, NOR Flash, SPI EEPROM, SPI Serial
Flash or I2C EEPROM

 IEEE-1149.1 (JTAG)
Boundary-Scan-Compatible

 Up to 26 General-Purpose I/O (GPIO) Pins

 196-Terminal Pb-Free Plastic BGA (Ball Grid Array) (ZCH Suffix)

 1.05-V Core (60 or 75 MHz), 1.8-V, 2.5-V, 2.75-V, or 3.3-V I/Os

 1.3-V Core (100, 120 MHz), 1.8-V, 2.5-V, 2.75-V, or 3.3-V I/Os

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TMS320C5515 DSP Block Diagram:

Device Compatibility
The C55xx DSP core is code-compatible with the C5000™ DSP platform

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DSP TMS320C5515 Functional Block Diagram:

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DSP TMS320C5515 Memory Map

The device provides 16M bytes of total memory space composed of on-chip RAM, on-chip ROM,
and external memory space supporting a variety of memory types. The on-chip, dual-access
RAM allows two accesses to a given block during the same cycle. There are 8 blocks of 8K bytes
of dual-access RAM. The on-chip, single-access RAM allows one access to a given block per
cycle. In addition, there are 32 blocks of 8K bytes of single-access RAM.

The remainder of the memory map is divided into five external spaces, and on-chip ROM. Each
external space has a chip select decode signal (called EM_CS0, EM_CS[2:5]) that indicates an
access to the selected space. The external memory interface (EMIF) supports access to
asynchronous memories such as SRAM, NAND, or NOR and Flash, and mobile single data rate
(mSDR) and single data rate (SDR) SDRAM.

The DSP memory is accessible by different master modules within the DSP, including the C55x
CPU, the four DMA controllers, LCD, and the CDMA of USB (See below figure)

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C55xx DSP Family Overview/Comparison:

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Device Nomenclature:

To designate the stages in the product development cycle, TI assigns prefixes to the part
numbers of all DSP devices and support tools. Each DSP commercial family member has one of
three prefixes: TMX, TMP, or TMS (e.g.,TMS320C5515AZCHA12). Texas Instruments
recommends two of three possible prefix designators for its support tools: TMDX and TMDS.
These prefixes represent evolutionary stages of product development from engineering
prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).

Device development evolutionary flow:

TMX Experimental device that is not necessarily representative of the final device's electrical
specifications.

TMP Final silicon die that conforms to the device's electrical specifications but has not
completed
quality and reliability verification.

TMS Fully-qualified production device.

Support tool development evolutionary flow:

TMDX Development-support product that has not yet completed Texas Instruments internal
qualification testing.

TMDS Fully qualified development-support product.

TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:

"Developmental product is intended for internal evaluation purposes."

TMS devices and TMDS development-support tools have been characterized fully, and the
quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the
standard production devices. Texas Instruments recommends that these devices not be used in
any production system because their expected end-use failure rate still is undefined. Only
qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates
the package type (for example, ZCH), and the temperature range (for example, "Blank" is the
commercial temperature range).

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