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UNIT II

8085 MICRO PROCESSOR

8085 Architecture:
The architecture of 8085 consists of various components like:

1. Accumulator & Register sets.

2. Program counter and stack pointer.
3. Flag Register.
4. ALU.
5. Instruction decoder and machine cycle encoder.
6. Address buffer.
7. Address/data buffer.
8. Increment/Decrement latch.
9. Interrupt control.
10. Serial I/O like SOD,SID.
11. Timing and Control circuit.

8085 Architecture

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Accumulator:

• The accumulator is an 8-bit register then is part of the arithmetic/logic unit(ALU).

• This register is used to store to store 8-bit data this data is used to perform arithmetic &
logical operation.
• The result of an operation is stored in the accumulator.
• The accumulator is also identified as register A.
• The accumulator is used for data transfer between an I/O port and memory location.

Register sets:
• The 8085 simulator has six general-purpose registers to store 8-bit data; these are identified as
B, C, D, E, H and L. They can be combined as register pair likeBC, DE and HL – to perform
some 16-bit operations.
• The programmer can use these registers to store or copy data into the registers by using data
copy instructions.
• Out of these six registers, four 8-bit registers are scratch pad registers which are accessible to
the programmer and hence can be used to temporarily store data during a program execution.
• And the two registers H and L are utilized in indirect addressing mode. In this mode, the
memory location i.e. the address is specified by the contents of the registers.

Program Counter (PC):

• It is a 16 bit register which holds the memory address of the next instruction to be executed in
the next step.
• This 16-bit register deals with sequencing the execution of instructions. This register is a
memory pointer. Memory locations have 16-bit addresses, and that is why this is a 16-bit
register.
• The microprocessor uses this register to sequence the execution of the instructions. The
function of the program counter is to point to the memory address from which the next
instruction is to be fetched. When a byte (machine code) is being fetched, the program
counter is incremented by one to point to the next memory location.

Stack Pointer (SP):

• Stack pointer is used during subroutine calling and execution.

• The stack pointer is also a 16-bit register used as a memory pointer. It points to a memory
location in R/W memory, called the stack.

Flag or status register:

• The ALU includes five flip-flops, which are set or reset after an operation according to data
conditions of the result in the accumulator and other registers. They are called Zero(Z), Carry
(CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags.
• The most commonly used flags are Zero, Carry, and Sign. The microprocessor uses these
flags to test data conditions.
• For example, after an addition of two numbers, if the sum in the accumulator is larger than
eight bits, the flip-flop uses to indicate a carry -- called the Carry flag (CY) -- is set to one.
• When an arithmetic operation results is zero, the flip-flop called the Zero(Z) flag is set to one.

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• Flag is an 8-bit register containing 5no.s of 1-bit flags:

1. Sign - If the result of the latest arithmetic operation is having MSB
(most- significant bit) 1 (meaning it is a negative number), then the sign
flag is set. Otherwise, it is reset to 0 which means it is a positive
number.
2. Zero - If the result of the latest operation is zero, then zero flag will be set; otherwise
it be reset.
3. Auxiliary carry - set if there was a carry out from bit 3 to bit 4 of the result.
4. Parity - set if the parity (the number of set bits in the result) is even. i.e.,
If the result of the latest operation is having even number of „1s, then
this flag will be set. Otherwise this will be reset to „0‟. This is used for
error checking.
5. Carry - set if there was a carry during addition, or borrow during
subtraction/comparison. Otherwise it will be reset.

Instruction register or Decoder:-

• Instruction register holds the instruction that is currently being processed.

• Once the instruction is fetch from the memory, it is reloaded in the instruction register for
some time, after the decoder decode the instruction performing some event or task.

Address buffer:
• The remaining higher order address lines form the address buffer ranging from [A8 -
A15].This is having the unidirectional buffer.

Address/data buffer:
• The address bus will be having 16 address lines [A15 - A0] .In which A7-A0 are called as
lower addressing lines and these are multiplexed with data lines [D7 - D0] to form
multiplexed address /data buffer .The address/data buffer is the bidirectional bus.

Increment/Decrement Address Latch:

• It increments/ decrements the address before sent to the address buffer

Interrupts:

The processor has 5 interrupts. They are presented below in the order of theirpriority (from lowest
to highest):

• INTR is maskable 8080A compatible interrupt. When the interrupt occurs, the processor
fetches from the bus one instruction, usually one of these instructions: One of the 8 RST
instructions (RST0 - RST7). The processor saves current program counter into stack and
branches to memory location N * 8 (where N is a 3-bit number from 0 to 7 supplied with the
RST instruction).
• CALL instruction (3 byte instruction). The processor calls the subroutine, address of which is
specified in the second and third bytes of the instruction.

• RST5.5 is a maskable interrupt. When this interrupt is received the processor saves the
contents of the PC register into stack and branches to 2CH (hexadecimal) address.

• RST6.5 is a maskable interrupt. When this interrupt is received the processor saves the
contents of the PC register into stack and branches to 34H (hexadecimal) address.

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• RST7.5 is a maskable interrupt. When this interrupt is received the processor saves the
contents of the PC register into stack and branches to 3CH (hexadecimal) address.

• TRAP is a non-maskable interrupt. When this interrupt is received the processorsaves the
contents of the PC register into stack and branches to 24H (hexadecimal) address.

• All maskable interrupts can be enabled or disabled using EI and DI instructions. RST 5.5,
RST6.5 and RST7.5 interrupts can be enabled or disabled individually using SIM Instruction
Serial I/O control

 These are control signals used for controlling 8085. These are subdivided into two types.
1. SID (Serial Input Data) – This is used for transferring of data into memory serially.
2. SOD (Serial Output Data) - This is used for transferring of data from memory to external
devices
 Interrupt control is used to transfer the ISR to the CPU.

PIN DIAGRAM

Pin Diagram of 8085

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A8 - A15 (Output 3 State):

Address Bus: The most significant 8 bits of the memory address or the 8 bits of the I/0 address,3
stated during Hold and Halt modes.

AD0 - AD7 (Input / Output 3 state):

Multiplexed Address/Data Bus; Lower 8 bits of the memory address (or I/0 address) appear on the bus
during the first clock cycle of a machine state. It then becomes the data bus during the second and
third clock cycles. 3 stated during Hold and Halt modes.

ALE (Output):
 Address Latch Enable: It occurs during the first clock cycle of a machine state and enables the
address to get latched into the on chip latch of peripherals.
 The falling edge of ALE is set to guarantee setup and hold times for the address information.
ALE can also be used to strobe the status information. ALE is never 3stated.

SO, S1 (Output): Data Bus Status. Encoded status of the bus cycle:

S1 S0
0 0 HALT
0 1 WRITE
1 0 READ
1 1 FETCH S1 can be used as an advanced R/W status.

RD (Output 3state):

READ: indicates the selected memory or I/0 device is to be read and that the Data Bus is available for
the data transfer.

WR (Output 3state):
 WRITE: indicates the data on the Data Bus is to be written into the selected memory or
I/0location.

 Data is set up at the trailing edge of WR. 3stated during Hold and Halt modes. 

READY (Input):
 If Ready is high during a read or write cycle, it indicates that the memory or
peripheral is readyto send or receive data.
 If Ready is low, the CPU will wait for Ready to go high before completing the
read or write cycle.
HOLD (Input):

 HOLD: Indicates that another Master is requesting the use of the Address and
Data Buses.

 The CPU, upon receiving the Hold request will relinquish the use of buses as
soon as the completion of the current machine cycle. 

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 Internal processing can continue. The processor can regain the buses only after the Hold is
removed. When the Hold is acknowledged, the Address, Data, RD, WR, and IO/M lines are
3stated.

HLDA (Output):

 HOLD ACKNOWLEDGE: indicates that the CPU has received the Hold
request and that it willrelinquish the buses in the next clock cycle. 

 HLDA goes low after the Hold request is removed. The CPU takes the buses
one half clock cycle after HLDA goes low.

INTR (Input):

 INTERRUPT REQUEST is used as a general purpose interrupt. It is sampled only during the
next clock cycle of the instruction. If it is active, the Program Counter (PC) will be inhibited
from incrementing and an INTA will be issued.

 During this cycle a RESTART or CALL instruction can be inserted to jump to the interrupt
service routine. The INTR is enabled and disabled by software. It is disabled by Reset and
immediately after an interrupt is accepted. 

INTA (Output):

 INTERRUPT ACKNOWLEDGE: is used instead of (and has the same timing as) RD during
theInstruction cycle after an INTR is accepted. 
 It can be used to activate the 8259 Interrupt chip or some other interrupt port.

RESTART INTERRUPTS:

These three inputs have the same timing as INTR except they cause an internal RESTART to
be automatically inserted.
 RST 7.5 Highest Priority
 RST 6.5
 RST 5.5 Lowest Priority

TRAP (Input):

 Trap interrupt is a non maskable restart interrupt. It is recognized at the same time as
INTR. It is unaffected by any mask or Interrupt Enable. It has the highest priority of any
interrupt.

RESET IN (Input):
 Reset sets the Program Counter to zero and resets the Interrupt Enable and HLDA flip
flops.
 None of the other flags or registers (except the instruction register) are affected. The CPU
is held in the reset condition as long as Reset is applied.

RESET OUT (Output):

Indicates CPlJ is being reset. Can be used as a system RESET. The signal is synchronized to
the processor clock.

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X1, X2 (Input):

Crystal or R/C network connections to set the internal clock generator X1 can also be an
external clock input instead of a crystal. The input frequency is divided by 2 to give the
internal operating frequency.

CLK (Output):
Clock Output for use as a system clock when a crystal or R/ C network is used as an input to
the CPU. The period of CLK is twice the X1, X2 input period.

IO/M (Output):
IO/M indicates whether the Read/Write is to memory or l/O Tristated during Hold and Halt
modes.

SID (Input):
Serial input data line The data on this line is loaded into accumulator bit 7 whenever a RIM
instruction is executed.

SOD (output):
Serial output data line. The output SOD is set or reset as specified by the SIM instruction.

Vcc: +5 volt supply. Vss: Ground Reference.

MEMORY ORGANIZATION

Memory Interfacing

The memory is made up of semiconductor material used to store the programs and
data. Three types of memory is,

 Process memory
 Primary or main memory
 Secondary memory

Memory Interfacing

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Typical EPROM and Static RAM

A typical semiconductor memory IC will have n address pins, m data pins (or

output pins).

 Having two power supply pins (one for connecting required supply voltage V and the other
for connecting ground).
 The control signals needed for static RAM are chip select (chip enable), read control (output
enable) and write control (write enable).
 The control signals needed for read operation in EPROM are chip select (chip
enable) and read control (output enable).

Decoder

It is used to select the memory chip of processor during the execution of a program. No of
IC's used for decoder is,

2-4 decoder (74LS139)

3-8 decoder (74LS138)

Fig 2.5 Block Diagram of 2-4 Decoder

Table 2.1 Truth Table for 2-4 Decoder

Consider a system in which the full memory space 64kb is utilized for EPROM memory. Interface
the EPROM with 8085 processor.

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The memory capacity is 64 Kbytes. i.e 2^n = 64 x 1000 bytes where n = address lines.

So, n = 16. In this system the entire 16 address lines of the processor are connected to address input
pins of memory IC in order to address the internal locations of memory. The chip select (CS) pin of
EPROM is permanently tied to logic low (i.e., tied to ground).

Since the processor is connected to EPROM, the active low RD pin is connected to active
low output enable pin of EPROM. The range of address for EPROM is 0000H to FFFFH.

TIMING DIAGRAM
Timing Diagram is a graphical representation. It represents the execution time taken by each
instruction in a graphical format. The execution time is represented in T-states.

Instruction Cycle -The time required to execute an instruction is called instruction cycle.

Machine Cycle - The time required to access the memory or input/output devices is called machine
cycle.

T-State-The machine cycle and instruction cycle takes multiple clock periods. A portion of an
operation carried out in one system clock period is called as T-state.

Machine cycles of 8085

The 8085 microprocessor has 5 (seven) basic machine cycles. They are

1. Opcode fetch cycle (4T)

2. Memory read cycle (3 T)
3. Memory write cycle (3 T)
4. I/O read cycle (3 T)
5. I/O write cycle (3 T)

Clock Signal

1. Opcode fetch machine cycle of 8085

Each instruction of the processor has one byte opcode. The opcodes are stored in memory. So,
the processor executes the opcode fetch machine cycle to fetch the opcode from memory. Hence,
every instruction starts with opcode fetch machine cycle. The time taken by the processor to
execute the opcode fetch cycle is 4T.

In this time, the first, 3 T-states are used for fetching the opcode from memory and the
remaining T-states are used for internal operations by the processor.

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Opcode fetch machine cycle

2. Memory Read Machine Cycle of 8085:

The memory read machine cycle is executed by the processor to read a data byte from
memory. The processor takes 3T states to execute this cycle. The instructions which have more
than one byte word size will use the machine cycle after the opcode fetch machine cycle.

Fig 2.8 Memory Read Machine Cycle

3. Memory Write Machine Cycle of 8085

The memory write machine cycle is executed by the processor to write a data byte in a
memory location. The processor takes, 3T states to execute this machine cycle.

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Memory Write Machine Cycle

4. I/O Read Cycle of 8085

The I/O Read cycle is executed by the processor to read a data byte from I/O port or from the
peripheral, which is I/O, mapped in the system. The processor takes 3T states to execute this
machine cycle. The IN instruction uses this machine cycle during the execution.

I/O Read Cycle

5. I/O Write Cycle of 8085

The I/O write machine cycle is executed by the processor to write a data byte in the I/O
port or to a peripheral, which is I/O, mapped in the system. The processor takes, 3T states to
execute this machine cycle.

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I/O Write Cycle

Timing diagram for STA 526AH

STA means Store Accumulator -The contents of the accumulator is stored in the specified
address (526A). The opcode of the STA instruction is said to be 32H. It is fetched from the
memory 41FFH of machine cycle. Then the lower order memory address is read(6A). - Memory
Read Machine Cycle. Read the higher order memory address (52).- Memory Read Machine Cycle
The combination of both the addresses are considered and the content from accumulator is
written in 526A. - Memory Write Machine Cycle Assume the memory address for the instruction
and let the content of accumulator is C7H. So, C7H from accumulator is now stored in 526A.

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Timing diagram for STA 526AH

INTERRUPTS:
Interrupt is signals send by an external device to the processor, to request the processor to
perform a particular task or work.

 Mainly in the microprocessor based system the interrupts are used for data transfer between
the peripheral and the microprocessor.
 The processor will check the interrupts always at the 2nd T-state of last machine cycle.
 If there is any interrupt it accept the interrupt and send the INTA (active low) signal to the
peripheral.
 The vectored address of particular interrupt is stored in program counter.
 The processor executes an interrupt service routine (ISR) addressed in program counter.
 It returned to main program by RET instruction.

Types of Interrupts:
It supports two types of interrupts.
 Hardware
 Software

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Software interrupts:

 The software interrupts are program instructions. These instructions are inserted at
desired locations in a program.
 The 8085 has eight software interrupts from RST 0 to RST 7. The vector address for
these interrupts can be calculated as follows.

Interrupt number * 8 = Vector address.

For RST 5,5 * 8 = 40 = 28H

Vector addresses of all interrupts

Hardware interrupts:
An external device initiates the hardware interrupts and placing an appropriate signal at the
interrupt pin of the processor. If the interrupt is accepted then the processor executes an interrupt
service routine. The 8085 has five hardware interrupts

(1) TRAP (2) RST 7.5 (3) RST 6.5 (4) RST 5.5 (5) INTR

TRAP:

 This interrupt is a non-maskable interrupt. It is unaffected by any mask or interrupt

enable.
 TRAP bas the highest priority and vectored interrupt.
 TRAP interrupt is edge and level triggered. This means hat the TRAP must go high and
remain high until it is acknowledged.
 In sudden power failure, it executes a ISR and send the data from main memory to backup
memory.
 The signal, which overrides the TRAP, is HOLD signal. (i.e., If the processor receives HOLD
and TRAP at the same time then HOLD is recognized first and then TRAP is recognized).
 There are two ways to clear TRAP interrupt.
1. By resetting microprocessor (External signal)
2. By giving a high TRAP ACKNOWLEDGE (Internal signal)

RST 7.5:

 The RST 7.5 interrupt is a maskable interrupt.

 It has the second highest priority.

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 It is edge sensitive. ie. Input goes to high and no need to maintain high state until it
recognized.

Maskable interrupt. It is disabled by,

1. DI Instruction
2. System or processor reset.
3. After reorganization of interrupt.

It is Enabled by EI instruction.

RST 6.5 and 5.5:

The RST 6.5 and RST 5.5 both are level triggered. ie. Inputs goes to high and stay high until it
recognized.

Maskable interrupt. It is disabled by,

1. DI, SIM instruction

2.System or processor reset.
3.After reorganization of interrupt.

It is Enabled by EI instruction.

The RST 6.5 has the third priority whereas RST 5.5 has the fourth priority.

INTR

INTR is a maskable interrupt. It is disabled by,

1.DI, SIM instruction

2. System or processor reset.
3.After reorganization of interrupt

INTR interrupt is Enabled by EI instruction.

Non- vectored interrupt. After receiving INTA (active low) signal, it has to supply the address of
ISR. It has lowest priority. It is a level sensitive interrupts. ie. Input goes to high and it is
necessary to maintain high state until it recognized.

The following sequence of events occurs when INTR signal goes high.

1. The 8085 checks the status of INTR signal during execution of each
instruction.
2. If INTR signal is high, then 8085 complete its current instruction and sends
active low interrupt acknowledge signal, if the interrupt is enabled.
3. In response to the acknowledge signal, external logic places an instruction
OPCODE on the data bus. In the case of multibyte instruction, additional interrupt
acknowledge machine cycles are generated by the 8085 to transfer the additional
bytes into the microprocessor.
4. On receiving the instruction, the 8085 save the address of next instruction on stack and execute
received instruction.

SIM and RIM for interrupts:

The 8085 provide additional masking facility for RST 7.5, RST 6.5 and RST 5.5 using SIM
instruction. The status of these interrupts can be read by executing RIM instruction. The masking or

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unmasking of RST 7.5, RST 6.5 and RST 5.5 interrupts can be performed by moving an 8-bit data to
accumulator and then executing SIM instruction.

Format of 8 bit data to be loaded into the Accumulator using SIM Instruction
The status of pending interrupts can be read from accumulator after executing RIM
instruction. When RIM instruction is executed an 8-bit data is loaded in accumulator, which can
be interpreted as shown in fig 1.14.

Format of 8 bit data in Accumulator after executing RIM

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8051 MICRO CONTROLLER

Microprocessors Vs. Microcontrollers

Microprocessor
• CPU is stand-alone, RAM, ROM, I/O, timer are separate
• Designer can decide on the amount of ROM, RAM and I/O ports.
• Expensive
• Their instructions operate on nibbles, bytes, words, or even double words.
• Addressing modes provide access to large arrays of data using pointers and offsets.
• Versatility
• General-purpose.

Microcontroller

• CPU, RAM, ROM, I/O and timer are all on a single chip
• Fix amount of on-chip ROM, RAM, I/O ports
• They have instructions to set and clear individual bits and perform bit operations.
• They have instructions for input/output operations, event timing, enabling and setting priority
levels for interrupts caused by external stimuli
• For applications in which cost, power and space are critical
• Single-purpose

8051 Architecture
Accumulator (ACC) :
The accumulator register act as an operand register, in case of some instructions .This may
either be implicit or specified in the instruction. The Acc register has been allotted and address in the
on chip special function register bank.

B Register:
The register in used to store one of the operands for multiply and divide instructions . In other
instructions, it may just be used as a scratch pad. This register is considered as a special faction
register.

Program status word (PSW)

This set of flags contains the status information and is considered as one on of the special
registers.

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Architecture of 8051

Stack pointer (Sp) :

This 8 bit wide register is incremented before the data is stored on to the stack using push or
call instructions. The register contains 8 bit stack top address. This stack may be defined anywhere in
the on chip 128 by the RAM. After reset, the SP register is initialized to 07. After each write to stack
operation, the 8 bit contents of the operand are stored on to the stack after incrementing the SP
register by one . Thus if SP contains 07H, the forthcoming PUSH operation will store the data at

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address 08 H in the internal RAM .The SP content will be incremented to 08.The 8051 stack is not a
top down data structure, like other Intel processors This register has also been allotted an address in
the special function register bank .

Data Pointer (DTPR)

This 16 bit register contains a higher byte (DPH) and the lower byte (DPL) of a 16 bit
external data RAM address. It is accessed as a 16 bit register or two 8bit register as specified above. It
has been allotted two address in the special Function register bank for its two bytes DPH and DPL

Port 0 to 3 latches and Drivers:

These four latches and drivers pairs are allotted to each of the four on chip I/O Ports. These
latches have been allotted addresses in the special function register bank using the allotted address
the user can communicate with these ports. These are identified as P0, P1, P2 and P3

Serial data buffer:

The serial data buffer internally contains two independent registers. one of them is a transmit
buffer which is necessarily a parallel .

Timing and control unit :

This unit derives all the necessary timing and control signal required for the internal operation
of the circuit It also derives control signal required for controlling the external system bus oscillator :
This circuit generates the basic timing clock signal for the operation of the circuit using crystal
oscillator .

Instruction Register :
This register decodes the opcode of an instruction to be executed and gives information to the
timing and control unit to generate necessary signals for the execution of the instruction

EPROM and Program Address Register :

These blocks provide an on chip EPROM and a mechanism to internally adders it Note that
EPROM is not available in all 8051 versions.

RAM and RAM address Register .

This block provide internal 128 bytes of RAM and mechanism to address it internally .

ALU
The arithmetic and logic unit performs 8 bit arithmetic and logical operations over the
operands held by the temporary registers TMPI and TMP2 .Users cannot access these temporary
registers .

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SFR Register Bank :

This is a set of special function registers which can be addressed using their respective
address which lie in the range 80 H to FFH . Finally the interrupt , serial port and timer units control
and perform their special functions under the control of the timing and control unit in serial out
register . The other is called receive butter which in a serial in parallel out register. Loading a byte to
the transmit buffer initiates serial transmission of that byte. The serial data butter in identified as
SBUF and is one of the special function registers. If a byte is written to SBUF, it initiates serial
transmission and if the SBUF is read, it reads received serial data .

Timer Register :

These two 16 bit register can be accessed as their lower and upper bytes. For example TL0
represents the lower byte of the timing register 0, while TH0 represents higher bytes of the timing
register 0. Similarly TL1 and TH1 represents lower and higher bytes of timing register 1. All these
registers can be accessed using the 4 addresses allotted to them which lies in the special function
registers. SFR address range, ie 80H to FFH .

Control Registers :

The special function registers IP, IE, TMOD, TCON, SCON and PCON contain control and
status information for interrupt timer/ counters and serial port. These register have been allotted
address in the SFR bank of 8051.

Program Status Word Register(PSW): -

D7 D6 D5 D4 D3 D2 D1 D0

CY AC F0 RS1 RS0 OV ---- PF

It contains several status bits that reflect the current state of the CPU. Besides, this register contains
four mathematical flags (Carry flag, Auxiliary Carry, Overflow flag, parity bit) two register bank
select bits (RS1 & RS0), and one user-definable status flag (F0) and one bit is not defined.

P - Parity bit: - If a number stored in the accumulator A contains even number of 1’s then this bit
will be automatically set (1), otherwise it will be cleared (0). It is mainly used during data transmit
and receive via serial communication.

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OV Overflow: - Overflow occurs when the result of an arithmetical operation is larger than 255 and
cannot be stored in one register. Overflow condition causes the OV bit to be set (1). Otherwise, it will
be cleared (0).

RS0, RS1 - Register bank select bits. These two bits are used to select one of four register banks of
RAM. By setting and clearing these bits, registers R0-R7 are stored in one of four banks of RAM.

RS1 RS0 Space in RAM

0 0 Bank0 (00H-07H)

0 1 Bank1 (08H-0FH)

1 0 Bank2 (10H-17H)
1 1 Bank3 (18H-1FH)

F0 - Flag 0. This is a general-purpose user defined flag.

AC - Auxiliary Carry Flag: - It is used for BCD operations only. This flag is set to ‘1’ when in the
addition operation the carry is generated at bit position D3 or in subtraction operation borrow is
needed at the bit position D3.

CY - Carry Flag: - This flag is set to ‘1’ when in the addition operation the final carry is generated or
in subtraction operation the Minuend is less than the Subtrahend.

PC (Program Counter): -It addresses the next instruction byte address in the program memory.
Program memory is on chip i.e. is 0000H to 0FFFH, external to the chip for addresses that exceeds
0FFFH or total external memory 0000h to 0FFFFH. The content of the PC is automatically
incremented after fetching of the instruction byte from the memory and some instructions also change
the value in the PC. The specialty of this register is it doesn’t have any internal address.

DPTR (Data Pointer): - It is made up of two 8-bit registers those are DPH & DPL. This register
gives the memory addresses for internal and external code access and external data access. The DPTR
has two independent internal addresses, one for DPL and another for DPH.

Internal Memory: - The 8051 Microcontroller has internal program memory (ROM) and internal
data memory (RAM). Due to this 8051 has a Harvard architecture, which uses a same address in
different memories, for code and data.

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Internal RAM: - The 8051 microcontroller has 128 bytes of internal RAM, its address range from
00H to 07FH. From 80H to 0FFH addresses are assigned to SFRs (Special Function Registers). The
internal RAM 128Bytes can divide into three parts. Those are

1. Register Banks – 32 Bytes (00H – 1FH)

2. Bit/Byte addressable memory – 16 Bytes (20H – 2FH)
3. User memory or General purpose memory—80 Bytes (30H – 7FH)

PIN Diagram

Pins 1-8: Port 1 Each of these pins can be configured as an input or an output.

Pin 9: RS A logic one on this pin disables the microcontroller and clears the contents of most
registers. In other words, the positive voltage on this pin resets the microcontroller. By applying logic
zero to this pin, the program starts execution from the beginning.

Pins10-17: Port 3 Similar to port 1, each of these pins can serve as general input or output. Besides,
all of them have alternative functions:

Pin 10: RXD Serial asynchronous communication input or Serial synchronous communication output.
Pin 11: TXD Serial asynchronous communication output or Serial synchronous communication clock
output.

Pin 12: INT0 Interrupt 0 input.

Pin diagram of 8051

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Pin 13: INT1 Interrupt 1 input.

Pin 14: T0 Counter 0 clock input.

Pin 15: T1 Counter 1 clock input.

Pin 16: WR Write to external (additional) RAM.

Pin 17: RD Read from external RAM.

Pin 18, 19: X2, X1 Internal oscillator input and output. A quartz crystal which specifies operating
frequency is usually connected to these pins.

Pin 20: GND Ground.

Pin 21-28: Port 2 If there is no intention to use external memory then these port pins are configured as
general inputs/outputs. In case external memory is used, the higher address byte, i.e. addresses A8-
A15 will appear on this port. Even though memory with capacity of 64Kb is not used,

Pin 29: PSEN If external ROM is used for storing program then a logic zero (0) appears on it every
time the microcontroller reads a byte from memory.

Pin 30: ALE Prior to reading from external memory, the microcontroller puts the lower address byte
(A0-A7) on P0 and activates the ALE output. After receiving signal from the ALE pin, the external
register (usually 74HCT373 or 74HCT375 add-on chip) memorizes the state of P0 and uses it as a
memory chip address.

Pin 31: EA By applying logic zero to this pin, P2 and P3 are used for data and address transmission
with no regard to whether there is internal memory or not. It means that even there is a program
written to the microcontroller, it will not be executed. Instead, the program written to external ROM
will be executed. By applying logic one to the EA pin, the microcontroller will use both memories,
first internal then external (if exists).

Pin 32-39: Port 0 Similar to P2, if external memory is not used, these pins can be used as general
inputs/outputs. Otherwise, P0 is configured as address output (A0-A7) when the ALE pin is driven
high (1) or as data output (Data Bus) when the ALE pin is driven low (0).

Pin 40: VCC +5V power supply.

Memory Organization

The 8051 microcontroller utilizes the Harvard architecture, with separate code and data
spaces. Memory organization in 8051 is similar to that of the industry standard 8051. There are three
memory areas, as shown.

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• Program Memory (Internal RAM, External RAM, or External ROM)

• External Data Memory (External RAM)

• Internal Data Memory (Internal RAM)

Program Memory

8051 can address up to 64kB of program memory space, from 0000H to FFFFH. The External
Bus Interface services program memory when the MEMPSRD signal is active. Program memory is
read when the CPU performs fetching instructions or MOVC. After reset, the CPU starts program
execution from location 0000H. The lower part of the program memory includes interrupt and reset
vectors. The interrupt vectors are spaced at eight-byte intervals, starting from 0003H. Program
memory can be implemented as Internal RAM, External RAM, External ROM, or a combination of
all three.

Program memory

External Data Memory

8051 can address up to 64kB of external data memory space, from 0000H to FFFFH. The
External Bus Interface services data memory when the MEMRD signal is active. Writing to external
program memory is only supported in debug mode using the OCI logic block and external debugger
hardware and software. 8051 writes into external data memory when the CPU executes MOVX @Ri
,A or MOVX @DPTR,A instructions.

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Internal Data Memory

The internal data memory interface services up to 256 bytes of off-core data memory. The
internal data memory address is always one byte wide. The memory space is 256 bytes large (00H to
FFH) and can be accessed by direct or indirect addressing.

Lower 128 Bytes of Internal RAM

Upper 128 Bytes of
Internal RAM

Internal Data Memory

On-Chip Memory.
The 8051 includes a certain amount of on chip memory. On-chip memory is really one of two
(SFR) memory. The layout of the 8051's internal memory is presented in the following memory map:

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On-Chip Memory

The Internal RAM is found on-chip on the 8051 so it is the fastest RAM available, and it is also the
most flexible in terms of reading, writing, and modifying it’s contents.

Bit Memory

The 8051, being a communications oriented microcontroller, gives the user the ability to access a
number of bit variables. These variables may be either 1 or 0. There are 128 bit variables available to
the user, numbered 00h through 7Fh. The user may make use of these variables with commands such
as SETB and CLR.

Bit variables 00h through 7Fh are for user defined functions in their programs. However, bit
variables 80h and above are actually used to access certain SFRs on a bit-by-bit basis.

Special Function Register (SFR) Memory

Special Function Registers (SFRs) are areas of memory that control specific functionality of the
8051 processor. For example, four SFRs permit access to the 8051’s 32 input/output lines. Another
SFR allows a program to read or write to the 8051’s serial port. Other SFRs allow the user to set the
serial baud rate, control and access timers, and configure the 8051’s interrupt system. When
programming, SFRs have the illusion of being Internal Memory. When using this method of memory
access (it’s called direct address), any instruction that has an address of 00h through 7Fh refers to an
Internal RAM memory address; any instruction with an address of 80h through FFh refers to an SFR
control register.

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