Aits Cse06 Cao Text-Assignment-03 Usman
Aits Cse06 Cao Text-Assignment-03 Usman
Instructions:
- The instructions are written in machine language or assembly language, and they are
executed in a specific sequence to perform a task.
Types of Instructions:
- There are different types of instructions that a computer can execute. Some common
types include:
1. Data Transfer Instructions: These instructions are used to move data from one memory
location to another.
2. Arithmetic and Logical Instructions: These instructions are used for performing
arithmetic and logical operations such as addition, subtraction, multiplication, and logical
AND, OR, NOT, etc.
3. Control Transfer Instructions: These instructions are used for controlling the flow of the
program execution, such as branching, jumping, and subroutine calls.
4. Input/Output Instructions: These instructions are used for input and output operations
such as reading from and writing to input/output devices.
Flynn's Classification:
- The classification is based on the number of instruction streams (or program counters)
and the number of data streams (or operands) that a computer can process simultaneously.
Types of Flynn's Classification:
1. Single Instruction Single Data (SISD): This type of architecture has a single processor
that executes a single instruction stream and operates on a single data stream at a time. It is
a traditional uniprocessor architecture.
2. Single Instruction Multiple Data (SIMD): This type of architecture has multiple
processors that execute the same instruction stream and operate on different data streams
simultaneously. It is commonly used in parallel processing for tasks that can be broken
down into many independent operations.
3. Multiple Instruction Single Data (MISD): This type of architecture has multiple
processors that execute different instruction streams but operate on the same data stream.
It is less common in practice.
4. Multiple Instruction Multiple Data (MIMD): This type of architecture has multiple
processors that execute different instruction streams and operate on different data streams
simultaneously. It is commonly used in parallel processing for tasks that require multiple
independent operations.
Addressing Modes:
- Addressing modes are used to specify the memory address of the operands for an
instruction.
1. Immediate Addressing: The operand is a constant value that is part of the instruction.
Example: MOV A, #10 (Move the value 10 to register A).
2. Direct Addressing: The operand is a memory location that contains the value to be used.
Example: MOV A, [1234H] (Move the value stored at memory location 1234H to register
A).
3. Indirect Addressing: The operand is a memory location that contains the memory
address of the value to be used. Example: MOV A, [BX] (Move the value stored at the
memory location whose address is stored in register BX to register A).
CISC Pipeline:
- In CISC pipeline architecture, the processor fetches and decodes complex instructions
and then executes them in a series of stages.
Example:
Suppose we have an instruction "ADD R1, [R2]" that adds the value stored in memory
location pointed to by R2 to the value stored in register R1. In the CISC pipeline, this
instruction would be executed in the following stages:
2. Instruction decode: Decode the instruction to determine the operands and the operation
to be performed.
4. Memory access: Fetch the value from the memory location pointed to by R2.
5. Execute operation: Add the fetched value to the value stored in R1 and store the result in
R1.
RISC Pipeline:
- In RISC pipeline architecture, the processor fetches and executes simple instructions in a
series of stages.
Example:
Suppose we have an instruction "ADD R1, R2, R3" that adds the value stored in register
R2 to the value stored in register R3 and stores the result in register R1. In the RISC
pipeline, this instruction would be executed in the following stages:
2. Instruction decode: Decode the instruction to determine the operands and the operation
to be performed.
4. Execute operation: Add the fetched values and store the result in register R1.
Pipeline Processor:
- A pipeline processor is a type of processor that breaks down a task into multiple stages
and processes each stage in parallel.
- Each stage in the pipeline operates on a different set of data, and the output of one stage
becomes the input for the next stage.
Vector Processor:
- The processor has specialized instructions that can perform the same operation on
multiple data elements simultaneously.
- This technique allows for highly efficient processing of large amounts of data in parallel.
Array Processor:
- An array processor is a type of processor that is specifically designed for processing
arrays of data.
- The processor has multiple processing elements that can operate in parallel on different
parts of the array.
- This technique allows for highly efficient processing of large arrays of data.
Stack Organization:
- The stack is a special area of memory used by the Central Processing Unit (CPU) to store
data temporarily.
- It is a Last-In-First-Out (LIFO) data structure, which means that the last item added to
the stack is the first item to be removed.
- The stack is used for storing local variables, function arguments, return addresses, and
other data during the execution of a program.
1. Stack Pointer (SP): It is a register that holds the address of the top of the stack.
2. Base Pointer (BP): It is a register that holds the address of the base of the current stack
frame.
The CPU uses the stack pointer to push data onto the stack and pop data off the stack.
When data is pushed onto the stack, the stack pointer is decremented, and when data is
popped off the stack, the stack pointer is incremented.
During the execution of a function, a new stack frame is created, and the base pointer is
updated to point to the base of the new stack frame. The base pointer is used to access the
local variables and function arguments of the current stack frame.
When a function call is made, the CPU pushes the return address onto the stack along with
any function arguments. When the function returns, the CPU pops the return address off
the stack and jumps to that address to resume execution of the calling function.