Background

• Program must be brought (from disk) into memory and

placed within a process for it to be run
• Main memory and registers are only storage CPU can
Memory Management access directly
• Register access in one CPU clock (or less)
• Main memory can take many cycles
• Cache sits between main memory and CPU registers
• Protection of memory required to ensure correct
operation

1 2

Binding of Instructions and Data to

Base and Limit Registers
Memory
• A pair of base and limit registers define
• Address binding of instructions and data to memory
the logical address space
addresses can happen at three different stages
– Compile time: If memory location known a priori,
absolute code can be generated; must recompile code if
starting location changes
– Execution time: Binding delayed until run time if the
process can be moved during its execution from one
memory segment to another. Need hardware support
for address maps (e.g., base and limit registers)

3 4

Multistep Processing of a User Program Logical vs. Physical Address Space

• The concept of a logical address space that is bound to
a separate physical address space is central to proper
memory management
– Logical address – generated by the CPU; also
referred to as virtual address
– Physical address – address seen by the memory
unit
• Logical and physical addresses are the same in
compile-time address-binding schemes; logical
(virtual) and physical addresses differ in execution-
time address-binding scheme
5 6

1
 Dynamic Relocation Using a
Memory-Management Unit (MMU) Relocation Register
• Hardware device that maps virtual to physical
address

• In MMU scheme, the value in the relocation

(base) register is added to every address
generated by a user process at the time it is sent
to memory

• The user program deals with logical addresses;

it never sees the real physical addresses
7 8

Dynamic Loading Swapping

• A process can be swapped temporarily out of memory
• Routine is not loaded until it is called. to a backing store, and then brought back into memory
• Better memory-space utilization; unused for continued execution
routine is never loaded. • Backing store –disk large enough to accommodate
• Useful when large amounts of code are copies of all memory images for all users;
needed to handle infrequently occurring cases • Roll out, roll in – swapping variant used for priority-
based scheduling algorithms; lower-priority process is
• No special support from the operating system swapped out so higher-priority process can be loaded
is required, implemented through program and executed
design. • System maintains a ready queue of ready-to-run
processes which have memory images on disk
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Schematic View of Swapping Contiguous Allocation

• Main memory usually divided into two partitions:
– Resident operating system, usually held in low memory.
– User processes then held in high memory.
• Relocation registers used to protect user processes from
each other, and from changing operating-system code
and data.
– Base register contains value of smallest physical address
– Limit register contains range of logical addresses – each
logical address must be less than the limit register.
– MMU maps logical address dynamically.
11 12

2
 HW Address Protection with Base and Contiguous Allocation (Cont.)
Limit Registers • Multiple-partition allocation
Logical +
relocation – Hole – block of available memory; holes of various size are
scattered throughout memory
– When a process arrives, it is allocated memory from a hole
large enough to accommodate it
– Operating system maintains information about:
a) allocated partitions b) free partitions (hole)

OS OS OS OS

process 5 process 5 process 5 process 5

process 9 process 9

process 8 process 10

13 process 2 process 2 process 2 process 2 14

Dynamic Storage-Allocation Problem Fragmentation

• External Fragmentation – total memory space
How to satisfy a request of size n from a list of free holes
exists to satisfy a request, but it is not contiguous
• First-fit: Allocate the first hole that is big enough • Internal Fragmentation – allocated memory
• Best-fit: Allocate the smallest hole that is big enough; may be slightly larger than requested memory;
must search entire list
this size difference is memory internal to a
– Produces the smallest leftover hole
• Worst-fit: Allocate the largest hole; must also search
partition, but not being used
entire list • Reduce external fragmentation by compaction
– Produces the largest leftover hole – Shuffle memory contents to place all free memory
together in one large block
First-fit and best-fit better than worst-fit in – Compaction is possible only if relocation is dynamic, and
terms of speed and storage utilization is done at execution time
15 16

Paging Address Translation Scheme

• Logical address space of a process can be noncontiguous;
process is allocated physical memory whenever the latter is • Address generated by CPU is divided into:
available. – Page number (p) – used as an index into a page table which
contains base address of each page in physical memory
• Divide physical memory into fixed-sized blocks called
frames (size is power of 2). – Page offset (d) – combined with base address to define the
physical memory address that is sent to the memory unit
• Divide logical memory into blocks of same size called pages.
• Keep track of all free frames. page number page offset
• To run a program of size n pages, need to find n free frames p d
and load program. m-n n
• Set up a page table to translate logical to physical addresses.
• Internal fragmentation.
– For given logical address space of size 2m and page size is 2n
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3
 Paging Model of Logical and
Paging Hardware
Physical Memory

19 20

Paging Example Free Frames

32-byte memory and 4-byte pages 21 Before allocation 22

After allocation

Implementation of Page Table Associative Memory

• Page table is kept in main memory
• Associative memory – parallel search
• Page-table base register (PTBR) points to the page table
Page # Frame #
• Page-table length register (PRLR) indicates size of the page
table
• In this scheme every data/instruction access requires two
memory accesses. One for the page table and one for the
data/instruction.
• The two memory access problem can be solved by the use of
a special fast-lookup hardware cache called associative
Address translation (p, d)
memory or translation look-aside buffers (TLBs) – If p is in associative register, get frame # out
• Some TLBs store address-space identifiers (ASIDs) in each – Otherwise get frame # from page table in
TLB entry – uniquely identifies each process to provide memory
address-space protection for that process 23 24

4
Paging Hardware With TLB Memory Protection
• Memory protection implemented by associating
protection bit with each frame.

• Valid-invalid bit attached to each entry in the

page table:
– “valid” indicates that the associated page is in the
process’ logical address space, and is thus a legal
page.
– “invalid” indicates that the page is not in the
process’ logical address space.
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Valid (v) or Invalid (i) Bit Shared Pages

• Shared code
– One copy of read-only (reentrant) code shared among
processes (i.e., text editors, compilers, window
systems).
– Each page table maps onto the same physical copy of
the shared code.
• Private code and data
– Each process keeps a separate copy of the code and
data.
– The pages for the private code and data can appear
anywhere in the logical address space.
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Shared Pages Example Structure of the Page Table

• As the number of processes increases, the
percentage of memory devoted to page tables
also increases.
• The following structures solved this problem:

• Hierarchical Paging

• Hashed Page Tables

• Inverted Page Tables

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5
 Hierarchical Page Tables Two-Level Page-Table Scheme
• Break up the logical address space into
multiple page tables.

• A simple technique is a two-level page

table.

31 32

Two-Level Paging Example Address-Translation Scheme

• A logical address (on 32-bit machine with 1K page size) is
divided into:
– a page number consisting of 22 bits
– a page offset consisting of 10 bits
• Since the page table is paged, the page number is divided into:
– a 12-bit page number
– a 10-bit page offset
• Thus, a logical address is as follows:
page number page offset
p1 p2 d

12 10 10
where p1 is an index into the outer page table, and p2 is the
displacement within the page of the outer page table 33 34

Three-level Paging Scheme Hashed Page Tables

• Common in address spaces > 32 bits.
• The virtual page number is hashed into a page
table. This page table contains a chain of
elements hashing to the same location.
• Virtual page numbers are compared in this
chain searching for a match.
• If a match is found, the corresponding
physical frame is extracted.

35 36

6
 Hashed Page Table Inverted Page Table
• One entry for each real page of memory.
• Entry consists of the virtual address of the page
stored in that real memory location, with
information about the process that owns that
page.
• Decreases memory needed to store each page
table, but increases time needed to search the
table when a page reference occurs.
• Use hash table to limit the search to one — or at
37
most a few — page-table entries. 38

Inverted Page Table Architecture Segmentation

• Memory-management scheme that supports user
view of memory
• A program is a collection of segments. A segment is
a logical unit such as:
main program,
procedure,
function,
method,
object,
local variables, global variables,
common block,
stack,
39 symbol table, arrays 40

User’s View of a Program Logical View of Segmentation

1

4
1

3 2
4

user space physical memory space

41 42

7
 Segmentation Architecture Segmentation Architecture - Cont.
• Logical address consists of a two tuple:
<segment-number, offset>, • Protection
• Segment table – maps two-dimensional physical – With each entry in segment table associate:
addresses; each table entry has: • validation bit = 0 ⇒ illegal segment
– base – contains the starting physical address where the • read/write/execute privileges
segments reside in memory • Protection bits associated with segments; code
– limit – specifies the length of the segment sharing occurs at segment level.
• Segment-table base register (STBR) points to the • Since segments vary in length, memory allocation is
segment table’s location in memory a dynamic storage-allocation problem.
• Segment-table length register (STLR) indicates
number of segments used by a program;
segment number s is legal if s < STLR 43 44

Segmentation Hardware Example of Segmentation

45 46