MAX4896
MAX4896
MAX4896
RELAY
PDCD VS COIL 1
Ordering Information appears at end of data sheet. INT FLAG
OUT1
RESET
µC VRELAY
SCLK MAX4896
CS RELAY
COIL 8
DIN
OUT8
DOUT
SPLD GND PGND
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Note 1: Maximum continuous current at a given temperature must be calculated such that the maximum continuous power dissipation
for the package is not exceeded.
Package Information
20-Pin TQFN
Package Code T2055+5
Outline Number 21-0140
Land Pattern Number 90-0010
Thermal Resistance
Junction to Ambient (θJA) 29ºC/W
Junction to Case (θJC) 2ºC/W
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(VS = +2.7V to +5.5V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
Note 2: Specifications at -40°C are guaranteed by design and not production tested.
Note 3: The output stages are compliant with the transient immunity requirements, as specified in ISO 7637 Part 3 with test pulses
1, 2, 3a, and 3b.
Note 4: Guaranteed by design.
MAX4896 toc02
fDIN = 0.5 x fCLK
MAX4896 toc01
MAX4896 toc03
11 ALL LOGIC INPUTS = VS
5.5 6.5
10
6.0
QUIESCENT CURRENT (µA)
5.0
SUPPLY CURRENT (mA)
9
5.5
8 TA = +85°C 4.5 VS = 5V
TA = +125°C 5.0 IOUT_SINK = 100mA
7
RON (Ω)
4.0 VS = 3.3V
6 4.5
5 3.5 4.0
4
3.5
3 TA = +25°C 3.0
3.0
2 TA = -40°C 2.5 IOUT_SINK = 50mA
1 VS = 2.7V 2.5
0 2.0 2.0
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 0.1 1 10 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
SUPPLY VOLTAGE (V) fCLK (MHz) SUPPLY VOLTAGE (V)
MAX4896 DS toc06
MAX4896 toc04
6 VS = 2.7V 6 2.10
VS = 5V
5 VS = 3.3V 5 VS = 3.3V 2.08
RON (Ω)
RON (Ω)
4 4 2.06
3 3 2.04
VS = 5.5V
VS = 5.5V
2 VS = 5V 2 2.02
1 1 2.00
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
OUTPUT OFF LEAKAGE CURRENT OUT LEAKAGE CURRENT INPUT LOGIC THRESHOLD
vs. SUPPLY VOLTAGE vs. TEMPERATURE vs. SUPPLY VOLTAGE
100 100 2.50
MAX4896 toc09
MAX4896 DS toc08
MAX4896 toc07
PDCD = VS
90 2.25
OUT LEAKAGE CURRENT (nA)
10
INPUT LOGIC THRESHOLD (V)
80 VOUT = 50V
OUTPUT OFF LEAKAGE (pA)
2.00
70
1 1.75
60 VOUT = 50V
50 1.50
VOUT = 24V
40 0.1 VOUT = 24V 1.25
30 VOUT = 12V
VOUT = 12V 1.00
20 0.01
0.75
10
0 0.001 0.50
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 -40 -25 -10 5 20 35 50 65 80 95 110 125 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
SUPPLY VOLTAGE (V) TEMPERATURE (°C) SUPPLY VOLTAGE (V)
MAX4896 toc11
MAX4896 toc12
VOUT = 15V RL = 300Ω VOUT = 50V RL = 150Ω
4.5 750 TA = -40°C
CL = 50pF CL = 50pF
2.5
700
3.5
2.0
tOFF 3.0 650
TA = +85°C
1.5 2.5 600
2.0 tOFF
550
1.0
1.5 TA = +125°C
tON 500
1.0
0.5
0.5 tON 450
0 0 400
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 4.5 4.7 4.9 5.1 5.3 5.5 4.5 4.7 4.9 5.1 5.3 5.5
SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)
VS = 3.3V VS = 5V
65.8
65.6 RESET RESET
0UT CLAMP VOLTAGE (V)
Pin Configuration
TOP VIEW
OUT3
OUT4
OUT5
OUT6
GND
15 14 13 12 11
PGND 16 10 PGND
OUT2 17 9 OUT7
VS 19 7 SPLD
*EP
+ 6 PDCD
FLAG 20
1 2 3 4 5
RESET
CS
DIN
SCLK
TQFN DOUT
(5mm x 5mm)
*EXPOSED PAD. CONNECT TO PGND.
Pin Description
PIN NAME FUNCTION
Reset Input. Drive RESET low to clear all latches and registers (all outputs are turned off). All OUT
1 RESET
pulldown currents are disabled when RESET = low.
Chip Select Input. Drive CS low to select the device. When CS is low, data at DIN is clocked into the
2 CS
8-bit shift register on SCLK’s rising edge. Drive CS from low to high to latch the data to the registers.
3 DIN Serial Data Input
4 SCLK Serial Clock Input
Serial Data Output. DOUT is the output of the 8-bit shift register. This output can be used to daisy chain
5 DOUT
multiple MAX4896s. The data at DOUT appears synchronous to SCLK’s falling edge.
Pulldown Current Disable. Drive PDCD high to disable OUT’s pulldown current source. Drive PDCD low
6 PDCD
to enable OUT_ pulldown current source. PDCD must be low to detect an open-load fault.
Short-Protection Latch-Off Disable Input. Drive SPLD high to disable the built-in short-circuit protection
7 SPLD latch-off feature. When SPLD is low, an overloaded channel is turned off immediately. See the Output
Short-Circuit/Current-Limiting Protection section.
Open-Drain Output 8. Connect OUT8 to the low side of a relay coil. OUT8 is pulled to PGND when
8 OUT8
activated and is otherwise high impedance.
Open-Drain Output 7. Connect OUT7 to the low side of a relay coil. OUT7 is pulled to PGND when
9 OUT7
activated and is otherwise high impedance.
Power Ground. PGND is the ground return path for the output sinks. Connect PGND pins together and
10, 16 PGND
to GND.
Functional Diagram
VS PDCD SPLD
OUT1
CLAMP
GATE CONTROL
AND CURRENT
LIMITING
RESET 8-BIT
LATCH
OPEN / SHORT
DETECT
CHANNEL 1
MAX4896
GND PGND
Detailed Description is an 8-bit word. Each data bit controls one of the eight
The MAX4896 is an 8-channel relay and load driver for outputs, with the most significant bit (D7) corresponding
medium voltage applications up to 50V. The MAX4896 to OUT8, and the least significant bit (D0) corresponding
features built-in inductive kickback protection, drive for to OUT1 (see Table 1). When CS is low, data at DIN is
latching/nonlatching, or dual-coil relays and an internal clocked into the shift register synchronously with SCLK’s
register for detecting open-load and short-circuit faults. rising edge. Driving CS from low to high latches the data
Each independent open-drain output features a 3Ω on- in the shift register to the output control register.
resistance and is guaranteed to sink 400mA at VS ≥ 4.5V, DOUT is the output of the internal output status register
and 100mA at VS ≤ 3.6V. for diagnostics purposes (see Figure 2 and Tables 2 and
The MAX4896 also incorporates a logic input (SPLD) 3). Status data for each channel is transferred to the shift
that allows the device to continue operating when an register at the falling edge of CS. The data bits contained
overcurrent condition lasts longer than the 280μs (max) in the shift register are then transferred to the DOUT out-
fault delay time. A built-in overvoltage protection clamp put synchronously with SCLK’s falling edge.
handles kickback voltage transients, which are common While CS is low, the switches always remain in their previ-
when driving inductive loads. Thermal-shutdown circuitry ous states. Drive CS high after 8 bits of data have been
shuts off all outputs (OUT_) when the junction tempera- shifted in to update the output state, and to further inhibit
ture exceeds +160°C. data from entering the shift register. When CS is high,
The MAX4896 employs a reset input that allows the user to transitions at DIN and SCLK have no effect on the output,
turn off all outputs simultaneously with a single control line. and the first input bit (D7) is present at DOUT.
The MAX4896 includes a 10MHz SPI-/QSPI-/MICROWIRE If the number of data bits entered while CS is low is
compatible serial interface. The serial interface is compat- greater or less than 8, the shift register contains only the
ible with TTL-/CMOS-logic voltage levels and operates last 8 data bits, regardless of when they were entered.
with a single +2.7V to +5.5V supply. The 3-wire serial interface is compatible with SPI, QSPI,
and MICROWIRE standards. The latch that drives the
Serial Interface analog output stages is updated on the rising edge of CS,
The serial interface consists of an 8-bit input shift regis- regardless of SCLK’s state.
ter, a parallel latch (output control register) controlled by
SCLK and CS, and an output status register containing Diagnostic Information
diagnostics information. The input to the shift register The MAX4896 contains an internal output status register
used for diagnostics information for each output (see
Tables 1, 2, and 3). When a fault condition is detected
at any channel for longer than the minimum fault-filtering
OUTPUT STATUS REGISTER (OSR) time (tD(FAULT)_min), the fault information is latched into
the corresponding position in the output status register
LATCHED ON CS:
(see Table 2), and the FLAG asserts. Status/diagnostics
DIN data for each channel in the output status register is trans-
DOUT
SCLK 8-BIT SHIFT REGISTER ferred to the output shift register at the falling edge of CS.
CS While CS is low, the diagnostics bits are then transferred
LATCHED ON CS:
to DOUT synchronously with SCLK’s falling edge. A rising
edge at CS resets the output status register data. During
OUTPUT CONTROL REGISTER (OUT) normal operation,the output status bit is the same as the
DIN bit (DO1 = D1, DO2 = D2). When the MAX4896 is
operating with a fault condition, the output status bit is the
Figure 1. Serial Interface inverse of the DIN bit (DO1 = 0, D1 = 1).
CS tCSW
tCSH tCSO
tCSS tCL tCH
SCLK
tDH
tDS
DIN D7 D6 D1 D0
tDO
DOUT
tON,
tOFF
OUT_
VS VS
0.1µF 0.1µF
DEVICE 1 DEVICE 2
VS VS
MAX4896 MAX4896
OUT1 OUT1
CS
20 TQFN-EP*
MAX4896ATP+ -40°C to +125°C
(5mm x 5mm)
20 TQFN-EP*
MAX4896ETP+ -40°C to +85°C
(5mm x 5mm)
Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
0 10/05 Initial release —
1 6/07 Removal of future product notice -
2 12/07 EP clarification 7
3 7/12 Updated FLAG Output section 10
4 5/14 Removed automotive reference under Applications section 1
Updated the General Description, Benefits and Features, Typical Operating Cir-
5 1/20 cuit, Pin Description, Detailed Description, Output Short-Circuit/Current-Limiting 1, 7–8, 10–11
Protection, Open-Load Detection, and FLAG Output sections, and Figure 3
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Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
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