6809 / 6309 Programming Aid

Addressing Modes
Immediate Direct Indexed 1 Extended Inherent 5 3 2 1 0
Instr. Forms Op ~ # Op ~ # Op ~ # Op ~ # Op ~ # Description H N Z V C
ABX ABX 3A 3/1 1 X = X + B (unsigned) - - - - -
ADC ADCA 89 2 2 99 4/3 2 A9 4+ 2+ B9 5/4 3 A = A + M8 + C ↕ ↕ ↕ ↕ ↕
ADCB C9 2 2 D9 4/3 2 E9 4+ 2+ F9 5/4 3 B = B + M8 + C ↕ ↕ ↕ ↕ ↕
ADCD 089 5/4 4 099 7/5 3 0A9 7/6+ 3+ 0B9 8/6 4 D = D + M16 + C - ↕ ↕ ↕ ↕
ADCR 031 4 3 r1 = r1 + r0 + C See Note 2 - ↕ ↕ ↕ ↕
ADD ADDA 8B 2 2 9B 4/3 2 AB 4+ 2+ BB 5/4 3 A = A + M8 ↕ ↕ ↕ ↕ ↕
ADDB CB 2 2 DB 4/3 2 EB 4+ 2+ FB 5/4 3 B = B + M8 ↕ ↕ ↕ ↕ ↕
ADDD C3 4/3 3 D3 6/4 2 E3 6/5+ 2+ F3 7/5 3 D = D + M16 - ↕ ↕ ↕ ↕
ADDE 18B 3 3 19B 5/4 3 1AB 5+ 3+ 1BB 6/5 4 E = E + M8 ↕ ↕ ↕ ↕ ↕
ADDF 1CB 3 3 1DB 5/4 3 1EB 5+ 3+ 1FB 6/5 4 F = F + M8 ↕ ↕ ↕ ↕ ↕
ADDR 030 4 3 r1 = r1 + r0 See Note 2 - ↕ ↕ ↕ ↕
ADDW 08B 5/4 4 09B 7/5 3 0AB 7/6+ 3+ 0BB 8/6 4 W = W + M16 - ↕ ↕ ↕ ↕
AIM #I8, EA 02 6 3 62 7+ 3+ 72 7 4 M8 = M8 & I8 - ↕ ↕ 0 -
AND ANDA 84 2 2 94 4/3 2 A4 4+ 2+ B4 5/4 3 A = A & M8 - ↕ ↕ 0 -
ANDB C4 2 2 D4 4/3 2 E4 4+ 2+ F4 5/4 3 B = B & M8 - ↕ ↕ 0 -
ANDCC 1C 3 2 CC = CC & I8 See Note 7
ANDD 084 5/4 4 094 7/5 3 0A4 7/6+ 3+ 0B4 8/6 4 D = D & M16 - ↕ ↕ 0 -
ANDR 034 4 3 r1 = r1 & r0 See Note 2 - ↕ ↕ 0 -
ASL ASLA 48 2/1 1 8 ↕ ↕ ↕ ↕
A
ASLB
ASLD
ASL 08 6/5 2 68 6+ 2+ 78 7/6 3
58
048
2/1
3/2
1
2
B
D
M8
} C bn b0
0
8
-
8
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
ASR ASRA 47 2/1 1 8 ↕ ↕ - ↕
ASRB
ASRD
ASR 07 6/5 2 67 6+ 2+ 77 7/6 3
57
047
2/1
3/2
1
2
A
B
D
M8
} bn b0 C
8
-
8
↕
↕
↕
↕
↕
↕
-
-
-
↕
↕
↕
BAND BAND 130 7/6 4 R.dstBit = M8.srcBit & R.dstBit See Note 3
BIAND 131 7/6 4 R.dstBit = M8.srcBit & R.dstBit See Note 3
BEOR BEOR 134 7/6 4 R.dstBit = M8.srcBit XOR R.dstBit See Note 3
BIEOR 135 7/6 4 R.dstBit = M8.srcBit XOR R.dstBit See Note 3
BIT BITA 85 2 2 95 4/3 2 A5 4+ 2+ B5 5/4 3 Bit Test A (A & M8) - ↕ ↕ 0 -
BITB C5 2 2 D5 4/3 2 E5 4+ 2+ F5 5/4 3 Bit Test B (B & M8) - ↕ ↕ 0 -
BITD 085 5/4 4 095 7/5 3 0A5 7/6+ 3+ 0B5 8/6 4 Bit Test D (D & M16) - ↕ ↕ 0 -
BITMD 13C 4 3 Bit Test MD (MD & I8) bits 6 and 7 only - - ↕ - -
BOR BOR 132 7/6 4 R.dstBit = M8.srcBit | R.dstBit See Note 3
BIOR 133 7/6 4 R.dstBit = M8.srcBit | R.dstBit See Note 3
CLR CLRA 4F 2/1 1 A=0 - 0 1 0 0
CLRB 5F 2/1 1 B=0 - 0 1 0 0
CLRD 04F 3/2 2 D=0 - 0 1 0 0
CLRE 14F 3/2 2 E=0 - 0 1 0 0
CLRF 15F 3/2 2 F=0 - 0 1 0 0
CLRW 05F 3/2 2 W=0 - 0 1 0 0
CLR 0F 6/5 2 6F 6+ 2+ 7F 7/6 3 M8 = 0 - 0 1 0 0
CMP CMPA 81 2 2 91 4/3 2 A1 4+ 2+ B1 5/4 3 Compare M8 from A 8 ↕ ↕ ↕ ↕
CMPB C1 2 2 D1 4/3 2 E1 4+ 2+ F1 5/4 3 Compare M8 from B 8 ↕ ↕ ↕ ↕
CMPD 083 5/4 4 093 7/5 3 0A3 7/6+ 3+ 0B3 8/6 4 Compare M16 from D - ↕ ↕ ↕ ↕
CMPE 181 3 3 191 5/4 3 1A1 5+ 3+ 1B1 6/5 4 Compare M8 from E 8 ↕ ↕ ↕ ↕
CMPF 1C1 3 3 1D1 5/4 3 1E1 5+ 3+ 1F1 6/5 4 Compare M8 from F 8 ↕ ↕ ↕ ↕
CMPR 037 4 3 Compare r0 from r1 See Note 2 - ↕ ↕ ↕ ↕
CMPS 18C 5/4 4 19C 7/5 3 1AC 7/6+ 3+ 1BC 8/6 4 Compare M16 from S - ↕ ↕ ↕ ↕
CMPU 183 5/4 4 193 7/5 3 1A3 7/6+ 3+ 1B3 8/6 4 Compare M16 from U - ↕ ↕ ↕ ↕
CMPW 081 5/4 4 091 7/5 3 0A1 7/6+ 3+ 0B1 8/6 4 Compare M16 from W - ↕ ↕ ↕ ↕
CMPX 8C 4/3 3 9C 6/4 2 AC 6/5+ 2+ BC 7/5 3 Compare M16 from X - ↕ ↕ ↕ ↕
CMPY 08C 5/4 4 09C 7/5 3 0AC 7/6+ 3+ 0BC 8/6 4 Compare M16 from Y - ↕ ↕ ↕ ↕

Legend:
Op Hex Operation Code (Leading '1' not shown for two-byte opcodes) EA Effective Address
~ Number of MPU Cycles (6809 emulation / native) C Value of Carry flag in CC
# Number of Program Bytes r0 First register (source) operand
I8 8-bit Immediate value r1 Second register (destination) operand
I16 16-bit Immediate value ↕ Status flag Set if TRUE, Cleared otherwise
M8 8-bit value in Memory (may also include Immediate values) - Status flag Not Affected by operation
M16 16-bit value in Memory (may also include Immediate values) Instructions in shaded rows are not available on 6809 microprocessors
 6809 / 6309 Programming Aid continued

Addressing Modes
Immediate Direct Indexed 1 Extended Inherent 5 3 2 1 0
Instr. Forms Op ~ # Op ~ # Op ~ # Op ~ # Op ~ # Description H N Z V C
COM COMA 43 2/1 1 A=A - ↕ ↕ 0 1
COMB 53 2/1 1 B=B - ↕ ↕ 0 1
COMD 043 3/2 2 D=D - ↕ ↕ 0 1
COME 143 3/2 2 E=E - ↕ ↕ 0 1
COMF 153 3/2 2 F=F - ↕ ↕ 0 1
COMW 053 3/2 2 W=W - ↕ ↕ 0 1
COM 03 6/5 2 63 6+ 2+ 73 7/6 3 M8 = M8 - ↕ ↕ 0 1
CWAI 3C 22/20 2 CC = CC & I8 ; Wait for interrupt See Note 7
DAA 19 2/1 1 Decimal Adjust A - ↕ ↕ 8 ↕
DEC DECA 4A 2/1 1 A=A-1 - ↕ ↕ ↕ -
DECB 5A 2/1 1 B=B-1 - ↕ ↕ ↕ -
DECD 04A 3/2 2 D=D-1 - ↕ ↕ ↕ -
DECE 14A 3/2 2 E=E-1 - ↕ ↕ ↕ -
DECF 15A 3/2 2 F=F-1 - ↕ ↕ ↕ -
DECW 05A 3/2 2 W=W-1 - ↕ ↕ ↕ -
DEC 0A 6/5 2 6A 6+ 2+ 7A 7/6 3 M8 = M8 - 1 - ↕ ↕ ↕ -
DIV DIVD 18D 25 3 19D 27/26 3 1AD 27+ 3+ 1BD 28/27 4 B = D ÷ M8; A = modulo See Note 12 - ↕ ↕ ↕ 9
DIVQ 18E 34 4 19E 36/35 3 1AE 36+ 3+ 1BE 37/36 4 W = Q ÷ M16; D = modulo See Note 12 - ↕ ↕ ↕ 9
EIM #I8, EA 05 6 3 65 7+ 3+ 75 7 4 M8 = M8 xor I8 - ↕ ↕ 0 -
EOR EORA 88 2 2 98 4/3 2 A8 4+ 2+ B8 5/4 3 A = A ⊕ M8 - ↕ ↕ 0 -
EORB C8 2 2 D8 4/3 2 E8 4+ 2+ F8 5/4 3 B = B ⊕ M8 - ↕ ↕ 0 -
EORD 088 5/4 4 098 7/5 3 0A8 7/6+ 3+ 0B8 8/6 4 D = D ⊕ M16 - ↕ ↕ 0 -
EORR 036 4 3 r1 = r0 ⊕ r1 See Note 2 - ↕ ↕ 0 -
EXG r0, r1 1E 8/5 2 r0 ↔ r1 See Note 2 - - - - -
INC INCA 4C 2/1 1 A=A+1 - ↕ ↕ ↕ -
INCB 5C 2/1 1 B=B+1 - ↕ ↕ ↕ -
INCD 04C 3/2 2 D=D+1 - ↕ ↕ ↕ -
INCE 14C 3/2 2 E=E+1 - ↕ ↕ ↕ -
INCF 15C 3/2 2 F=F+1 - ↕ ↕ ↕ -
INCW 05C 3/2 2 W=W+1 - ↕ ↕ ↕ -
INC 0C 6/5 2 6C 6+ 2+ 7C 7/6 3 M8 = M8 + 1 - ↕ ↕ ↕ -
JMP 0E 3/2 2 6E 3+ 2+ 7E 4/3 3 PC = Effective Address - - - - -
JSR 9D 7/6 2 AD 7/6+ 2+ BD 8/7 3 Jump to Subroutine - - - - -
LD LDA 86 2 2 96 4/3 2 A6 4+ 2+ B6 5/4 3 A = M8 - ↕ ↕ 0 -
LDB C6 2 2 D6 4/3 2 E6 4+ 2+ F6 5/4 3 B = M8 - ↕ ↕ 0 -
LDD CC 3 3 DC 5/4 2 EC 5+ 2+ FC 6/5 3 D = M16 - ↕ ↕ 0 -
LDE 186 3 3 196 5/4 3 1A6 5+ 3+ 1B6 6/5 4 E = M8 - ↕ ↕ 0 -
LDF 1C6 3 3 1D6 5/4 3 1E6 5+ 3+ 1F6 6/5 4 F = M8 - ↕ ↕ 0 -
LDMD 13D 5 3 MD = I8 - - - - -
LDQ CD 5 5 0DC 8/7 3 0EC 8+ 3+ 0FC 9/8 4 Q = M32 - ↕ ↕ 0 -
LDS 0CE 4 4 0DE 6/5 3 0EE 6+ 3+ 0FE 7/6 4 S = M16 - ↕ ↕ 0 -
LDU CE 3 3 DE 5/4 2 EE 5+ 2+ FE 6/5 3 U = M16 - ↕ ↕ 0 -
LDW 086 4 4 096 6/5 3 0A6 6+ 3+ 0B6 7/6 4 W = M16 - ↕ ↕ 0 -
LDX 8E 3 3 9E 5/4 2 AE 5+ 2+ BE 6/5 3 X = M16 - ↕ ↕ 0 -
LDY 08E 4 4 09E 6/5 3 0AE 6+ 3+ 0BE 7/6 4 Y = M16 - ↕ ↕ 0 -
LDBT 136 7/6 4 R.dstBit = M8.srcBit See Note 3
LEA LEAS 32 4+ 2+ S = Effective Address - - - - -
LEAU 33 4+ 2+ U = Effective Address - - - - -
LEAX 30 4+ 2+ X = Effective Address - - ↕ - -
LEAY 31 4+ 2+ Y = Effective Address - - ↕ - -
LSL LSLA 48 2/1 1 8 ↕ ↕ ↕ ↕

}
A
LSLB 58 2/1 1 B 8 ↕ ↕ ↕ ↕
D 0
LSLD 048 3/2 2 C bn b0 - ↕ ↕ ↕ ↕
M8
LSL 08 6/5 2 68 6+ 2+ 78 7/6 3 8 ↕ ↕ ↕ ↕
LSR LSRA 44 2/1 1 - 0 ↕ - ↕
LSRB 54 2/1 1 A - 0 ↕ - ↕
LSRD
LSRW
LSR 04 6/5 2 64 6+ 2+ 74 7/6 3
044
054
3/2
3/2
2
2
B
D
W
M8
} 0
bn b0 C
-
-
-
0
0
0
↕
↕
↕
-
-
-
↕
↕
↕

– 147 –
 6809 / 6309 Programming Aid continued

Addressing Modes
Immediate Direct Indexed 1 Extended Inherent 5 3 2 1 0
Instr. Forms Op ~ # Op ~ # Op ~ # Op ~ # Op ~ # Description H N Z V C
MUL MUL 3D 11/10 1 D = A * B (unsigned) - - ↕ - 9
MULD 18F 28 4 19F 30/29 3 1AF 30+ 3+ 1BF 31/30 4 Q = D * M16 (signed) - ↕ 6 - 0
NEG NEGA 40 2/1 1 A=A +1 8 ↕ ↕ ↕ ↕
NEGB 50 2/1 1 B=B+1 8 ↕ ↕ ↕ ↕
NEGD 040 3/2 2 D=D+1 - ↕ ↕ ↕ ↕
NEG 00 6/5 2 60 6+ 2+ 70 7/6 3 M8 = M8 + 1 8 ↕ ↕ ↕ ↕
NOP 12 2/1 1 No Operation - - - - -
OIM #I8, EA 01 6 3 61 7+ 3+ 71 7 4 M8 = M8 | I8 - ↕ ↕ 0 -
OR ORA 8A 2 2 9A 4/3 2 AA 4+ 2+ BA 5/4 3 A = A | M8 - ↕ ↕ 0 -
ORB CA 2 2 DA 4/3 2 EA 4+ 2+ FA 5/4 3 B = B | M8 - ↕ ↕ 0 -
ORCC 1A 3 2 CC = CC | I8 See Note 7
ORD 08A 5/4 4 09A 7/5 3 0AA 7/6+ 3+ 0BA 8/6 4 D = D | M16 - ↕ ↕ 0 -
ORR 035 4 3 r1 = r1 | r0 See Note 2 - ↕ ↕ 0 -
PSH PSHS 34 5/4+ 2 Push registers onto S stack See Note 4 - - - - -
PSHU 36 5/4+ 2 Push registers onto U stack See Note 4 - - - - -
PSHSW 038 6 2 Push W onto S stack - - - - -
PSHUW 03A 6 2 Push W onto U stack - - - - -
PUL PULS 35 5/4+ 2 Pull registers from S stack See Note 4 - - - - -
PULU 37 5/4+ 2 Pull registers from U stack See Note 4 - - - - -
PULSW 039 6 2 Pull W from S stack - - - - -
PULUW 03B 6 2 Pull W from U stack - - - - -
ROL ROLA 49 2/1 1 - ↕ ↕ ↕ ↕
ROLB 59 2/1 1 A - ↕ ↕ ↕ ↕
ROLD
ROLW
049
059
3/2
3/2
2
2
B
D
W
M8
} C bn b0
-
-
↕
↕
↕
↕
↕
↕
↕
↕
ROL 09 6/5 2 69 6+ 2+ 79 7/6 3 - ↕ ↕ ↕ ↕
ROR RORA 46 2/1 1 - ↕ ↕ - ↕
RORB 56 2/1 1 A - ↕ ↕ - ↕
RORD
RORW
046
056
3/2
3/2
2
2
B
D
W
M8
} C bn b0
-
-
↕
↕
↕
↕
-
-
↕
↕
ROR 06 6/5 2 66 6+ 2+ 76 7/6 3 - ↕ ↕ - ↕
RTI 3B 15/17 1 Return from Interrupt (when CC.E = 1) See Note 7
3B 6 1 Return from Interrupt (when CC.E = 0) See Note 7
RTS 39 5/4 1 Return from Subroutine - - - - -
SBC SBCA 82 2 2 92 4/3 2 A2 4+ 2+ B2 5/4 3 A = A - M8 - C 8 ↕ ↕ ↕ ↕
SBCB C2 2 2 D2 4/3 2 E2 4+ 2+ F2 5/4 3 B = B - M8 - C 8 ↕ ↕ ↕ ↕
SBCD 082 5/4 4 092 7/5 3 0A2 7/6+ 3+ 0B2 8/6 4 D = D - M16 - C - ↕ ↕ ↕ ↕
SBCR 033 4 3 r1 = r1 - r0 - C See Note 2 - ↕ ↕ ↕ ↕
SEX SEX 1D 2/1 1 Sign Extend B into A - ↕ ↕ - -
SEXW 14 4 1 Sign Extend W into D - ↕ ↕ - -
ST STA 97 4/3 2 A7 4+ 2+ B7 5/4 3 M8 = A - ↕ ↕ 0 -
STB D7 4/3 2 E7 4+ 2+ F7 5/4 3 M8 = B - ↕ ↕ 0 -
STD DD 5/4 2 ED 5+ 2+ FD 6/5 3 M16 = D - ↕ ↕ 0 -
STE 197 5/4 3 1A7 5+ 3+ 1B7 6/5 4 M8 = E - ↕ ↕ 0 -
STF 1D7 5/4 3 1E7 5+ 3+ 1F7 6/5 4 M8 = F - ↕ ↕ 0 -
STQ 0DD 8/7 3 0ED 8+ 3+ 0FD 9/8 4 M32 = Q - ↕ ↕ 0 -
STS 0DF 6/5 3 0EF 6+ 3+ 0FF 7/6 4 M16 = S - ↕ ↕ 0 -
STU DF 5/4 2 EF 5+ 2+ FF 6/5 3 M16 = U - ↕ ↕ 0 -
STW 097 6/5 3 0A7 6+ 3+ 0B7 7/6 4 M16 = W - ↕ ↕ 0 -
STX 9F 5/4 2 AF 5+ 2+ BF 6/5 3 M16 = X - ↕ ↕ 0 -
STY 09F 6/5 3 0AF 6+ 3+ 0BF 7/6 4 M16 = Y - ↕ ↕ 0 -
STBT 137 8/7 4 M8.dstBit = R.srcBit - ↕ ↕ - -
SUB SUBA 80 2 2 90 4/3 2 A0 4+ 2+ B0 5/4 3 A = A - M8 8 ↕ ↕ ↕ ↕
SUBB C0 2 2 D0 4/3 2 E0 4+ 2+ F0 5/4 3 B = B - M8 8 ↕ ↕ ↕ ↕
SUBD 83 4/3 3 93 6/4 2 A3 6/5+ 2+ B3 7/5 3 D = D - M16 - ↕ ↕ ↕ ↕
SUBE 180 3 3 190 5/4 3 1A0 5+ 3+ 1B0 6/5 4 E = E - M8 8 ↕ ↕ ↕ ↕
SUBF 1C0 3 3 1D0 5/4 3 1E0 5+ 3+ 1F0 6/5 4 F = F - M8 8 ↕ ↕ ↕ ↕
SUBR 032 4 3 r1 = r1 - r0 See Note 2 - ↕ ↕ ↕ ↕
SUBW 080 5/4 4 090 7/5 3 0A0 7/6+ 3+ 0B0 8/6 4 W = W - M16 - ↕ ↕ ↕ ↕

– 148 –
 6809 / 6309 Programming Aid continued

Addressing Modes
Immediate Direct Indexed 1 Extended Inherent 5 3 2 1 0
Instr. Forms Op ~ # Op ~ # Op ~ # Op ~ # Op ~ # Description H N Z V C
SWI SWI 3F 19 / 21 1 Software Interrupt 1 See Note 5 - - - - -
SWI2 03F 20 / 22 2 Software Interrupt 2 See Note 5 - - - - -
SWI3 13F 20 / 22 2 Software Interrupt 3 See Note 5 - - - - -
SYNC 13 ≥ 4 / ≥ 3 1 Synchronize to Interrupt - - - - -
TFM r0+, r1+ 138 6+3n 3 Block Move Incrementing See Note 10 - - 1 - -
r0-, r1- 139 6+3n 3 Block Move Decrementing See Note 10 - - 1 - -
r0+, r1 13A 6+3n 3 Block Write to address See Note 10 - - 1 - -
r0, r1+ 13B 6+3n 3 Block Read from address See Note 10 - - 1 - -
TFR r0, r1 1F 6/4 2 r1 = r0 See Note 2 - - - - -
TIM #I8, EA 0B 6 3 6B 7+ 3+ 7B 7 4 Bit Test Memory (I8 & M8) - ↕ ↕ 0 -
TST TSTA 4D 2/1 1 Test A - ↕ ↕ 0 -
TSTB 5D 2/1 1 Test B - ↕ ↕ 0 -
TSTD 04D 3/2 2 Test D - ↕ ↕ 0 -
TSTE 14D 3/2 2 Test E - ↕ ↕ 0 -
TSTF 15D 3/2 2 Test F - ↕ ↕ 0 -
TSTW 05D 3/2 2 Test W - ↕ ↕ 0 -
TST 0D 6/4 2 6D 6/5+ 2+ 7D 7/5 3 Test M8 - ↕ ↕ 0 -

Relative Relative
Addressing Addressing
Instr. Forms Op ~ # Description Instr. Forms Op ~ # Description
BCC BCC 24 3 2 Branch If C = 0 BLT BLT 2D 3 2 Branch If < 0
LBCC 024 5 (6) 4 Long Branch If C = 0 (11) LBLT 02D 5 (6) 4 Long Branch If < 0 (11)
BCS BCS 25 3 2 Branch If C = 1 BMI BMI 2B 3 2 Branch If N = 1
LBCS 025 5 (6) 4 Long Branch If C = 1 (11) LBMI 02B 5 (6) 4 Long Branch If N = 1 (11)
BEQ BEQ 27 3 2 Branch If Z = 1 BNE BNE 26 3 2 Branch If Z = 0
LBEQ 027 5 (6) 4 Long Branch If Z = 1 (11) LBNE 026 5 (6) 4 Long Branch If Z = 0 (11)
BGE BGE 2C 3 2 Branch If ≥ 0 BPL BPL 2A 3 2 Branch If N = 0
LBGE 02C 5 (6) 4 Long Branch If ≥ 0 (11) LBPL 02A 5 (6) 4 Long Branch If N = 0 (11)
BGT BGT 2E 3 2 Branch If > 0 BRA BRA 20 3 2 Branch unconditionally
LBGT 02E 5 (6) 4 Long Branch If > 0 (11) LBRA 16 5/4 3 Long Branch unconditionally
BHI BHI 22 3 2 Branch If higher BRN BRN 21 3 2 Branch never (no-op)
LBHI 022 5 (6) 4 Long Branch If higher (11) LBRN 021 5 4 Long Branch never (no-op)
BHS BHS 24 3 2 Branch If higher or same BSR BSR 8D 7/6 2 Branch to subroutine
LBHS 024 5 (6) 4 Long Branch If higher or same (11) LBSR 17 9/7 3 Long Branch to subroutine
BLE BLE 2F 3 2 Branch If ≤ 0 BVC BVC 28 3 2 Branch If V = 0
LBLE 02F 5 (6) 4 Long Branch If ≤ 0 (11) LBVC 028 5 (6) 4 Long Branch If V = 0 (11)
BLO BLO 25 3 2 Branch If lower BVS BVS 29 3 2 Branch If V = 1
LBLO 025 5 (6) 4 Long Branch If lower (11) LBVS 029 5 (6) 4 Long Branch If V = 1 (11)
BLS BLS 23 3 2 Branch If lower or same
LBLS 023 5 (6) 4 Long Branch If lower or same (11)

Notes:
1. The Indexed column provides base values for the MPU cycles and byte counts. To obtain totals, add the values from the Indexed Addressing Mode Table on page 150.
2. r0 and r1 may be any pair of 8-bit registers, or any pair of 16-bit registers. Mixing registers of different sizes (TFR, EXG) behaves differently on the 6309 than on the
6809. The ZERO register (6309 only) may be used in combination with any other register. Undefined register codes produce a value of FF or FFFF on the 6809.
3. The bit manipulation instructions (other than STBT) do not affect the CC register unless it is specified as the target register, in which case only the destination bit may
be affected. Target registers for the bit manipulation instructions are limited to A, B and CC.
4. The PSH and PUL instructions require one additional cycle for each byte pushed or pulled.
5. SWI sets the I and F flags in CC. SWI2 and SWI3 do not affect I and F.
6. The MULD instruction sets the Z flag in CC when the high-order word (D) is zero, even if the low-order word (W) is non-zero.
7. The CC register is set as a direct result of the instruction.
8. Value of the Condition Code bit is undefined.
9. Special cases: For MUL, Carry set only if bit 7 is 1. For DIVD and DIVQ, Carry is set only if bit 0 is 1
10. Source and destination registers for the TFM instruction are limited to X, Y, U, S and D. The W register always specifies the byte count. TFM is the only instruction that
can be interrupted before it completes.
11. Conditional long branches require a 6th cycle if the branch is taken (6809 only).
12. The DIV instructions perform signed division. DIVD executes in l fewer cycle if a two's-complement overflow occurs. If a Range error occurs then the destination
registers are not modified, the instruction executes in fewer cycles (13 fewer for DIVD, 21 fewer for DIVQ), the V flag is set and the N, Z and C flags are cleared.

– 149 –
 Indexed Addressing Mode Table
Non Indirect Indirect
Assembler Postbyte + + Assembler Postbyte + +
Type Forms Form Opcode ~ # Form Opcode ~ #
Constant Offset From R No offset ,R 1RR00100 0 0 [,R] 1RR10100 3 0
(twos complement offset) 5 bit offset (-16 to +15 ) n,R 0RRnnnnn 1 0 not available - use 8-bit
8 bit offset (-128 to +127 ) n,R 1RR01000 1 1 [n,R] 1RR11000 4 1
16 bit offset (-32768 to +32767) n,R 1RR01001 4/3 2 [n,R] 1RR11001 7 / 6 2
Constant Offset From W No offset ,W 10001111 0 0 [,W] 10010000 3 0
(twos complement offset) 16 bit offset n,W 10101111 2 2 [n,W] 10110000 5 2
Accumulator Offset From R A - Accumulator offset A,R 1RR00110 1 0 [A,R] 1RR10110 4 0
(twos complement offset) B - Accumulator offset B,R 1RR00101 1 0 [B,R] 1RR10101 4 0
D - Accumulator offset D,R 1RR01011 4/2 0 [D,R] 1RR11011 7 / 5 0
E - Accumulator offset E,R 1RR00111 1 0 [E,R] 1RR10111 4 0
F - Accumulator offset F,R 1RR01010 1 0 [F,R] 1RR11010 4 0
W - Accumulator offset W,R 1RR01110 1 0 [W,R] 1RR11110 4 0
Auto Increment/Decrement of R Post-Increment by 1 ,R+ 1RR00000 2/1 0 not allowed
Post-Increment by 2 ,R++ 1RR00001 3/2 0 [,R++] 1RR10001 6 / 5 0
Pre-Decrement by 1 ,-R 1RR00010 2/1 0 not allowed
Pre-Decrement by 2 ,--R 1RR00011 3/2 0 [,--R] 1RR10011 6 / 5 0
Auto Increment/Decrement of W Post-Increment by 2 ,W++ 11001111 1 0 [,W++] 11010000 4 0
Pre-Decrement by 2 ,--W 11101111 1 0 [,--W] 11110000 4 0
Constant Offset From PC 8 bit offset (-128 to +127 ) n,PCR 1XX01100 1 1 [n,PCR] 1XX11100 4 1
(twos complement offset) 16 bit offset (-32768 to +32767) n,PCR 1XX01101 5/3 2 [n,PCR] 1XX11101 8 / 6 2
Extended Indirect 16 bit address [n] 10011111 5 / 4 2

RR Register XX = Don't Care + and + these columns indicate the additional

00 X ~ # number of MPU cycles and program bytes
01 Y for the particular variation.
10 U
11 S Indexing modes in shaded rows are not available on 6809 microprocessors.

Inter-Register Postbyte Bit-Manipulation Postbyte (6309 only)

b7 b4 b3 b0 b7 b6 b5 b3 b2 b0

Destination Bit Number (0 - 7)

Source Register (r0) Source Bit Number (0 - 7)
Destination Register (r1) Target Register

Code Register Code Register Code Register

0000 D 1000 A 00 CC
0001 X 1001 B 01 A
0010 Y 1010 CC 10 B
0011 U 1011 DP 11 Invalid
0100 S 1100 0
0101 PC 1101 0
0110 W 1110 E
0111 V 1111 F

On 6809 microprocessors, the shaded Register Codes

produce a value of FF or FFFF (all bits set).

– 150 –
 Programming Model

Accumulator A Accumulator B Accumulator E Accumulator F

Accumulator D Accumulator W
Accumulator Q
Index Register X
CC Register Bits
Index Register Y
E Entire register state stacked
F FIRQ interrupt masked User Stack Pointer U
H Half-Carry
I IRQ interrupt masked
System Stack Pointer S
N Negative result (twos complement) Program Counter PC
Z Zero result
Transfer Value Register V
V Overflow
C Carry (or borrow) Zero Register 0
MD Register Bits Direct Page Register DP
/0 Divide-by-zero Exception Condition Codes Register CC E F H I N Z V C
IL Illegal Instruction Exception
FM FIRQ uses IRQ stacking method (Entire state) Mode Register MD /0 IL FM NM
NM Native Mode (reduced cycles, W stacked on interrupts) b7 b0

The /0 and IL bits of the MD register can only be read once after an error exception occurs. They are reset to 0 after executing a BITMD
instruction. The FM and NM bits of the MD register are write-only. Using the BITMD instruction to test these bits always produces zero.

Register Stacking Order

Lower Memory Addresses

CC
Pull Order

Stack Ptr after stacking

A PSH / PUL Postbyte
B b7 b6 b5 b4 b3 b2 b1 b0
Stacked on Interrupts only
when the NM bit is set in MD.
6309 Only.
} E
F
CC
A
DP B
X.H DP
X.L X
Y.H Y
U/S
Y.L
PC
U/S . H
U/S . L
Push Order

PC . H
PC . L
Stack Ptr before stacking
Higher Memory Addresses

When the FM bit in the MD register is set, the Entire register set is stacked upon an FIRQ interrupt, otherwise only CC and PC are stacked.
The Transfer Value register V is never stacked upon interrupts. No instructions are provided to directly push or pull the V register.
The E and F accumulators are stacked upon interrupts only if the NM bit is set in the MD register.
The PSHS, PULS, PSHU and PULU instructions do not permit the E and F accumulators (W) to be specified. These registers can be pushed and
pulled together using the PSHSW, PSHUW, PULSW and PULUW instructions, or individually using the Auto Increment/Decrement Indexing
modes with STE, STF, LDE, LDF (although these will have an effect on the Condition Codes).

– 151 –
 6809 / 6309 Opcode Map
DIRECT REL A/D/E B/W/F INDEX EXTND IMMED DIRECT INDEX EXTND IMMED DIRECT INDEX EXTND
$0_ $1_ $2_ $3_ $4_ $5_ $6_ $7_ $8_ $9_ $A_ $B_ $C_ $D_ $E_ $F_
_0 NEG PAGE 2 BRA LEAX NEGA NEGB NEG NEG SUBA SUBA SUBA SUBA SUBB SUBB SUBB SUBB
$10 _0 ADDR NEGD SUBW SUBW SUBW SUBW
$11 _0 BAND SUBE SUBE SUBE SUBE SUBF SUBF SUBF SUBF
_1 OIM PAGE 3 BRN LEAY OIM OIM CMPA CMPA CMPA CMPA CMPB CMPB CMPB CMPB
$10 _1 LBRN ADCR CMPW CMPW CMPW CMPW
$11 _1 BIAND CMPE CMPE CMPE CMPE CMPF CMPF CMPF CMPF
_2 AIM NOP BHI LEAS AIM AIM SBCA SBCA SBCA SBCA SBCB SBCB SBCB SBCB
$10 _2 LBHI SUBR SBCD SBCD SBCD SBCD
$11 _2 BOR
_3 COM SYNC BLS LEAU COMA COMB COM COM SUBD SUBD SUBD SUBD ADDD ADDD ADDD ADDD
$10 _3 LBLS SBCR COMD COMW CMPD CMPD CMPD CMPD
$11 _3 BIOR COME COMF CMPU CMPU CMPU CMPU
_4 LSR SEXW BHS/CC PSHS LSRA LSRB LSR LSR ANDA ANDA ANDA ANDA ANDB ANDB ANDB ANDB
$10 _4 LBHS/CC ANDR LSRD LSRW ANDD ANDD ANDD ANDD
$11 _4 BEOR
_5 EIM BLO/CS PULS EIM EIM BITA BITA BITA BITA BITB BITB BITB BITB
$10 _5 LBLO/CS ORR BITD BITD BITD BITD
$11 _5 BIEOR
_6 ROR LBRA BNE PSHU RORA RORB ROR ROR LDA LDA LDA LDA LDB LDB LDB LDB
$10 _6 LBNE EORR RORD RORW LDW LDW LDW LDW
$11 _6 LDBT LDE LDE LDE LDE LDF LDF LDF LDF
_7 ASR LBSR BEQ PULU ASRA ASRB ASR ASR STA STA STA STB STB STB
$10 _7 LBEQ CMPR ASRD STW STW STW
$11 _7 STBT STE STE STE STF STF STF
_8 LSL BVC LSLA LSLB LSL LSL EORA EORA EORA EORA EORB EORB EORB EORB
$10 _8 LBVC PSHSW LSLD EORD EORD EORD EORD
$11 _8 TFM r+,r+

_9 ROL DAA BVS RTS ROLA ROLB ROL ROL ADCA ADCA ADCA ADCA ADCB ADCB ADCB ADCB
$10 _9 LBVS PULSW ROLD ROLW ADCD ADCD ADCD ADCD
$11 _9 TFM r-,r-

_A DEC ORCC BPL ABX DECA DECB DEC DEC ORA ORA ORA ORA ORB ORB ORB ORB
$10 _A LPBL PSHUW DECD DECW ORD ORD ORD ORD
$11 _A TFM r+,r DECE DECF
_B TIM BMI RTI TIM TIM ADDA ADDA ADDA ADDA ADDB ADDB ADDB ADDB
$10 _B LBMI PULUW ADDW ADDW ADDW ADDW
$11 _B TFM r ,r+ ADDE ADDE ADDE ADDE ADDF ADDF ADDF ADDF
_C INC ANDCC BGE CWAI INCA INCB INC INC CMPX CMPX CMPX CMPX LDD LDD LDD LDD
$10 _C LBGE INCD INCW CMPY CMPY CMPY CMPY LDQ LDQ LDQ
$11 _C BITMD INCE INCF CMPS CMPS CMPS CMPS
_D TST SEX BLT MUL TSTA TSTB TST TST BSR JSR JSR JSR LDQ STD STD STD
$10 _D LBLT TSTD TSTW STQ STQ STQ
$11 _D LDMD TSTE TSTF DIVD DIVD DIVD DIVD
_E JMP EXG BGT JMP JMP LDX LDX LDX LDX LDU LDU LDU LDU
$10 _E LBGT LDY LDY LDY LDY LDS LDS LDS LDS
$11 _E DIVQ DIVQ DIVQ DIVQ
_F CLR TFR BLE SWI CLRA CLRB CLR CLR STX STX STX STU STU STU
$10 _F LBLE SWI2 CLRD CLRW STY STY STY STS STS STS
$11 _F SWI3 CLRE CLRF MULD MULD MULD MULD

Shaded Instructions are available on 6309 microprocessors only Undefined opcodes generate an Illegal Instruction exception on the 6309 only.
 6809 Undefined Opcode Behavior
Unlike the 6309 microprocessor, the 6809 does not trap illegal instructions. This section describes the behavior of the 6809 when it executes
an undefined opcode. In most cases, the CPU behaves as if it had executed the instruction whose opcode value is either one less or one more
than that of the undefined opcode. The Opcode Map and notes shown below describe the specific behavior of each undefined opcode. The
same behavior will result when an undefined opcode is preceded by a Page 2 ($10) or Page 3 ($11) selector, except that 1 additional MPU
cycle is consumed.

DIRECT REL ACC. A ACC. B INDEX EXTND IMMED DIRECT INDEX EXTND IMMED DIRECT INDEX EXTND
$0_ $1_ $2_ $3_ $4_ $5_ $6_ $7_ $8_ $9_ $A_ $B_ $C_ $D_ $E_ $F_
_0 LBRA4
_1 NEG NEGA NEGB NEG NEG
_2 NEG/ NEGA/ NEGB/ NEG/ NEG/
COM1 COMA1 COMB1 COM1 COM1
_3
_4 HCF2
_5 LSR HCF2 LSRA LSRB LSR LSR

_6
_7 6 6
_8 3 ANDCC 5

_9
_A
_B DEC NOP DECA DECB DEC DEC
_C
_D HCF2
_E RESET7 CLRA CLRB

_F 8 8

1. Undefined opcodes in row 2 execute as a NEG instruction when the Carry bit in CC is 0, and as a COM instruction when the Carry bit is 1.
2. Opcodes $14, $15 and $CD all cause the CPU to stop functioning normally. One or more of these may be the HCF (Halt and Catch Fire) instruction.
The HCF instruction was provided for manufacturing test purposes. Its causes the CPU to halt execution and enter a mode in which the Address lines
are incrementally strobed.
3. Opcode $18 affects only the Condition Codes register (CC). The value in the Overflow bit (V) is shifted into the Zero bit (Z) while the value in the IRQ
Mask bit (I) is shifted into the Half Carry bit (H). All other bits in the CC register are cleared. Execution of this opcode takes 3 MPU cycles.
4. The 6809 will execute opcode $20 as an LBRA when it is preceded by a Page 2 selector ($10). The 6309 considers this an illegal instruction.
5. Opcode $38 behaves just like the ANDCC instruction ($1C), except for the fact that it uses 1 additional MPU cycle (for a total of 4).
6. Opcodes $87 and $C7 read and discard an 8-bit Immediate operand which follows the opcode. The value of the immediate byte is irrelevant. The
Negative bit (N) in the CC register is always set, while the Zero (Z) and Overflow (V) bits are always cleared. No other bits in the Condition Codes
register are affected. Each of these opcodes execute in 2 MPU cycles.
7. Opcode $3E is similar to the SWI instruction. It stacks the Entire register state, sets the I and F bits in the Condition Codes register and then loads the
PC register with an address obtained from the RESET vector ($FFFE:F). This could potentially be used as a fourth Software Interrupt instruction, so
long as the code invoked by the Reset vector is able to differentiate between a software reset and a hardware reset. It does NOT set the Entire bit (E) in
the CC register prior to stacking the register state. This could cause an RTI instruction for a Reset handler to fail to operate as expected. This opcode
uses the same number of MPU cycles as SWI (15).
8. Opcodes $8F and $CF are STX Immediate and STU Immediate respectively. These instructions are partially functional. Two bytes of immediate data
follow the opcode. The first immediate byte is read and discarded by the instruction. The lower half (LSB) of the X or U register is then written into the
second immediate byte. The Negative bit (N) in the CC register is always set, while the Zero (Z) and Overflow (V) bits are always cleared. No other
bits in the Condition Codes register are affected. Each of these opcodes execute in 3 MPU cycles.

NOTE:
This information was obtained through experimentation and may not be completely accurate. No information about how the 6809 operates when undefined opcodes are
executed was ever published by Motorola.

– 153 –