IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 24, NO.

4, APRIL 2016 1603

An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder

Abstract— Memories that operate in harsh environments, like for In recent years, the number of errors that affect more than one
example space, suffer a significant number of errors. The error correction memory cell has increased significantly. This is due to the scaling
codes (ECCs) are routinely used to ensure that those errors do not cause
of the memory cells and is projected to grow further [5]. These
data corruption. However, ECCs introduce overheads both in terms of
memory bits and decoding time that limit speed. In particular, this is an errors, known as multiple cell upsets (MCUs), pose a challenge
issue for applications that require strong error correction capabilities. for SEC–DED codes. One solution to ensure that the MCU errors
A number of recent works have proposed advanced ECCs, such as can be corrected is to interleave the bits of different logical words
orthogonal Latin squares or difference set codes that can be decoded so that an MCU affects one bit per word [6]. This is based on
with relatively low delay. The price paid for the low decoding time is
that in most cases, the codes are not optimal in terms of memory overhead the observation that the cells affected by an MCU are physically
and require more parity check bits. On the other hand, codes like the close [7]. Interleaving, however, has a cost as it complicates the
(24,12) Golay code that minimize the number of parity check bits have memory design [8]. In some space applications, there is an additional
a more complex decoding. A compromise solution has been recently issue as the number of errors is high, and SEC–DED codes may not
explored for Bose–Chaudhuri–Hocquenghem codes. The idea is to imple-
ment a fast parallel decoder to correct the most common error patterns
be sufficient when errors accumulate over time [9]. These issues have
(single and double adjacent) and use a slower serial decoder for the led to an increased interest on the use of more advanced ECCs to
rest of the patterns. In this brief, it is shown that the same scheme can protect SRAM memories.
be efficiently implemented for the (24,12) Golay code. In this case, the As MCUs affect cells that are close together, a number of codes
properties of the Golay code can be exploited to implement a parallel that can correct double-adjacent or triple-adjacent errors have been
decoder that corrects single- and double-adjacent errors that is faster
and simpler than a single-error correction decoder. The evaluation results recently proposed [8], [10]–[12]. These codes, in many cases, do not
using a 65-nm library show significant reductions in area, power, and require additional parity check bits and in the rest require only one or
delay compared with the traditional decoder that can correct single and two additional bits. The decoding complexity increases but in many
double-adjacent errors. In addition, the proposed decoder is also able cases can still be implemented with limited impact on the memory
to correct some triple-adjacent errors, thus covering the most common
error patterns. speed. These codes are useful for applications in which the error rate
is low, however, when the error rate is large, codes that can correct
Index Terms— Double adjacent error correction (DAEC), error errors on multiple independent bits are needed [9].
correction codes (ECCs), Golay code, memory, single error Research for multibit ECCs has focused on reducing the decoding
correction (SEC), triple-adjacent error correction. latency as in many cases, the traditional decoders are serial and
require several clock cycles. To some extent this can be done for
I. I NTRODUCTION some traditional ECCs by using a parallel syndrome decoder [13] but
the decoder complexity explodes as the error correction capability or
Harsh environments, like space, are a challenge for electronic the word size increases. Another approach is to use codes that can
circuits in general and for memories in particular. For example, be decoded with low delay, such as orthogonal Latin squares (OLSs)
radiation causes several types of errors that can disrupt the circuit or difference set (DS) codes [14], [15]. In the case of OLS codes,
functionality [1]. One common error for SRAM memories is soft the main issue is that they are not optimal in terms of the number
errors that change the value of one or more memory cells [2]. of parity check bits and thus require more memory overhead. The
To avoid corruption in the data stored in the memory, error correction DS codes are more competitive in terms of parity check bits but are
codes (ECCs) are commonly used [3]. still not optimal for some word lengths. For example, the
ECCs add parity check bits to each memory word to detect and (21, 10) DS code can correct 2-bit errors while a code with a similar
correct errors. This requires an encoder to compute those bits when block size and code rate, and the (24,12) extended Golay code [16]
writing to the memory and a decoder to detect and correct errors can correct 3-bit errors. However, the Golay code requires a more
when reading from the memory. These elements increase the memory complex decoder that needs several clock cycles [17].
area and the power consumption, and can also reduce the access Namba et al. [18] have proposed a compromise solution for
speed. These overheads increase with the error correction capability Bose–Chaudhuri–Hocquenghem codes. The idea is that the most
of the ECC. Traditionally, codes that can correct a single bit error common error patterns are decoded in parallel and the rest serially.
per word have been used. In particular, single error correction–double In particular, single and double-adjacent errors are corrected in a
error detection (SEC–DED) codes that can also detect double errors single clock cycle. This means that the most memory accesses can
are commonly used [4]. be completed in a single clock cycle, and only a small percentage of
the words in error require a full serial decoding. This can enable the
Manuscript received May 4, 2015; revised July 8, 2015; accepted
August 5, 2015. Date of publication August 20, 2015; date of current version use of traditional ECCs that do not support fast parallel decoding to
March 18, 2016. protect SRAM memories.
P. Reviriego and J. A. Maestro are with the Universidad Antonio de Nebrija, In this brief, the use of the scheme in [18] is considered for the
Madrid 28040, Spain (e-mail: [email protected]; [email protected]). (24,12) Golay code. In more detail, an efficient parallel decoder capa-
S. Liu and L. Xiao are with the Microelectronics Center, Harbin
Institute of Technology, Harbin 150001, China (e-mail: [email protected];
ble of correcting the single and double-adjacent errors is presented.
[email protected]). The decoder exploits the properties of the Golay code to reduce the
Digital Object Identifier 10.1109/TVLSI.2015.2465846 implementation cost. This results in a decoder that is simpler than a
1063-8210 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
1604 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 24, NO. 4, APRIL 2016

Fig. 1. Parity check matrix of the (24,12) Golay code.

Fig. 2. Parity check matrix of the (24,12) Golay code with the proposed bit placement.

traditional SEC decoder but that can also correct all double-adjacent The requirement for SEC is that the columns must be different.
errors and some triple-adjacent errors. The proposed decoder has been Therefore, it would seem possible to use a subset of the parity
implemented in hardware description language and mapped to a 65- bits to decode single errors. However, since the code can correct
nm technology to show its benefits. The main contribution of this three errors, we need to ensure that the single-error parallel decoder
brief is to enable a fast and efficient parallel correction of the single does not introduce erroneous corrections in the presence of multiple
and double-adjacent errors in the (24,12) Golay code. bit errors. For example, if we use an SEC-DAEC code with a
The rest of this brief is organized as follows. Section II provides minimum distance of four, a triple error can cause a miscorrection
an introduction to the (24,12) Golay code. The proposed decoder is in the SEC-DAEC decoding phase. A 4-bit error may not be even
presented in Section III. The evaluation results are summarized and detected by the SEC-DAEC decoder. Therefore, the full syndrome is
discussed in Section IV. Finally, this brief ends with the conclusions used for comparisons in all the cases to ensure that triple errors do
in Section V. not trigger miscorrections and 4-bit errors are detected.

II. (24,12) E XTENDED G OLAY C ODE III. P ROPOSED SEC-DAEC PARALLEL D ECODER
The (24,12) extended Golay code is obtained by adding an overall The existing SEC-DAEC decoders are similar to SEC decoders but
parity check bit to the (23, 12) Golay code [16]. This code is they need to check also the syndrome values that correspond double-
a perfect code with a minimum distance of seven and has been adjacent errors [10]. This requires roughly doubling the number of
widely studied [19]. The extended code has a minimum distance of comparisons. Then, the correction of each bit is triggered by three
eight, and therefore can correct 3-bit errors and detect 4-bit errors. syndrome values (the single bit and the two double adjacent). This
It has been used in many applications including space missions that results in a decoder that is significantly more complex than a simple
require strong error correction capabilities [19]. The decoding of SEC decoder.
the Golay code is done in a series of steps [17], [20] and requires The proposed parallel decoder as discussed before has the objective
several clock cycles. For example, 27 clock cycles are needed in the of correcting single and double-adjacent bit errors. The first step is
implementation presented in [17]. This, as discussed before, is not to place the bits in the memory such that data and parity bits are
suitable for SRAM protection. To the best of our knowledge, interleaved, as shown in Fig. 2. This interleaving has no impact on
no SEC-DAEC parallel decoder optimized for the Golay code has memory performance, as it is a simple remapping of the bits when
been proposed in the literature. they are read from or written to the memory.
The parity check matrix of the (24,12) Golay code is shown Let us now consider the syndrome values for an error on the
in Fig. 1. The 12 first bits correspond to the parity check bits and second bit (first data bit), a double adjacent on bits one and two,
last 12 to the data bits. A single-error correcting parallel decoder a double adjacent on bits two and three, and a triple adjacent on bits
can be implemented by computing the syndrome and comparing one, two, and three. In all those cases, bit two should be corrected.
in parallel with the 12 data bit and the 12 check bit columns. The syndrome values for those error patterns are shown in Fig. 3.
When there is a match that bit is corrected [4]. The interesting observation is that the first two rows are the only ones
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 24, NO. 4, APRIL 2016 1605

TABLE II
D ECODER A REA (µm2 )

TABLE III
D ECODER D ELAY (ns)

Fig. 3. Example of syndrome values for errors that affect the first data bit
in the proposed bit placement.

TABLE IV
TABLE I D ECODER P OWER (mW)
N UMBER OF C OMPARATORS R EQUIRED FOR THE D ECODER

IV. E VALUATION
that change from one pattern to another and that the values cover the The proposed parallel SEC-DAEC decoder has been implemented
four possible combinations of the first two bits. This means that the in HDL and mapped to a TSMC 65-nm technology library using
decoding can be done by simply comparing the remaining ten bits Synopsys Design Compiler. The traditional SEC and SEC-DAEC
with the last ten bits of the syndrome. If they match, then the second decoders have also been implemented to show the benefits of the
bit (first data bit) has to be corrected. It can be observed that the same new decoder.
reasoning applies to the rest of the data bits, except the last one. For The synthesis was done twice, one with maximum effort to reduce
the last bit, there are only two values to check (single and double area and another with maximum effort to reduce delay. The first one
adjacent with bit 23). In this case, it is easy to see that this can be shows the benefits in area when delay is not an issue, and the second
done by checking the first 11 bits only. shows the maximum speed that can be achieved by the decoder.
The previous discussion shows how parallel decoding can be The results for decoder area, delay, and power are shown
efficiently implemented. In fact, the proposed parallel decoder will in Tables II–IV. It can be observed that optimizing for delay leads,
be simpler than an SEC decoder. Table I summarizes the comparators in all cases, to a large increase in circuit area and power. The
needed for each of the different decoders. A comparator is needed for proposed SEC-DAEC decoder requires a less circuit area than both
each syndrome value that triggers a correction. For an SEC code, this the traditional SEC-DAEC decoder and an SEC decoder. In the case
is simply 24 while for a traditional SEC-DAEC code is 47. In the case of the area optimized synthesis, the reductions are over 45% and 11%,
of the proposed decoder, 12 comparators cover both single bit errors respectively. This clearly confirms that the proposed SEC-DAEC
on the data bits and double adjacent bit errors, and another 12 are decoder is much simpler than the traditional SEC-DAEC decoder and
needed to cover single errors on the check bits giving a total of 24. more interestingly, and is also simpler than the SEC decoder. In terms
It can be observed that the proposed decoder needs less comparator of delay, the proposed decoder is also faster than both the traditional
and also less bits in some of them. Both factors help to reduce the SEC-DAEC decoder and an SEC decoder. For the delay optimized
decoder complexity. In Section IV, the benefits will be evaluated for synthesis, the reductions are 28% and 21% compared with the
a design mapped to a 65-nm technology. traditional SEC-DAEC decoder and the SEC decoder, respectively.
The proposed parallel decoder also has to detect errors that it Finally, the power consumption is significantly smaller than for the
cannot correct. In those cases, the serial decoder must be used to traditional SEC-DAEC decoder and similar to that of the SEC decoder
correct the error. The logic needed to detect those errors is simply (slightly lower for area optimized and slightly larger for the delay-
a check for a no zero syndrome and a check that none of the optimized synthesis).
comparators has detected a match. The first part can be implemented In summary, the evaluation for a commercial library confirms that
with a 12-input OR gate and the second with another 24-input the proposed SEC-DAEC parallel decoder reduces significantly the
OR gate.
cost of implementing DAEC compared with the traditional
It should be noted that the same idea can be partly applied to other SEC-DAEC decoder. In fact, the area and delay are also lower than
triple ECCs even if the number of parity check and data bits is not for a parallel SEC decoder.
the same. In more detail, when there are more data bits, the first
data bits can also be interleaved with parity bits and decoded with V. C ONCLUSION
the proposed scheme, while for the rest, a traditional SEC-DAEC In this brief, a single and double-adjacent error correcting parallel
decoding can be used. The application of the proposed scheme to decoder for the (24,12) extended Golay code has been proposed.
other codes is left for future work. The decoder uses the properties of the code to achieve an efficient
1606 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 24, NO. 4, APRIL 2016

implementation. In fact, the proposed decoder is not only much [8] A. Neale and M. Sachdev, “A new SEC-DED error correction code
simpler than a traditional SEC-DAEC decoder, but also simpler than subclass for adjacent MBU tolerance in embedded memory,” IEEE
Trans. Device Mater. Rel., vol. 13, no. 1, pp. 223–230, Mar. 2013.
a standard SEC decoder for the Golay code. To evaluate the benefits
[9] M. A. Bajura et al., “Models and algorithmic limits for an ECC-based
of the new decoder, it has been implemented in HDL and mapped to a approach to hardening sub-100-nm SRAMs,” IEEE Trans. Nucl. Sci.,
65-nm library. The results confirm that significant reductions in area, vol. 54, no. 4, pp. 935–945, Aug. 2007.
delay, and power consumption can be obtained compared with the [10] A. Dutta and N. A. Touba, “Multiple bit upset tolerant memory using a
traditional SEC-DAEC decoder. selective cycle avoidance based SEC-DED-DAEC code,” in Proc. IEEE
VLSI Test Symp., May 2007, pp. 349–354.
The new SEC-DAEC parallel decoder can be used in conjunction [11] Z. Ming, X. L. Yi, and L. H. Wei, “New SEC-DED-DAEC codes for
with a serial decoder so that the most common error patterns are multiple bit upsets mitigation in memory,” in Proc. IEEE/IFIP 20th Int.
corrected in one clock cycle. Conf. VLSI Syst.-Chip, Oct. 2011, pp. 254–259.
[12] L.-J. Saiz-Adalid, P. Reviriego, P. Gil, S. Pontarelli, and J. A. Maestro,
“MCU tolerance in SRAMs through low-redundancy triple adjacent error
R EFERENCES correction,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., to be
published.
[1] R. D. Schrimpf and D. M. Fleetwood, Radiation Effects and Soft [13] R. Naseer and J. Draper, “DEC ECC design to improve memory reliabil-
Errors in Integrated Circuits and Electronic Devices. Singapore: ity in sub-100 nm technologies,” in Proc. IEEE ICECS, Aug./Sep. 2008,
World Scientific, 2004. pp. 586–589.
[2] R. C. Baumann, “Soft errors in advanced computer systems,” IEEE Des. [14] M. Y. Hsiao, D. C. Bossen, and R. T. Chien, “Orthogonal Latin square
Test. Comput., vol. 22, no. 3, pp. 258–266, May/Jun. 2005. codes,” IBM J. Res. Develop., vol. 14, no. 4, pp. 390–394, Jul. 1970.
[3] C. L. Chen and M. Y. Hsiao, “Error-correcting codes for semiconductor [15] S.-F. Liu, P. Reviriego, and J. A. Maestro, “Efficient majority logic
memory applications: A state-of-the-art review,” IBM J. Res. Develop., fault detection with difference-set codes for memory applications,” IEEE
vol. 28, no. 2, pp. 124–134, Mar. 1984. Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 1, pp. 148–156,
[4] M. Y. Hsiao, “A class of optimal minimum odd-weight-column Jan. 2012.
SEC-DED codes,” IBM J. Res. Develop., vol. 14, no. 4, pp. 301–395, [16] M. J. E. Golay, “Notes on digital coding,” Proc. IEEE, vol. 37, p. 657,
Jul. 1970. Jun. 1949.
[5] E. Ibe, H. Taniguchi, Y. Yahagi, K. Shimbo, and T. Toba, “Impact of [17] S. Sarangi and S. Banerjee, “Efficient hardware implementation of
scaling on neutron-induced soft error in SRAMs from a 250 nm to encoder and decoder for Golay code,” IEEE Trans. Very Large Scale
a 22 nm design rule,” IEEE Trans. Electron Devices, vol. 57, no. 7, Integr. (VLSI) Syst., to be published.
pp. 1527–1538, Jul. 2010. [18] K. Namba, S. Pontarelli, M. Ottavi, and F. Lombardi, “A single-bit and
[6] P. Reviriego, J. A. Maestro, S. Baeg, S. Wen, and R. Wong, “Pro- double-adjacent error correcting parallel decoder for multiple-bit error
tection of memories suffering MCUs through the selection of the correcting BCH codes,” IEEE Trans. Device Mater. Rel., vol. 14, no. 2,
optimal interleaving distance,” IEEE Trans. Nucl. Sci., vol. 57, no. 4, pp. 664–671, Jun. 2014.
pp. 2124–2128, Aug. 2010. [19] S. Lin and D. J. Costello, Error Control Coding, 2nd ed.
[7] S. Satoh, Y. Tosaka, and S. A. Wender, “Geometric effect of multiple-bit Englewood Cliffs, NJ, USA: Prentice-Hall, 2004.
soft errors induced by cosmic ray neutrons on DRAM’s,” IEEE Electron [20] E. R. Berlekamp, “Decoding the Golay code,” Jet Propulsion Lab.,
Device Lett., vol. 21, no. 6, pp. 310–312, Jun. 2000. Pasadena, CA, USA, Tech. Rep. 32-1526, 1971, pp. 81–84.