Microelectronics Reliability 81 (2018) 167–173

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Microelectronics Reliability
journal homepage: www.elsevier.com/locate/microrel

Correspondence

Fault tolerant encoders for Single Error Correction and Double Adjacent Error Correction codes T

A R T I C L E I N F O A B S T R A C T

Keywords: Error correction codes (ECCs) are commonly used to deal with soft errors in memory applications. Typically,
Memory Single Error Correction-Double Error Detection (SEC-DED) codes are widely used due to their simplicity.
Fault tolerant However, the phenomenon of more than one error in the memory cells has become more serious in advanced
Logic sharing technologies. Single Error Correction-Double Adjacent Error Correction (SEC-DAEC) codes are a good choice to
Error correction codes (ECCs)
protect memories against double adjacent errors that are a major multiple error pattern. An important con-
Single Error Correction-Double Adjacent Error
sideration is that the ECC encoder and decoder circuits can also be affected by soft errors, which will corrupt the
Correction (SEC-DAEC)
memory data. In this paper, a method to design fault tolerant encoders for SEC-DAEC codes is proposed. It is
based on the fact that soft errors in the encoder have a similar effect to soft errors in a memory word and
achieved by using logic sharing blocks for every two adjacent parity bits. In the proposed scheme, one soft error
in the encoder can cause at most two errors on adjacent parity bits, thus the correctness of memory data can be
ensured because those errors are correctable by the SEC-DAEC code. The proposed scheme has been im-
plemented and the results show that it requires less circuit area and power than the encoders protected by the
existing methods.

1. Introduction

Soft errors caused by radiation particles have become one of the most challenging issues for memory reliability [1]. When a radiation particle,
such as an atmospheric neutron or a heavy ion hits the sensitive node of a memory cell, extra electron-hole pairs are generated, and the charges can
be collected by depletion regions. When the amount of the collected charge exceeds a critical value, the voltage level of the node could be changed,
and a soft error on the cell occurs [2]. For memories, soft errors can lead to data corruption and system failure. As technology scales down, the charge
induced by a radiation particle can be shared by several neighboring cells, thus multiple cell upsets (MCUs) occur [3]. MCUs, especially double
adjacent errors, are a significant percentage of soft errors in current technology nodes [4–6] (e.g., the percentage of double adjacent errors is more
than 70% of all multiple error patterns for 65 nm/45 nm SRAMs in [5]).
Error correction codes (ECCs) are commonly used to protect memories against soft errors [7–8]. Additional redundancy cells that store the parity
bits are added to each word in the memory array. Then, the encoder turns the k-bit data into an n-bit code-word and for the errors in the code-word,
the decoder can correct them and output the original data if the code has enough correction capability. Single Error Correction-Double Error
Detection (SEC-DED) codes are widely used due to their simplicity [7]. However, SEC-DED codes alone are no longer sufficient to protect the
memories in the presence of MCUs. One common approach to deal with MCUs is to combine SEC-DED codes with the use of interleaving in the
arrangement of the memory cells, so that cells that belong to the same logical word are physically separated. In that case, double adjacent errors as
an example, can only affect one bit per word and thus can be corrected by the SEC-DED codes. However, interleaving is not suitable in small
memories or register applications as its use may have an impact on floor-planning, access time and power consumption [6,9]. In order to deal with
double adjacent errors, which are the major error pattern among the MCUs, Single error correction-Double Adjacent Error Correction (SEC-DAEC)
codes have been studied by using the same number of parity bits as the ones of SEC-DED codes [9]. Therefore, in most cases, SEC-DAEC codes are a
good choice to provide protection for memories.
When ECCs are used to deal with the soft errors, there is also a reliability problem for the encoders and decoders because the circuits can also be
struck by the radiation particles as the memory cells. An error in the encoder during a write operation can corrupt the memory word being written.
An error in the decoder during a read operation can cause an incorrect output data. This means that the reliability for encoders and decoders can
affect the memory data directly. A well-known technique such as Triple Modular Redundancy (TMR) can protect the logic by tripling the circuits and
making a majority vote among the outputs [10]. However, it will result in a large circuit overhead. Some other alternatives with moderate overheads
have been presented in recent years. A fault tolerant encoder for SEC-DED codes has been proposed in [11] by considering the error in the encoder
has a similar effect to the SEU in memory and then can be corrected by the code. A concurrent error detection technique to detect errors in the
encoders of Orthogonal Latin Squares (OLS) codes was proposed in [12]. This scheme takes advantage of the property of OLS codes, which have no
logic sharing among the computations of the parity bits, to make the encoder self-checking. It can also be implemented for the syndrome compu-
tation part of the decoder. This work was extended to the decoder of OLS codes in [13]. Similarly, fault tolerant encoders and decoders for Euclidean
Geometry-Low Density Parity Check (EG-LDPC) codes were proposed in [14]. However, as in the case of OLS codes, the proposed scheme is tailored
to the specific features of EG-LDPC codes and cannot be used for SEC-DAEC codes.
In this paper, a method to design fault tolerant encoders for SEC-DAEC codes is studied based on the method presented in [11] but by using logic

https://doi.org/10.1016/j.microrel.2017.12.017
Received 11 April 2017; Received in revised form 9 November 2017; Accepted 10 December 2017
0026-2714/ © 2017 Published by Elsevier Ltd.
Correspondence Microelectronics Reliability 81 (2018) 167–173

1100110001110100100000
0001010011011001010000
1010100111100011001000
1001001110010110000100
0110101100001101000010
0111011000101010000001

Fig. 1. Parity check matrix H for the (22, 16) SEC-DAEC code in [9].

b1

b2

b3

b4

b5

b6
c1
b7
c2
b8
c3
b9
c4
b10
c5
b11
c6
b12

b13

b14

b15

b16

Fig. 2. Illustration of the encoder for the (22, 16) SEC-DAEC code in [9].

sharing blocks. The idea will be explored in detail in the following sections showing that it can be used to further reduce the circuit overheads
comparing to the existing methods.
The rest of the paper is organized as follows. Section 2 includes a description of fault tolerant encoders for SEC-DED codes in [11]. Based on that,
the proposed fault tolerant encoders for SEC-DAEC codes by using logic sharing blocks are presented in Section 3. Section 4 gives the comparison for
the implementation of different methods to protect encoders, which shows the benefit of the proposed scheme. Finally, the conclusions are presented
in Section 5.

2. Related work

SEC-DAEC encoders can be implemented simply by computing the parity bits for the input data bits. According to the parity check matrix H of the
codes, each parity bit can be obtained by performing multiple xor operations among the data bits. For example, the H matrix and the encoder
implementation for (22, 16) SEC-DAEC code (i.e., n = 22, k = 16) in [9] are shown in Fig. 1 and Fig. 2 respectively, in which b1-b16 are the data
bits and c1-c6 are the parity check bits. As mentioned before, the parity bit c1 can be obtained by performing multiple xor operations among the data
bits b1, b2, b5, b6, b10, b11, b12, and b14 based on H matrix, and so on for other parity bits.
In Fig. 2, it can be observed that errors on many of the first stage gates would corrupt more than one of the parity bits. For example, if the gate
that has inputs b6, b10, and b12 is affected by a soft error during a write operation, the output of these two gates used to obtain c1 and c2 will be
corrupted. Then there will be a double error on c1 and c2 stored in the memory word and it is uncorrectable by the SEC-DED code.
Soft errors in the encoder have a similar effect to soft errors in a memory word, having this into account, the fault tolerant encoders for SEC-DED
codes have been designed in [11] by adding some additional xor gates to avoid any logic sharing among the parity bits. The method can also be
implemented for SEC-DAEC codes. The modified encoder for (22, 16) SEC-DAEC code using the scheme in [11] is shown in Fig. 3, in which the grey
gates are the added ones. It can be observed that if an error affects any gate of the encoder circuit, at most one bit error will be created among the
parity bits, and then the error can be corrected by regarding it as an error in the memory word. With this scheme, the encoders for SEC-DAEC codes
can have an adequate protection level at the cost of some overheads in the encoder implementation.

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b1

b2

b3

b4

b5

b6
c1
b7
c2
b8
c3
b9
c4
b10
c5
b11
c6
b12

b13

b14

b15

b16

Fig. 3. Illustration of the fault tolerant encoder implementation proposed in [11] for the (22, 16) SEC-DAEC code in [9].

3. Proposed scheme

The proposed fault tolerant encoders for SEC-DAEC codes are based on the method proposed in [11] but allowing a controlled logic sharing,
which has benefits in terms of circuit overheads. The logic sharing is allowed among two adjacent parity check bits. This is achieved by putting two
adjacent parity bits in each block, and then synthesizing the blocks separately. The scheme ensures that any error in the encoder will affect at most
two adjacent parity bits that are correctable. In order to obtain an encoder with the lowest overhead, the pairs of parity bits that belong to each block
should be carefully selected with the largest logic sharing value. The value of logic sharing means the number of the same data bits that participate in
two adjacent parity bits. When we arrange two adjacent parity bits with larger logic sharing value, more xor gates are shared between by these two
parity bits, thus less circuit area is required by the encoder.
Let us take the (22, 16) SEC-DAEC code in [9] as an example to describe the proposed method in detail. From the H matrix as shown in Fig. 1, it
can be observed that the logic sharing values between each two adjacent parity bits are 3, 3, 4, 3, and 4 respectively. Therefore we put the first and
second parity bits into the first block (the value of logic sharing is 3), put the third and fourth parity bits in the second block (the value of logic
sharing is 4), and put the last two parity bits in the last block (the value of logic sharing is 4) as in that case the gates that can be shared are
maximized.
The corresponding fault tolerant encoder is shown in Fig. 4, in which the grey gates are logic sharing ones. It can be observed that in the worst
case, any error on the encoder circuit will cause two adjacent errors on the parity bits that is equivalent to a double adjacent error in the memory
word. Therefore, an adequate protection for the encoder is provided.
In the case of the (39, 32) SEC-DAEC code in [9], according to its H matrix as shown in Fig. 5, the first logic sharing block contains parity bits c1
and c2; the second logic sharing block contains c4 and c5; the third logic sharing block contains c6 and c7. The bit c3 is left alone to achieve a largest
logic sharing value. For the (72, 64) SEC-DAEC code in [9] with the H matrix as shown in Fig. 6, the logic sharing blocks in the best case are arranged
for c1 and c2; c3 and c4; c5 and c6; c7 and c8, respectively.
In summary, the proposed logic sharing scheme can ensure that an error in the encoder can trigger errors on at most two adjacent parity bits that
can be corrected by the SEC-DAEC codes.
Let us now consider a double error on the encoder. In the case that the double error affects xor gates on the same parity check equation, if the two
errors affect the same time window at the output, they will compensate and produce the correct result. If they affect different time windows, the
output will be in error depending on the timing. In the case that the double error affects a shared logic that computes two adjacent parity checks, it
can at most produce two adjacent errors that can be corrected by the SEC-DAEC codes. The only failing case is that the two errors affect different
blocks of parity computations. In this case multiple errors (up to four) can be produced at the output of the encoder. However, this should be less
likely as the gates that belong to the same block will be in most cases placed together. Therefore, if we assume that there is physical locality in the
multiple error as it is caused by a single particle hit, the probability that it affects two different parity computation blocks should be low.
It is worth mentioning that the proposed scheme can also be used to protect the syndrome computation part of the decoder as it is basically the
encoder with the xor of each parity computation with the corresponding stored parity bit. This part of the decoder is more vulnerable than the part
that compares the syndrome with the columns of the H matrix to locate errors. The reason is that all gates in the syndrome computation part are xor
so there is no logic masking. For the syndrome comparing part, each comparator can be considered as a set of and gates that in the absence of a soft

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Correspondence Microelectronics Reliability 81 (2018) 167–173

b1
b2
b4
b5
b6
b9 c1
b10
b11
c2
b12
b13
b14
b16 Logic sharing block1

b1
b3
b4
b5
b7
b8
c3
b9
b10
b11 c4
b12
b14
b15
b16 Logic sharing block2

b2
b3
b4
b5
b6
b7
c5
b8
b11
b13 c6
b14
b15
b16 Logic sharing block3

Fig. 4. The proposed encoder for the (22, 16) SEC-DAEC code in [9].

error in the word stored, receives zeros on the inputs. This means that if a soft error changes the output of one of these gates, the error will be masked
in the subsequent level unless there is also a second error in the word stored (something that is highly unlikely).

4. Evaluation

In order to evaluate the benefits of the proposed technique, its circuit overheads have been compared with two existing schemes in terms of the
area, delay and power. The first existing scheme is to triple the original encoder (i.e., all parity bits are included in one block) and then make a
majority voting among the tripled blocks, which is referred to as TMR in the rest sections. The second scheme is to use different blocks for each parity
bit to avoid any logic sharing as done in [11], which is referred to as no-logic-sharing in the rest sections. All the schemes have been implemented for
(22, 16), (39, 32), and (72, 64) SEC-DAEC codes in Verilog, and the encoders have been synthesized and mapped to a TSMC 65 nm technology using
Synopsys Design Compiler (DC).
Synthesis of encoders has been run in two configurations: area optimization and delay optimization. The first one gives the best area that can be
obtained and the second one gives the best delay. They thus provide information on the circuit cost and delay that can be achieved.

101110010101100001001010011100001000000
010101001011000100011100011000010100000
101010100110001010110000110000110010000
010100011100010101100001100001110001000
001001100000101101001011000011100000100
100001001001011010010110100111000000010
010010110010110010100101001110000000001

Fig. 5. Parity check matrix H for the (39, 32) SEC-DAEC code in [9].

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100101011101011001010010010000101100010011001000110100001110000010000000
101110011000001010100100100001011000100110010001101000011100000101000000
011010101011101011001001000010110001001100100011010000111000001100100000
111101100101100110010010100101100010011001000110100001100000011100010000
100101100011110110100101001011000100110010001100000011010000111000001000
111011001111110111001010010110001001100000011001000110100001110000000100
011010110110111100010100101100000011000100110010001101000011100000000010
010111101110011100101001011000010110001001100100011010000111000000000001

Fig. 6. Parity check matrix H for the (72, 64) SEC-DEAC code in [9].

Table 1
Comparison of synthesized encoders with an area optimization.

Codes Options Area Delay Power

2
(μm ) (%) (ns) (%) (mW) (%)

(22, 16) SEC-DAEC TMR 438.4 268.6 1.16 165.7 0.476 337.6
No-logic-sharing 191.6 117.4 0.70 100 0.162 114.9
Proposed scheme 163.2 100 0.70 100 0.141 100
(39, 32) SEC-DAEC TMR 924.0 257.0 1.24 155.0 0.982 281.4
No-logic-sharing 424.0 117.9 0.80 100 0.382 109.5
Proposed scheme 359.6 100 0.80 100 0.349 100
(72, 64) SEC-DAEC TMR 1934.8 247.3 1.43 137.5 2.189 290.0
No-logic-sharing 1018.8 130.2 1.04 100 0.942 124.8
Proposed scheme 782.4 100 1.04 100 0.755 100

Table 2
Comparison of synthesized encoders with a delay optimization.

Codes Options Area Delay Power

(μm2) (%) (ns) (%) (mW) (%)

(22, 16) SEC-DAEC TMR 1158.8 248.5 0.52 140.5 0.935 336.3
No-logic-sharing 524.0 112.3 0.37 100 0.302 108.6
Proposed scheme 466.4 100 0.37 100 0.278 100
(39, 32) SEC-DAEC TMR 2209.2 246.5 0.57 126.7 1.807 297.2
No-logic-sharing 970.8 108.3 0.45 100 0.644 105.9
Proposed scheme 896.4 100 0.45 100 0.608 100
(72, 64) SEC-DAEC TMR 4335.6 242.3 0.68 125.9 3.977 294.6
No-logic-sharing 2072.8 115.8 0.54 100 1.473 109.1
Proposed scheme 1789.6 100 0.54 100 1.350 100

Table 1 shows the results for the area optimized synthesis for the encoders with the different options. As expected, the proposed fault tolerant
encoder results in significant cost reductions. Let us take the proposed scheme as the baseline, TMR and the no-logic-sharing scheme cost 168.6% and
17.4% more area for the (22, 16) encoder, 157.0% and 17.9% more area for the (39, 32) code, 147.3% and 30.2% area for the (72, 64) code,
respectively. The cost reduction is achieved because fewer gates are required in the proposed fault tolerant encoders by using logic sharing blocks. In
terms of delay, the proposed scheme and the no-logic sharing scheme require the same ones because the critical paths are the same. TMR costs
65.7%, 55% and 37.5% more delay than the other two schemes for the (22, 16), (39, 32) and (72, 64) codes because there is a voting logic in the
TMR scheme. In terms of power, the TMR scheme and the no-logic-sharing scheme cost 237.6% and 14.9% more than the ones costed by the
proposed scheme for the (22, 16) code, 181.4% and 9.5% for the (39, 32) code and 190% and 24.8% for the (72, 64) code, respectively.
The results for the delay optimized synthesis are presented in Table 2, from which we can observe that the proposed encoders also work better.
The encoders using TMR and the no-logic-sharing scheme cost 148.5% and 12.3% more area and 236.3% and 8.6% more power than the proposed
scheme for the (22, 16) code, 146.5% and 8.3% more area and 197.2% and 5.9% more power for the (39, 32) code, and 142.3% and 15.8% more
area and 194.6% and 9.1% more power for the (72, 64) code. In terms of delay, the TMR scheme requires 40.5%, 26.7% and 25.9% more than the
other two schemes which have the same ones as the reasons mentioned above.
A more clear comparison is illustrated from Figures 7–9. It can be observed that the proposed scheme results in the lowest overheads in all cases.
This is due to the logic sharing blocks, which reduce the number of xor gates in the circuits.
It is interesting to consider the impact on the overall area and power of the memory. To do so, the proposed fault tolerant encoders in conjunction
with a 4K word memory have been synthesized and mapped to the same 65 nm library. The results are shown in Table 3. It can be observed that the
reductions obtained by using the proposed technique are very small (less than 0.05%) in terms of area. However, in terms of dynamic power the
proposed scheme can save 0.5% for the entire design when using a 64 bit data word. As noted before, the proposed scheme can be also used to
protect the decoder thus potentially increasing the savings. In any case, this 0.5% power reduction is achieved with no performance penalty and thus
even if the saving is not large, it can help designers to minimize overall power consumption. Finally, the percentage will vary with memory size and
technology. As modern ASICs can have thousands of embedded memories of different sizes, the overall reduction on the ASIC power consumption
can be more meaningful. Therefore, it can be an interesting option when circuit overhead is limited in the memory application.

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5000
Area optimization DC for TMR
Area optimization DC for no-logic-sharing
Area optimization DC for proposed scheme
4000 Delay optimization DC for TMR
Delay optimization DC for no-logic-sharing
Delay optimization DC for proposed scheme
3000

Area (μm2)
2000

1000

0
(22, 16) code (39, 32) code (72, 64) code

Fig. 7. Encoder area estimates for different schemes.

2.4
2.2 Area optimization DC for TMR
Area optimization DC for on-logic-sharing
2.0 Area optimization DC for proposed scheme
Delay optimization DC for TMR
1.8
Delay optimization DC for no-logic-sharing
1.6 Delay optimization DC for proposed scheme

1.4
Delay (ns)

1.2
1.0
0.8
0.6
0.4
0.2
0.0
(22, 16) code (39, 32) code (72, 64) code

Fig. 8. Encoder delay estimates for different schemes.

4.5
Area optimization DC for TMR
4.0 Area optimization DC for no-logic-sharing
Area optimization DC for proposed scheme
3.5 Delay optimization DC for TMR
Delay optimization DC for no-logic-sharing
3.0 Delay optimization DC for proposed scheme
Power (mW)

2.5

2.0

1.5

1.0

0.5

0.0
(22, 16) code (39, 32) code (72, 64) code
Fig. 9. Encoder power estimates for different schemes.

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Table 3
Comparison of synthesized encoders with a delay optimization.

Codes Options Area Power

(μm2) (%) (mW) (%)

(22, 16) SEC-DAEC TMR 190,484.0 100.15 4.926 100.4

No-logic-sharing 190,234.0 100.01 4.909 100.1
Proposed scheme 190,205.6 100 4.904 100
(39, 32) SEC-DAEC TMR 311,989.3 100.18 7.755 101.1
No-logic-sharing 311,487.5 100.02 7.691 100.2
Proposed scheme 311,421.3 100 7.673 100
(72, 64) SEC-DAEC TMR 547,876.9 100.20 13.275 101.2
No-logic-sharing 546,906.5 100.03 13.118 100.5
Proposed scheme 546,757.3 100 13.055 100

5. Conclusions

This paper has presented a scheme to design fault tolerant encoders for SEC-DAEC codes. By dividing the circuit into several logic sharing blocks,
the number of xor gates required by the encoders is decreased. The method ensures that an error in the encoder can trigger errors on at most two
adjacent parity bits that can be corrected by the SEC-DAEC codes. Therefore, it provides an adequate protection for the encoder.
The proposed encoder has been implemented and compared to the existing TMR technique and no-logic-sharing scheme in [11] in terms of area,
delay and power. The results show that the proposed scheme has an advantage in all cases, thus it can be an interesting alternative for the memories
protected by SEC-DAEC codes.
Finally, it is worth mentioning that the proposed scheme can also be used to protect the syndrome computation part of the decoder.

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⁎
Shanshan Liua, Pedro Reviriegob, Juan Antonio Maestrob, Liyi Xiaoa,
a
Microelectronics Center, Harbin Institute of Technology, Harbin 150001, China
b
Aerospace Research and Innovation in Electronic Systems Center (ARIES), Universidad Antonio de Nebrija, C/Pirineos, 55, E-28040, Madrid, Spain
E-mail address: [email protected]

⁎
Corresponding author.

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