Digital Design Concepts,

Introduction to Verilog HDL

Digital Logic Design is a “a minute to learn, a

lifetime to master”
Need for HDL
Gate Length
What is Moore’s Law
What is Moore’s Law
Complexity & Productivity Growth of ICs

• Complexity grows 58%/yr (doubles every 18 mos)

• Productivity grows 21%/yr (doubles every 3 1/2 yrs) unless
methodology is updated
Complexity and Productivity Growth
10,000,000 100,000,000
Com
1,000,00 plexity 10,000,00
Tra ns is tors pe r C hip

0 0

Tra ns is tors /Sta ff M

Productivit

P roduc tiv ity

100,000 1,000,00
C om ple x ity

y 0
(K )

10,000 100,000

1,000 10,000

onth
100 1,000

10 100
1980 1985 1990 1995
[Source: MITRE]
2000 2005 2010
7

source: Jin-Fu Li, EE, NCU

IC Community

Design rules
Simulation models
Silicon and parameters IC
foundry Mask layouts design
Integrated circuits

CAD
Process information
tool Software tools
provider

[M. M. Vai, VLSI

design]

source: Jin-Fu Li, EE, NCU

 System to Silicon Design

System Requirements Algorithm Hardware Architecture Synthesis

Σ
X[k] =
= x[n]e-j2 πk/N
-j2 πk/N
X[k] Σ x[n]e

πk/N
+j2 πk/N
x[n] =
x[n] = X[k]e
Σ X[k]e
+j2 Σ

System Integration Fabricate and Test Physical Design For Test

Observe
Observe

Cont rol
Cont rol

[Source: MITRE]

source: Jin-Fu Li, EE, NCU

FPGA Design Flow
Functional Spec

HDL
Behavioral
Simulation
Synthesis

Place and Route

Static Timing Analysis

Verify in Circuit
ASIC Design Flow
◻ Functional Spec

◻ HDL
◻ Behavioral
Simulation
◻ Synthesis
◻ Static Timing Analysis
DFT Insertion
◻ Formal Equivalence
◻ Place and Route
◻ Static Timing Analysis

◻ Formal Equivalence

◻ Physical Verification
◻ Verify in Circuit
Design Steps in an IC

An industrial level overview

Languages Usage

Requirements Matlab
Algorithm and Architectural C/C++

Func & SW Development

Behavioral
Ver System
SoC Verification a“E” C
Syste
IP Verification Sugar
VHDL m
Verilog
Verilog
RTL
Gates
Transistor

s
Difference between C and
HDL HDL is a hardware
◻ C is a middle level ◻

language. its a mix of description language(HDL)

a high level language . It is used for
implementing the hardware
and an assembly circuit.
language.

◻ C can only ◻ HDL allows both sequential

and concurrent executions.
handle
sequential
◻ But a successful HDL
instructions. programmer needs thorough
working knowledge of the
◻ A C program can be hardware circuits. He
successfully written should be able to predict
with pure logical or how a given code will be
algorithmic thinking. implemented in hardware.
Difference between C and
HDL
◻ Normally we don't ◻ But when it comes to HDL
care about resource a slightly complicated code
usage in C. This is can make you bent on your
because a C program knee The memory and
is usually ran on a other logic elements are
computer which uses limited in a FPGA(where
you normally put the
a powerful processor
VHDL/ Verilog code in).
with high speed. We This is why it is very
also don't care about difficult to implement
the memory usage. image processing
algorithms in HDL than in
C.
HDL
◻ What and why HDL
◻ Verilog HDL
◻ Modelling a simple circuit.
□ Delays
□ Stimulus
◻ Abstraction Levels
□ Gates
□ Dataflow
□ Behavioural
Hardware Description Language
(HDL)
◻ Basic idea is a programming language to describe
hardware
◻ Initial purpose was to allow abstract design and
simulation
□ Design could be verified then implemented
in hardware
◻ Now Synthesis tools allow direct implementation
from HDL code.
□ Large improvement in designer productivity
HDL
◻ HDL allows write-run-debug cycle for hardware
development.
□ Similar to programming software
□ Much, much faster than design-implement-debug
◻ Combined with modern Field Programmable Gate
Array chips large complex circuits (100000s of
gates) can be implemented.
 Advantages of HDL

19
HDLs
◻ There are many different HDLs
□ Verilog HDL
□ ABEL
□ VHDL
◻ VHDL is the most common
□ Large standard developed by US DoD
□ VHDL = VHSIC HDL
□ VHSIC = Very High Speed Integrated Circuit
Standard HDL supported by IEEE
VHDL – (Very high speed integrated circuit
Hardware Description Language) ) became IEEE
standard 1076 in 1987. It was updated in 1993 and is
known today as "IEEE standard 1076 1993
- a Department of Defense mandated language
that was initially used by defense contractors, but is
now used commercially and in research universities.

21
Standard HDL supported by IEEE
Verilog – ". The Verilog hardware description language
has been used far longer than VHDL and has been used
extensively since it was launched by Gateway in 1983.
Cadence bought Gateway in 1989 and opened Verilog to
the public domain in 1990. It became IEEE standard 1364
in December 1995.
- a proprietary HDL promoted by a company called
Cadence Data systems, but Cadence transferred control of
Verilog to a consortium of companies and universities
known as Open Verilog International (OVI).

22
A Tale of Two HDLs
VHDL Verilog

23
Digital Design using Verilog

24
Verilog HDL
◻ Verilog HDL is second most common
□ Easier to use in many ways = better for teaching
□ C - like syntax
◻ History
□ Developed as proprietry language in 1985
□ Opened as public domain spec in 1990
■ Due to losing market share to VHDL
□ Became IEEE standard in 1995
 History

Paper or breadboard
Gate level

26
• Too low-level for initial functional 27
specification Abstract behavioral model
• Early high-level design exploration
 We will use Verilog…

28
 Verilog Capabilities

• Primitive logic gates , such as and, or and

nand, are built-in into the language.
• It has built-in logic functions such as &
(bitwise-and) and | (bitwise-or).
• Flexibility of creating a user-defined primitive
(UDP). Such a primitive could either be a
combinational logic primitive or a sequential
logic primitive.
• Switch-level modeling primitive gates, such as
pmos and nmos, are also built-in into the
language.
29
 Verilog Capabilities
• Explicit language constructs are provided for
specifying pin-to-pin delays, path delays and
timing checks of a design.
• A design can be modeled in three different
styles or in a mixed style. These styles are:
behavioral style- modeled using procedural
constructs;
dataflow style – modeled using continuous
assignments; and
structural style- modeled using gate and
module instantiations.

30
 Verilog Capabilities
• There are two data types in Verilog HDL;
the net data type
the register data type.
• Hierarchical designs can be described, up to any
level , using the module instantiation construct.
• A design can be of arbitrary size.
• Verilog HDL is non-proprietary and is an IEEE
standard.
• It is human and machine readable. Thus, it can be
used as an exchange language between tools and
designers.
31
 Verilog Capabilities
• The capabilities of the Verilog HDL language can be
further extended by using the programming language
interface (PLI) mechanism.
• A design can be described in a wide range of levels,
ranging from switch-level, gate-level, register-
transfer-level (RTL) to algorithmic-level, including
process and queuing-level.
• A design can be modeled entirely at the switch-level
using the built-in switch-level primitives.

32
 Verilog Capabilities
• The same single language can be used to
generate stimulus for the design and for
specifying test constraints, such as specifying the
values of inputs.
• Verilog HDL can be used to perform response
monitoring of the design under test.
• High-level programming language constructs
such as conditionals, case statements, and loops
are available in the language.

33
 Verilog Capabilities

• Notion of concurrency and time can be

explicitly modeled.
• Powerful file read and write capabilities are
provided.
• The language is non-deterministic under
certain situations.

34
 Verilog Capabilities

Mixed-Level Modeling

switch algorithm

gate switch

gate
RTL

35
Introduction to Verilog
Verilog has Three styles of Coding
Gate Level modeling
Data Flow modeling
Behavioral Modeling
Verilog HDL
◻ Verilog constructs are use defined keywords
□ Examples: and, or, wire, input output
◻ One important construct is the module
□ Modules have inputs and outputs
□ Modules can be built up of Verilog primatives or of
user defined submodules.
Example: Simple Circuit
Diagram
Example: Simple Circuit
HDL
module smpl_circuit(A,B,C,x,y);
input A,B,C;
output x,y;
wire e;
and g1(e,A,B);
not g2(y, C);
or g3(x,e,y);
endmodule
Simple Circuit Notes
◻ The module starts with module keyword
and finishes with endmodule.
◻ Internal signals are named with wire.
◻ Comments follow //
◻ input and output are ports. These are placed
at the start of the module definition.
◻ Each statement ends with a semicolon, except
endmodule.
Circuit to code

module smpl_circuit(A,B,C,x,y);
input A,B,C;
output x,y;
wire e;
and g1(e,A,B);
not g2(y, C);
or g3(x,e,y);
endmodule
Dataflow modelling
◻ Another level of abstraction is to model dataflow.
◻ In dataflow models, signals are continuously
assigned values using the assign
keyword.
◻ assign can be used with Boolean expressions.
□ Verilog uses & (and), | (or), ^ (xor) and ~
(not)
◻ Logic expressions and binary arithmetic are
also possible.
Simple Circuit Boolean
Expression

x = A.B + C
y=C
Boolean Expressions

//Circuit specified with Boolean equations

module circuit_bln (x,y,A,B,C);
input A,B,C;
output x,y;
assign x = A | (B & ~C);
assign y = ~C ;
endmodule
Multiplexor
◻ Multiplexor is a combinational circuit where
an input is chosen by a select signal.
□ Two input mux
□ output =A if select =1
□ output= B if select =0

A
B
x
s
Two Input
Multiplexor
◻ A two-input mux is actually a three input device.
s A B x
0 0 0 0
0 0 1 1
A
0 1 0 0
B
x 0 1 1 1
1 0 0 0
s
1 0 1 0
1 1 0 1
x = A.s + B.s
1 1 1 1
 Dataflow description of 2-input Mux

◻ Conditional operator ?:takes three operands:

condition? true_expression :
false_expression

module mux2x1_df
(A,B,select,OUT);
input A,B,select;
output OUT;
assign OUT = select ? A : B;
endmodule
Behavioural
Modelling
◻ Represents circuits at functional and
algorithmic level.
◻ Use proceedural statements similar in concept to
proceedural programming languages (e.g. C, Java),
◻ Behavioural modelling is mostly used to
represent sequential circuits.
Behavioural
Modelling
◻ Behavioural models place proceedural statements
in a block after the always keyword.
◻ The always keyword takes a list of variables.
The block of statements is executed whenever one
of the variables changes.
◻ The target variables are of type reg. This
type retains its value until a new value is
assigned.
Behavioral description of 2-input mux

module mux2x1_bh(A,B,select,OUT);
input A,B,select;
output OUT;
reg OUT;
always @ (select or A or B)
if (select == 1) OUT = A;
else OUT = B;
endmodule
HDL Summary
◻ Hardware Description Languages allow fast design
and verification of digital circuits.
◻ Accurate simulation and testing requires delays and
inputs to be specified.
◻ There are three different levels of abstraction
for modelling circuits.
Thank you