CENG400-Midterm-Fall 2014
CENG400-Midterm-Fall 2014
School of Engineering
Department of Computer and Communication Engineering
Fall 2014 – 2015
Instructors: Dr. Zaher Merhi, Dr. Ali Ghwouyel, Dr. Ayman Khalil, Dr. Ali Bazzi, Dr.
Abdelmehsen Ahmad
Time: 75 minutes
There are three Questions in the booklet each has several parts, please answer all parts of the 3
questions to the best of your ability.
Marking Scheme:
Page 1 of 9
Question 1: CPU Performance (25 Points)
3. If Processor P1 runs the program in 0.01 ms, what should be the clock rate? ( 4 points)
Page 2 of 9
5. Consider now that the instructions of Class A represents addition operations and the
instructions of class C represent multiplications. An optimization is done to reduce the
number of clock cycles of this class of instructions. Each multiplication is then replaced
by 3 addition operations. That is, we can completely replace Class C with Class A in this
way each class C instruction takes 3 class A instructions. Class B remains unchanged.
a. What will be the total number of clock cycles needed to run the program? ( 3
points)
c. The execution of the program takes now 3 microseconds. What is the new clock
rate for P1? ( 3 points)
Page 3 of 9
Question 2: Single Cycle Data Path (35 points)
a) Consider the data path below for a single cycle 32-bits MIPS processor
Assume that we are executing the following instruction
4
2
1
$t0 = 0x00000A57
3
$t1 = 0x000006B0
PC = 0x000000B30
Page 4 of 9
1) Fill the table below with the content of the lines indicated by the number on the figure (12
Points)
1
2
3
4
5
6
2) For each of the following instructions fill the respective tables (6 points)
lw
RegDst Branch
MemRead MemtoReg
ALUOp MemWrite
ALUSrc RegWrite
slt
RegDst Branch
MemRead MemtoReg
ALUOp MemWrite
ALUSrc RegWrite
beq
RegDst Branch
MemRead MemtoReg
ALUOp MemWrite
ALUSrc RegWrite
Page 5 of 9
b) Consider the following MIPS program that was run on 5 stage MIPS pipeline processor
addi $t0, $t1, 100
lw $t2, 4($t0)
lw $t0, 8($t2)
lw $t2, 16($t0)
add $t2, $t2,$t1
sw $t1, 0($t3)
addi $t4, $t3, 100
i. Assume Now that forwarding is employed, fill the table below. Indicate Stalls by writing
ST in the Clock cycle (C) where it occurs and Forwarding by an arrow() (12 points)
Clock cycle
Instruction C1 C2 C3 C4 C5 C6 C7 C8 C9 C C C 12 C 13 C 14 C 15 C 16 C 17 C 18
10 11
addi $t0,
$t1, 100
lw $t2,
4($t0)
lw $t0,
8($t2)
lw $t2,
16($t0)
add $t2,
$t2,$t1
sw $t1,
0($t3)
addi $t4,
$t3, 100
ii. Is it possible to re-write the program in order to reduce the number of stall cycles? if yes
explain how? (5 points)
Page 6 of 9
Question 4 – MIPS (40 Points)
(a) (20 points) Given the following MIPS program what does
Address Program Comment (what is the instruction performing)
0x12ABC ADD $v0, $v0, $0 Set the content of $s0 to 0
ADDi $t0, $0, 1
Label2: AND $t2, $a0, $t0
BEQ $t2, $0, Label1
ADDi $v0, $v0, 1
Label1: SLL $t0, $t0, 1
BEQ $t0, $0, Exit
J Label2
Exit:
a) Fill the table by adding all addresses and comments on each program instruction (7
points)
b) Assume that the value of $a0 = 0x00000007 trace the program and find the value of $v0,
write down the first 4 iteration (3 points)
d) Translate to binary the following instructions taken from the program above
i. ( 3 points)
Instruction BEQ $t2, $0, Label1
Binary
HEX
ii. ( 3 points)
Instruction J Label2
Binary
HEX
iii. (2 points)
Instruction AND $t2, $a0, $t0
Binary
HEX
Page 7 of 9
(b) (20 points) Write a MIPS programs that performs the concatenation of two strings. That is, if
the first string is “I Love \0” and the second string is “MIPS \0” after performing the function
the result will be anther string with the value “I love MIPS \0”.
The two strings are stored are located 0x2234F50 and 0x12AD48 and the resulting string will
be located at address 0x100.
Assume that the string contents are already existing in memory and that each string is
terminated by ‘/0’
Page 8 of 9
Extra Sheet
Page 9 of 9