CD54HC4538, CD74HC4538,

CD54HCT4538, CD74HCT4538
Data sheet acquired from Harris Semiconductor
SCHS123E High-Speed CMOS Logic Dual Retriggerable
June 1998 - Revised October 2003 Precision Monostable Multivibrator

Features Description
• Retriggerable/Resettable Capability The ’HC4538 and ’HCT4538 are dual
retriggerable/resettable monostable precision multivibrators
• Trigger and Reset Propagation Delays Independent of
[ /Title for fixed voltage timing applications. An external resistor
RX, CX
(RX) and an external capacitor (CX) control the timing and
(CD54 the accuracy for the circuit. Adjustment of RX and CX
• Triggering from the Leading or Trailing Edge
HC453 provides a wide range of output pulse widths from the Q and
• Q and Q Buffered Outputs Available
8, Q terminals. The propagation delay from trigger input-to-
CD74 • Separate Resets output transition and the propagation delay from reset input-
to-output transition are independent of RX and CX.
HC453 • Wide Range of Output Pulse Widths
8, Leading-edge triggering (A) and trailing edge triggering (B)
• Schmitt Trigger Input on A and B Inputs inputs are provided for triggering from either edge of the
CD74 input pulse. An unused “A” input should be tied to GND and
• Retrigger Time is Independent of CX
HCT45 an unused B should be tied to VCC. On power up the IC is
38) • Fanout (Over Temperature Range) reset. Unused resets and sections must be terminated. In
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads normal operation the circuit retriggers on the application of
/Sub- each new trigger pulse. To operate in the non-triggerable
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
ject mode Q is connected to B when leading edge triggering (A)
(High • Wide Operating Temperature Range . . . -55oC to 125oC is used or Q is connected to A when trailing edge triggering
Speed • Balanced Propagation Delay and Transition Times (B) is used. The period (τ) can be calculated from τ = (0.7)
RX, CX; RMIN is 5kΩ. CMIN is 0pF.
CMOS • Significant Power Reduction Compared to LSTTL
Logic Logic ICs Ordering Information
• HC Types
TEMP. RANGE
- 2V to 6V Operation PART NUMBER (oC) PACKAGE
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V CD54HC4538F3A -55 to 125 16 Ld CERDIP

• HCT Types CD54HCT4538F3A -55 to 125 16 Ld CERDIP

- 4.5V to 5.5V Operation CD74HC4538E -55 to 125 16 Ld PDIP
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min) CD74HC4538M -55 to 125 16 Ld SOIC
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH CD74HC4538MT -55 to 125 16 Ld SOIC

CD74HC4538M96 -55 to 125 16 Ld SOIC

Pinout
CD54HC4538, CD54HCT4538 CD74HC4538NSR -55 to 125 16 Ld SOP
(CERDIP)
CD74HC4538 CD74HC4538PW -55 to 125 16 Ld TSSOP
(PDIP, SOIC, SOP, TSSOP)
CD74HC4538PWR -55 to 125 16 Ld TSSOP
CD74HCT4538
(PDIP, SOIC) CD74HC4538PWT -55 to 125 16 Ld TSSOP
TOP VIEW
CD74HCT4538E -55 to 125 16 Ld PDIP
1CX 1 16 VCC
1RXCX 2 15 2CX CD74HCT4538M -55 to 125 16 Ld SOIC
1R 3 14 2RXCX
CD74HCT4538MT -55 to 125 16 Ld SOIC
1A 4 13 2R
CD74HCT4538M96 -55 to 125 16 Ld SOIC
1B 5 12 2A
1Q 6 11 2B NOTE: When ordering, use the entire part number. The suffixes 96
1Q 7 10 2Q
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
GND 8 9 2Q

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
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 CD54HC4538, CD74HC4538, CD54HCT4538, CD74HCT4538

Functional Diagram
1Cx 1Rx
VCC
1 2

1Cx 1RxCx
4 6
1A 1Q
MONO 1
5 7
1B 1Q
3
1R

13
2R
12 10
2A 2Q

11 MONO 2 9
2B 2Q

2Cx 2RxCx

15 14
GND = 8 VCC
VCC = 16 2Cx 2Rx

TRUTH TABLE
R2
INPUTS OUTPUTS
CL R1
R A B Q Q CL Q

L X X L H p
D n
X H X L H
CL CL
X X L L H Q
p CL
H L ↓ n
p
H ↑ H CL n R1

H = High Level, L = Low Level, ↑ = Transition from Low to High, CL

↓ = Transition from High to Low, One High Level Pulse,
One Low Level Pulse, X = Irrelevant. FIGURE 1. FF DETAIL

2
 CD54HC4538, CD74HC4538, CD54HCT4538, CD74HCT4538

16
VCC
VCC VCC

VCC
RX
2(14) + COMP II 6(10)
R1
Q
CX 1(15) -
R2

VCC
8 VCC 7(9)
Q
HIGH Z

3(13)

R
VCC

4(12)
A D R1 R2 Q
FF
CL Q
5(11) CL
B

FIGURE 2. LOGIC DIAGRAM (1 MONO)

FUNCTIONAL TERMINAL CONNECTIONS

VCC TO GND TO INPUT PULSE TO OTHER

TERMINAL NUMBER TERMINAL NUMBER TERMINAL NUMBER CONNECTIONS

FUNCTION MONO1 MONO2 MONO1 MONO2 MONO1 MONO2 MONO1 MONO2

Leading-Edge 3, 5 11, 13 4 12
Trigger/Retriggerable

Leading-Edge 3 13 4 12 5-7 11-9

Trigger/Non-Retriggerable

Trailing-Edge 3 13 4 12 5 11
Trigger/Retriggerable

Trailing-Edge 3 13 5 11 4-6 12-10

Trigger/Non-Retriggerable

NOTES:
1. A retriggerable one-shot multivibrator has an output pulse width which is extended one full time period (T) after application of the last
trigger pulse.
2. A non-triggerable one-shot multivibrator has a time period (T) referenced from the application of the first trigger pulse.

T T
FIGURE 3. INPUT PULSE TRAIN FIGURE 4. RETRIGGERABLE MODE FIGURE 5. NON-RETRIGGERABLE MODE
PULSE WIDTH (A MODE) PULSE WIDTH
(A MODE)

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 CD54HC4538, CD74HC4538, CD54HCT4538, CD74HCT4538

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Package Thermal Impedance, θJA (see Note 5):
DC Input Diode Current, IIK E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73oC/W
DC Output Diode Current, IOK NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W
DC Output Source or Sink Current per Output Pin, IO Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC (Note 3)
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Times, tr, tf
Reset Input:
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Trigger Inputs A or B:
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited (Max)
External Timing Resistor, RX (Note 4) . . . . . . . . . . . . . . . .5kΩ (Min)
External Timing Capacitor, CX (Note 4) . . . . . . . . . . . . . . . . . 0 (Min)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:
3. Unless otherwise specified, all voltages are referenced to ground.
4. The maximum allowable values of RX and CX are a function of leakage of capacitor CX, the leakage of the ’HC4538, and leakage due to
board layout and surface resistance. Values of RX and CX should be chosen so that the maximum current into pin 2 or pin 14 is 30mA.
Susceptibility to externally induced noise signals may occur for RX > 1MΩ.
5. The package thermal impedance is calculated in accordance with JESD 51-7.

DC Electrical Specifications
TEST
CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC
VCC
PARAMETER SYMBOL VI (V) IO (mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS
HC TYPES
High Level Input VIH - - 2 1.5 - - 1.5 - 1.5 - V
Voltage
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input VIL - - 2 - - 0.5 - 0.5 - 0.5 V
Voltage
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level Output VOH VIH or VIL -0.02 2 1.9 - - 1.9 - 1.9 - V
Voltage
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
CMOS Loads
-0.02 6 5.9 - - 5.9 - 5.9 - V
High Level Output - - - - - - - - - V
Voltage
-4 4.5 3.98 - - 3.84 - 3.7 - V
TTL Loads
-5.2 6 5.48 - - 5.34 - 5.2 - V

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 CD54HC4538, CD74HC4538, CD54HCT4538, CD74HCT4538

DC Electrical Specifications (Continued)

TEST
CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC
VCC
PARAMETER SYMBOL VI (V) IO (mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS
Low Level Output VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V
Voltage
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
CMOS Loads
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low Level Output - - - - - - - - - V
Voltage
4 4.5 - - 0.26 - 0.33 - 0.4 V
TTL Loads
5.2 6 - - 0.26 - 0.33 - 0.4 V
Input Leakage II VCC or - 6 - - ±0.1 - ±1 - ±1 µA
Current A, B, R GND
Input Leakage - 6 - - ±0.05 - ±0.5 - ±0.5 µA
Current RXCX
(Note 6)
Quiescent Device ICC VCC or 0 6 - - 8 - 80 - 160 µA
Current GND
Active Device Current ICC VCC or 0 6 - - 0.6 - 0.8 - 1 mA
Q = High & Pins 2, 14 GND
at VCC/4
HCT TYPES
High Level Input VIH - - 4.5 to 2 - - 2 - 2 - V
Voltage 5.5
Low Level Input VIL - - 4.5 to - - 0.8 - 0.8 - 0.8 V
Voltage 5.5
High Level Output VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V
Voltage
CMOS Loads
High Level Output -4 4.5 3.98 - - 3.84 - 3.7 - V
Voltage
TTL Loads
Low Level Output VOL VIH or VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Voltage
CMOS Loads
Low Level Output 4 4.5 - - 0.26 - 0.33 - 0.4 V
Voltage
TTL Loads
Input Leakage II VCC and - 5.5 - ±0.1 - ±1 - ±1 µA
Current GND
Input Leakage - 5.5 - - ±0.05 - ±0.5 - ±0.5 µA
Current RXCX
(Note 6)
Quiescent Device ICC VCC or 0 5.5 - - 8 - 80 - 160 µA
Current GND
Active Device Current ICC VCC or 0 5.5 - - 0.6 - 0.8 - 1 mA
Q = High & Pins 2, 14 GND
at VCC/4
Additional Quiescent ∆ICC VCC - 4.5 to - 100 360 - 450 - 490 µA
Device Current Per (Note 7) -2.1 5.5
Input Pin: 1 Unit Load
NOTES:
6. When testing IIL the Q output must be high. If Q is low (device not triggered) the pull-up P device will be ON and the low resistance path
from VDD to the test pin will cause a current far exceeding the specification.
7. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

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 CD54HC4538, CD74HC4538, CD54HCT4538, CD74HCT4538

HCT Input Loading Table

INPUT UNIT LOADS

All 0.5

NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g.

360µA max at 25oC.

Prerequisite for Switching Specifications

25oC -40oC TO 85oC -55oC TO 125oC

PARAMETER SYMBOL VCC (V) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS

HC TYPES

Input Pulse Widths tWH, tWL

A, B 2 80 - - 100 - - 120 - - ns

4.5 16 - - 20 - - 24 - - ns

6 14 - - 17 - - 20 - - ns

R tWL 2 80 - - 100 - - 120 - - ns

4.5 16 - - 20 - - 24 - - ns

6 14 - - 17 - - 20 - - ns

Reset Recovery Time tREC 2 5 - - 5 - - 5 - - ns

4.5 5 - - 5 - - 5 - - ns

6 5 - - 5 - - 5 - - ns

Retrigger Time trT 5 - 175 - - - - - - - ns

(Figure 11)

HCT TYPES

Input Pulse Widths tWH, tWL

A, B 4.5 16 - - 20 - - 24 - - ns

R tWL 4.5 20 - - 25 - - 30 - - ns

Reset Recovery Time tREC 4.5 5 - - 5 - - 5 - - ns

Retrigger Time trT 5 - 175 - - - - - - - ns

(Figure 11)

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 CD54HC4538, CD74HC4538, CD54HCT4538, CD74HCT4538

Switching Specifications CL = 50pF, Input tr, tf = 6ns, RX = 10KΩ, CX = 0

-40oC TO -55oC TO
25oC 85oC 125oC
TEST
PARAMETER SYMBOL CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS

HC TYPES

Propagation Delay tPLH CL = 50pF

A, B to Q 2 - - 250 - 315 - 375 ns

4.5 - - 50 - 63 - 75 ns

CL = 15pF 5 - 21 - - - - - ns

CL = 50pF 6 - - 43 - 54 - 64 ns

A, B to Q tPHL CL = 50pF 2 - - 250 - 315 - 375 ns

4.5 - - 50 - 63 - 75 ns

CL = 15pF 5 - 21 - - - - - ns

CL = 50pF 6 - - 43 - 54 - 64 ns

R to Q tPHL CL = 50pF 2 - - 250 - 315 - 375 ns

4.5 - - 50 - 63 - 75 ns

CL = 15pF 5 - 21 - - - - - ns

CL = 50pF 6 - - 43 - 54 - 64 ns

R to Q tPLH CL = 50pF 2 - - 250 - 315 - 375 ns

4.5 - - 50 - 63 - 75 ns

CL = 15pF 5 - 21 - - - - - ns

CL = 50pF 6 - - 43 - 54 - 64 ns

Output Transition Time tTLH, tTHL CL = 50pF 2 - - 75 - 95 - 110 ns

4.5 - - 15 - 19 - 22 ns

6 - - 13 - 16 - 19 ns

Output Pulse Width τ CL = 50pF 3 0.64 - 0.78 0.612 0.812 0.605 0.819 ms
RX = 10k, CX = 0.1µF
5 0.63 - 0.77 0.602 0.798 0.595 0.805 ms

Output Pulse Width Match, - - - ±1 - - - - - %

Same Package
Power Dissipation Capacitance CPD CL = 15pF 5 - 136 - - - - - pF
(Notes 8, 9)

Input Capacitance CI CL = 50pF - 10 - 10 - 10 - 10 pF

HCT TYPES

Propagation Delay tPLH

A, B to Q CL = 50pF 4.5 - - 55 - 69 - 83 ns

CL = 15pF 5 - 23 - - - - - ns

A, B to Q tPHL CL = 50pF 4.5 - - 55 - 69 - 83 ns

CL = 15pF 5 - 23 - - - - - ns

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 CD54HC4538, CD74HC4538, CD54HCT4538, CD74HCT4538

Switching Specifications CL = 50pF, Input tr, tf = 6ns, RX = 10KΩ, CX = 0 (Continued)

-40oC TO -55oC TO
25oC 85oC 125oC
TEST
PARAMETER SYMBOL CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS

R to Q tPHL CL = 50pF 4.5 - - 40 - 50 - 60 ns

CL = 15pF 5 - 17 - - - - - ns

R to Q tPLH CL = 50pF 4.5 - - 50 - 63 - 75 ns

CL = 15pF 5 - 21 - - - - - ns

Output Transition Time tTLH, tTHL CL = 50pF 4.5 - - 15 - 19 - 22 ns

Output Pulse Width τ CL = 50pF 5 0.63 - 0.77 0.602 0.798 0.595 0.805 ms
RX = 10k, CX = 0.1µF

Output Pulse Width Match, - - - - ±1 - - - - - %

Same Package
Power Dissipation Capacitance CPD CL = 15pF 5 - 134 - - - - - pF
(Notes 8, 9)

Input Capacitance CI CL = 50pF - 10 - 10 - 10 - 10 pF

NOTES:
8. CPD is used to determine the dynamic power consumption, per one shot.
9. PD = (CPD + CX) VCC2 fi ∑(CL VCC2 fO) where fi = input frequency, fO = output frequency, CL = output load capacitance,
CX = external capacitance VCC = supply voltage assuming fi « -I-
τ

Test Circuits and Waveforms

tr = 6ns tf = 6ns tr = 6ns tf = 6ns

VCC 3V
90% 2.7V
INPUT 50% INPUT 1.3V
10% GND 0.3V GND

tTHL tTLH tTHL tTLH

90% 90%
50% 1.3V
INVERTING 10% INVERTING
10%
OUTPUT OUTPUT
tPHL tPLH tPHL tPLH

FIGURE 6. HC AND HCU TRANSITION TIMES AND PROPAGA- FIGURE 7. HCT TRANSITION TIMES AND PROPAGATION
TION DELAY TIMES, COMBINATION LOGIC DELAY TIMES, COMBINATION LOGIC

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 CD54HC4538, CD74HC4538, CD54HCT4538, CD74HCT4538

Typical Performance Curves

HC4538 - TA11646C HCT4538 - TA13646C

0.70 TA = 25oC 0.70 TA = 25oC

10kΩ, 10nF
0.69 0.69
K FACTOR

K FACTOR
10kΩ, 100nF 10kΩ, 10nF
100kΩ, 100nF
10kΩ, 100nF
100kΩ, 100nF
0.68 0.68
100kΩ, 10nF

100kΩ, 10nF
0.67 0.67

2 3 4 4.5 5 5.5 6 2 3 4 4.5 5 5.5 6

VCC, DC SUPPLY VOLTAGE (V) VCC, DC SUPPLY VOLTAGE (V)

FIGURE 8. K FACTOR vs DC SUPPLY VOLTAGE (VCC) - V FIGURE 9. K FACTOR vs DC SUPPLY VOLTAGE (VCC) - V

104
HC/HCT4538 TA = 25oC
1.3 VCC = 5V, TA = 25oC RX = 10kΩ
trr, TYP MIN RETRIGGER TIME (ns)
1.2

1.1 103
K FACTOR

1.0

0.9
VCC = 4.5V
0.8 2kΩ 102
10kΩ VCC = 5V
0.7
100kΩ
0.6

10 102 103 104 105 10 102 103 104

CX, TIMING CAPACITANCE (pF) CX, TIMING CAPACITANCE (pF)

FIGURE 10. K FACTOR vs CX FIGURE 11. MINIMUM RETRIGGER TIME vs TIMING

CAPACITANCE

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 CD54HC4538, CD74HC4538, CD54HCT4538, CD74HCT4538

Power-Down Mode
During a rapid power-down condition, as would occur with a An alternate protection method is shown in Figure 13, where
power-supply short circuit with a poorly filtered power supply, a 51Ω current-limiting resistor is inserted in series with CX.
the energy stored in CX could discharge into Pin 2 or 14. To Note that a small pulse width decrease will occur however,
aviod possible device damage in this mode, when CX is ≥ and RX must be appropriately increased to obtain the origi-
0.5µF, a protection diode with a 1 ampere or higher rating nally desired pulse width.
(1N5395 or equivalent) and a separate ground return for CX
should be provided as shown in Figure 12.

VCC VCC

IN5395
OR RX RX
EQUIVALENT
2(14) 16 2(14) 16

+ 51Ω
CX
≥0.5µF
CX
≥0.5µF
1(15) 8 1(15) 8

FIGURE 12. RAPID POWER-DOWN PROTECTION CIRCUIT FIGURE 13. ALTERNATE RAPID POWER-DOWN PROTECTION
CIRCUIT

10
 PACKAGE OPTION ADDENDUM

www.ti.com 14-May-2022

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

5962-8688601EA ACTIVE CDIP J 16 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8688601EA Samples
& Green CD54HC4538F3A
CD54HC4538F ACTIVE CDIP J 16 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 CD54HC4538F Samples
& Green
CD54HC4538F3A ACTIVE CDIP J 16 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8688601EA Samples
& Green CD54HC4538F3A
CD54HCT4538F3A ACTIVE CDIP J 16 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 CD54HCT4538F3A Samples
& Green
CD74HC4538E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC4538E Samples

CD74HC4538EE4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC4538E Samples

CD74HC4538M ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4538M Samples

CD74HC4538M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4538M Samples

CD74HC4538M96E4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4538M Samples

CD74HC4538M96G4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4538M Samples

CD74HC4538ME4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4538M Samples

CD74HC4538MG4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4538M Samples

CD74HC4538MT ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4538M Samples

CD74HC4538NSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4538M Samples

CD74HC4538PW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4538 Samples

CD74HC4538PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4538 Samples

CD74HC4538PWRG4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4538 Samples

CD74HC4538PWT ACTIVE TSSOP PW 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4538 Samples

CD74HCT4538E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT4538E Samples

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 14-May-2022

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

CD74HCT4538M ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4538M Samples

CD74HCT4538M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4538M Samples

CD74HCT4538MT ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4538M Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 14-May-2022

OTHER QUALIFIED VERSIONS OF CD54HC4538, CD54HCT4538, CD74HC4538, CD74HCT4538 :

• Catalog : CD74HC4538, CD74HCT4538

• Automotive : CD74HC4538-Q1, CD74HC4538-Q1
• Military : CD54HC4538, CD54HCT4538

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Military - QML certified for Military and Defense Applications

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CD74HC4538M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HC4538NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD74HC4538PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HC4538PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HCT4538M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC4538M96 SOIC D 16 2500 340.5 336.1 32.0
CD74HC4538NSR SO NS 16 2000 356.0 356.0 35.0
CD74HC4538PWR TSSOP PW 16 2000 356.0 356.0 35.0
CD74HC4538PWT TSSOP PW 16 250 356.0 356.0 35.0
CD74HCT4538M96 SOIC D 16 2500 340.5 336.1 32.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
CD74HC4538E N PDIP 16 25 506 13.97 11230 4.32
CD74HC4538E N PDIP 16 25 506 13.97 11230 4.32
CD74HC4538EE4 N PDIP 16 25 506 13.97 11230 4.32
CD74HC4538EE4 N PDIP 16 25 506 13.97 11230 4.32
CD74HC4538M D SOIC 16 40 507 8 3940 4.32
CD74HC4538ME4 D SOIC 16 40 507 8 3940 4.32
CD74HC4538MG4 D SOIC 16 40 507 8 3940 4.32
CD74HC4538PW PW TSSOP 16 90 530 10.2 3600 3.5
CD74HCT4538E N PDIP 16 25 506 13.97 11230 4.32
CD74HCT4538E N PDIP 16 25 506 13.97 11230 4.32
CD74HCT4538M D SOIC 16 40 507 8 3940 4.32

Pack Materials-Page 3
 PACKAGE OUTLINE
NS0016A SCALE 1.500
SOP - 2.00 mm max height
SOP

8.2 SEATING PLANE

TYP
7.4
A PIN 1 ID 0.1 C
AREA
14X 1.27
16
1

10.4 2X
10.0 8.89
NOTE 3

8
9
0.51
16X
5.4 0.35
B 0.25 C A B 2.00 MAX
5.2
NOTE 4

0.15 TYP

SEE DETAIL A
0.25 0.3
GAGE PLANE 0.1

0 - 10
1.05
0.55 DETAIL A
TYPICAL
(1.25)

4220735/A 12/2021

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

www.ti.com
 EXAMPLE BOARD LAYOUT
NS0016A SOP - 2.00 mm max height
SOP

16X (1.85) SEE

SYMM DETAILS

1 16

16X (0.6)

SYMM

14X (1.27)

8 9

(R0.05) TYP

(7)

LAND PATTERN EXAMPLE

SCALE:7X

SOLDER MASK SOLDER MASK METAL

METAL OPENING OPENING

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220735/A 12/2021

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
NS0016A SOP - 2.00 mm max height
SOP

16X (1.85) SYMM

1 16

16X (0.6)

SYMM

14X (1.27)

8 9

(R0.05) TYP (7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:7X

4220735/A 12/2021

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
PW0016A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1

2X
5.1 4.55
4.9
NOTE 3

8
9
0.30
4.5 16X 1.2 MAX
B 0.19
4.3
NOTE 4 0.1 C A B

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE
0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220204/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

www.ti.com
 EXAMPLE BOARD LAYOUT
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220204/A 02/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220204/A 02/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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