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Lab 08

The document describes a lab experiment on flip flops and counters. The objectives are to test different modes of a JK flip flop and design a modulo-4 asynchronous up counter using JK flip flops. The theory section explains flip flops, JK flip flops, and digital counters including synchronous, asynchronous, and modulus counters. The simulation and experiment sections involve simulating different flip flop designs and building a modulo-4 counter using JK flip flops. Questions at the end involve drawing timing diagrams for the modulo-4 and modulo-5 counters.

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Aleena Khalid
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90 views16 pages

Lab 08

The document describes a lab experiment on flip flops and counters. The objectives are to test different modes of a JK flip flop and design a modulo-4 asynchronous up counter using JK flip flops. The theory section explains flip flops, JK flip flops, and digital counters including synchronous, asynchronous, and modulus counters. The simulation and experiment sections involve simulating different flip flop designs and building a modulo-4 counter using JK flip flops. Questions at the end involve drawing timing diagrams for the modulo-4 and modulo-5 counters.

Uploaded by

Aleena Khalid
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Lab#08: Flip Flops

Student Name: ……Shehroz K.………….. Class/Section: ……BS CYS II……………


Week: ………………
Registration no: …………223609………….
Date: …25/05/202………

8.1 Objectives

After completing this lab, you will:


● To test different modes of JK Flip Flop

● to design modulo-4 Asynchronous UP Counter using JK FF

8.2 Theory

Flip Flop
A flip-flop circuit can maintain a binary state indefinitely (as long as the power is delivered to the
circuit) until directed by an input signal to switch states. The major differences among various types
of flip-flop are in the number of inputs they possess and in the manner in which the input affect the
binary state.

JK Flip-Flop
JK flip-flop is an edge triggered device. A typical JK flip flop has three input: J, K and a clock input.
The flip flop can be either positive or negative edge triggered. The output Q is available in
complemented form as well.
Besides the usual inputs and outputs, most of the flip flop IC also possess two asynchronous inputs,
namely preset and Clear. These inputs are usually active low. If used Preset and Clear inputs keep
the flip flop in set and reset state respectively, irrespective of the other inputs. Both of these inputs
cannot be used simultaneously, otherwise they will bring the flip flop in unstable state.

Figure 9.1 : Symbols of JK Flip Flop


7473/7476 Dual JK Flip Flop
Both the Ics 7473 and 7476 are similar in functionality except for one difference. The flip-flops in
7473 have only one type of active low asynchronous input, which is Clear input, whereas the flip-
flops in 7476 have both Preset and Clear inputs. Both these Ics have negitive edge triggered flip-
flops. Refer to Appendix A for IC Pin configuration and function of various Pins of this IC is
described below,
8.2.1 1CLK, 2CLK: Negitive edge triggered clock inputs for FF1 and FF2 respectively
8.2.2 1PRE,2PRE(7476 only): Active low preset inputs for FF1 and FF2 respectively.
8.2.3 1CLR.2CLR: Active low clear inputs for FF1 and FF2 respectively.
8.2.4 1J,2J: Active high J inputs for FF1 and FF2 respectively.
8.2.5 1K,2K: Active high K inputs for FF1 and FF2 respectively.
8.2.6 1Q,2Q: Active high outputs for FF1 and FF2 respectively.
8.2.7 1Q’, 2Q’: Active low outputs for FF1 and FF2 respectively.
8.2.8 VCC and GND:Supply connection lines

Digital Counters
A digital counter is a set of flip-flops whose states change in response to pulses applied at the input
to the counter.Every counter resets after a certain number of clock pulses. Thus, as it name implies,
a counter is used to count pulses.An n stage counter can count up to a maximum of 2 n states, n is
equal to the number of flip-flops required for the construction of counter.

Modulus Counters
The number of input pulses that causes a counterto reset to its initial count is called the modulus of
the counter. Thus, the modulus equals to total number of distinct states(counts), including zero that
a counter can store. A binary counter with n stages is a modulo-2 n (or MOD-2n) counter. The largest
count a mod-N counter can achieve is N-1, i.e a mod-N counter never reaches the binary number
equal to its modulus, N is always equal to or less than 2n.

Counters can be classified as,


● Synchronous Counter, which are clock driven. All the flip-flops are driven by a single
clock.
● Asynchronous Counter, which are event driven. Clock input is given to the first flip-flop
only. Rest of the flip-flops are driven by their preceding flip-flops.

MOD-4 Asynchronous UP Counter


The number of flip-flops required to construct a mod-4 counter is 4. This counter will count from 0
to 3, a total of 4 distinct states.
8.3 Simulation using Verilog HDL

a) Simulate the Design Modules for D, S-R, J-K and T Flip-Flops.


b) Also perform test bench for D, S-R, J-K and T Flip-Flops.

D Flip Flop
SR Flip Flop
JK Flip Flop
T Flip Flop
8.4 Experiment

Components and Apparatus Required

5. Digital logic trainer board


6. Logic Probe
7. Connecting Wires
8. Following ICs and their datasheets or pin configuration
● 7473/7476 JK Flip Flop
Experiment #01: 7473/7476 Dual JK Flip Flop
8.4.1 Make VCC and GND supply connections.
8.4.2 Connect the CLK input to some clock source or a switch.
8.4.3 Apply different combinations of 1s and 0s at inputs J, K, Preset and Clear.
8.4.4 Observe the output and record your observation in the following table
CLK PRE* CLR J K Q
↓ 1 1 0 0
↓ 1 1 0 1
↓ 1 1 1 0
↓ 1 1 1 1
↓ 1 1 1 1
↓ 1 0 1 1
↓ 0 1 1 1
1 1 1 1 1

*Ignore if 7473 IC is being used.

Experiment #01: MOD-4 Asynchronous Counter


8.4.5 Make Connections as shown in the figure below,
8.4.6 Observe the binary values at outputs of two flip flops with incoming clock pulse.

8.5 Exercise

Question#01: Draw the timing diagram for MOD-4 counter designed in this lab
Question#02: Simulate MOD-5 asynchronous counter using any simulation tool. The number of flip-
flops required to construct a MOD-5 counter is 3. This Counter will count 0 to 4 , a total of 5 distinct
states. Since a 3-stage counter can count up to 8 states at maximum, a NAND gate is used to reset it
after 5 clock pulses. Attached hardcopy of the simulated circuit.

Question#03: Draw the timing diagram for MOD-5 counter simulated in question#02,
Lab Evaluation Session
Tota Obtain
Assessment Comments if Any
l ed
s
Mar Marks
ks

Simulation 2

Experiment 4

Knowledge 2

Presentatio 2
n

Marks 10

Instructor Signature: _

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