INDIAN INSTITUTE OF INFORMATION TECHNOLOGY SENAPATI MANIPUR

Mantripukhri, Imphal – 795002, Manipur, India, www.iiitmanipur.ac.in

Department of ECE, EC101 - Digital Design, 1𝑠𝑡 Sem: ECE & CSE
End-Semester Examination, 70 Marks, Date: 06/04/2022, Time: 10:30 AM to 01:30 PM

Name: Roll No:

1. Design and implement a 4 bit parallel adder/subtractor using two’s compliment technique. In the case of
subtraction consider A<B and A>B. Hint: C𝑖𝑛 = 0 for addition, C𝑖𝑛 = 1 for subtraction

i. Obtain the truth table for full adder and full subtractor. [4]
ii. Implement a full adder using only 9 two input NAND gates. [3]
iii. Consider a full adder symbol as shown in Fig. 1 in addition to few logic gates for implementing a 4 bit
parallel adder/subtractor with a C𝑖𝑛 as a control signal. [8]

A B

Full Adder
Cin C

Figure 1: Full adder symbol and its internal logic circuit is equivalent to 1(ii)

2. A lawn sprinkling system is controlled automatically (according to the data provided by the different sensors)
by certain combinations of the following variables.
Season (S = 1, if summer ; 0, otherwise), S - Whether forecasting sensor
Moisture content of soil (M =1, if high ; 0, if low), M- Soil moisture measurement sensor
Outside temperature (T = 1, if high ; 0, if low), T - Temperature sensor
Outside humidity (H =1, if high ; 0, if low), H - Humidity sensor

The sprinkler is turned on (logic function F = 1) under any of the following circumstances:

1.�The moisture content is low in winter.

2.�The temperature is high and the moisture content is low in summer.
3.�The temperature is high and the humidity is high in summer.
4.�The temperature is low and the moisture content is low in summer.
5.�The temperature is high and the humidity is low.

i. Obtain the truth table for logic function F. [5]

ii. Find the simplest possible logic expression for F involving the variables S, M, T and H for turning on the
sprinkler system and implement the logic expression using two input NAND gates [5]
iii. Implement the logic function F using 4:1 Mux with the help of additional gates. [2]
iv. Implement the logic function F using 2:1 Mux with the help of additional gates. [3]

3. Design and implement a logic circuit as shown in Fig. 2 to display your roll number (Example: EC21010205)
on seven segment display when the BCD code (0 to 9) is given as the input. (Note: Consider 10 to 15 as a
don’t care conditions ”X”)

i. Construct the truth table as per the table shown in Fig. 3. [4]

1
 EN

Common
BCD Cathode
PROM Seven
Counter
Segment
Display

Figure 2: Digital Logic Circuit

ii. Design and implement a asynchronous BCD counter (Mod-10 counter ) using negative-edge triggered JK
flip-flops. (Note: Initially, Q𝐴 Q𝐵 Q𝐶 Q𝐷 are at 0 0 0 0 and flip-flops are having two extra control signals
one is Clear - Active low and another one is Preset - Active high)[4]
iii. Finally, implement a digital logic circuit using PROM and what will be the data in each memory location
of PROM for displaying your roll no on SSD. [3]
iv. The size of the PROM. [1]

l BCD Outputs Hexa

i ma Roll
c Decimal
De No
A B C D EN a b c d e f g
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 1 0
6 0 1 0 1
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1

Figure 3: Truth Table.

2
4. A logic circuit output is 1 when the 4 bit binary input ABCD is equivalent to a decimal number that is multiple
of 2. Don’t consider 0 as a multiple of 2.
i. Show the truth table to represent the above logic. [3]
ii. Obtain a minimal sum of product (SOP) expression using K-map. [2]
iii. Realize the reduced SOP expression using only NAND gates. Both 2-input and 3-input NAND gates are
available. [3]
iv. Implement above logic circuit using 4:1 MUX. [3]
5. Design and implement a 4 bit synchronous counter/shift-register using PROM as shown in Fig. 4 to generate
a random sequence as given in Fig. 5. There are four control signals in addition to clock signal (Clk): A reset
signal (𝐶𝑙𝑟̄ - Active low), parallel load (Load - Active high), a counter enable signal (C𝑛 - Active high), and a
signal to indicate whether the counter should count up or count down (Up/𝐷𝑛). ̄ ̄ 2. Load, 3.
Priority: 1. 𝐶𝑙𝑟,
C𝑛 and 4. Up/𝐷𝑛. ̄

Outputs
Inputs Cn Up/Dn DA DB DC DD
.
. Load
.
.
PROM .
. Clr
. 4-bit counter/shiftregister
.
Clk

QA QB QC QA

Figure 4: PROM and 4 bit synchronous counter/shift-register.

i. Construct a characteristic table expressing relation between present state and next state including control
signals. [6]
ii. Design and implement digital logic circuit using PROM for generating a random sequence as shown in
Fig. 5. [4]
iii. What is the size of the PROM? [1]
iv. Define PLA and PAL. [2]

0 8 2 4 6 7 12

15 13 14 5 3 11 10

Figure 5: Random sequence.

3
6. Consider the Pseudo Random Generator given in Fig. 6 and generate a binary sequence of bit patterns. Initial
bit pattern is 0101. [4]

DA DB DC DD
CLK
QA QB QC QD

Figure 6: Pseudo Random Noise Generator.

Note: ”All the Best”.