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This script sets up the search paths and libraries for a Cadence RTL Compiler synthesis run. It reads in the HDL file "counter.v", sets timing constraints and clock parameters, synthesizes the design, and writes out reports and output files.

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Animesh Jena
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22 views1 page

Script

This script sets up the search paths and libraries for a Cadence RTL Compiler synthesis run. It reads in the HDL file "counter.v", sets timing constraints and clock parameters, synthesizes the design, and writes out reports and output files.

Uploaded by

Animesh Jena
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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######################################################

# Script for Cadence RTL Compiler synthesis


# Erik Brunvand, 2008
# Use with syn-rtl -f rtl-script
# Replace items inside <> with your own information
######################################################

# Set the search paths to the libraries and the HDL files
# Remember that "." means your current directory. Add more directories
# after the . if you like.
set_attribute hdl_search_path {/home/buet/project11/rtl}
set_attribute lib_search_path {/home/buet/project11/libs}
set_attribute information_level 7 /
set_attribute library {slow.lib}
read_hdl -v2001 {counter.v}

set myFiles [list counter.v] ;# All your HDL files


set basename counter ;# name of top level module
set myClk clk ;# clock name
set myPeriod_ps 10000 ;# Clock period in ps
set myInDelay_ns 0.1 ;# delay from clock to inputs valid
set myOutDelay_ns 0.1 ;# delay from clock to output valid
set runname synthesis_report ;# name appended to output files

#*********************************************************
#* below here shouldn't need to be changed... *
#*********************************************************

# Analyze and Elaborate the HDL files


read_hdl ${myFiles}
elaborate ${basename}

# Apply Constraints and generate clocks


set clock [define_clock -period ${myPeriod_ps} -name ${myClk} [clock_ports]]
external_delay -input $myInDelay_ns -clock ${myClk} [find / -port ports_in/*]
external_delay -output $myOutDelay_ns -clock ${myClk} [find / -port ports_out/*]

# Sets transition to default values for Synopsys SDC format,


# fall/rise 400ps
dc::set_clock_transition .4 $myClk

# check that the design is OK so far


check_design -unresolved
report timing -lint

# Synthesize the design to the target library


synthesize -to_mapped

# Write out the reports


report timing > ${basename}_${runname}_timing.rep
report gates > ${basename}_${runname}_cell.rep
report power > ${basename}_${runname}_power.rep
report area > ${basename}_${runname}_area.rep

# Write out the structural Verilog and sdc files


write_hdl -mapped > ${basename}_${runname}.v
write_sdc > ${basename}_${runname}.sdc

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