This script sets up the search paths and libraries for a Cadence RTL Compiler synthesis run. It reads in the HDL file "counter.v", sets timing constraints and clock parameters, synthesizes the design, and writes out reports and output files.
This script sets up the search paths and libraries for a Cadence RTL Compiler synthesis run. It reads in the HDL file "counter.v", sets timing constraints and clock parameters, synthesizes the design, and writes out reports and output files.
This script sets up the search paths and libraries for a Cadence RTL Compiler synthesis run. It reads in the HDL file "counter.v", sets timing constraints and clock parameters, synthesizes the design, and writes out reports and output files.
This script sets up the search paths and libraries for a Cadence RTL Compiler synthesis run. It reads in the HDL file "counter.v", sets timing constraints and clock parameters, synthesizes the design, and writes out reports and output files.
# Erik Brunvand, 2008 # Use with syn-rtl -f rtl-script # Replace items inside <> with your own information ######################################################
# Set the search paths to the libraries and the HDL files # Remember that "." means your current directory. Add more directories # after the . if you like. set_attribute hdl_search_path {/home/buet/project11/rtl} set_attribute lib_search_path {/home/buet/project11/libs} set_attribute information_level 7 / set_attribute library {slow.lib} read_hdl -v2001 {counter.v}
set myFiles [list counter.v] ;# All your HDL files
set basename counter ;# name of top level module set myClk clk ;# clock name set myPeriod_ps 10000 ;# Clock period in ps set myInDelay_ns 0.1 ;# delay from clock to inputs valid set myOutDelay_ns 0.1 ;# delay from clock to output valid set runname synthesis_report ;# name appended to output files
#********************************************************* #* below here shouldn't need to be changed... * #*********************************************************
