Lab 6: TTL logic family.

Electrical parameters
and output types.

Contents
1. Objectives

2. Material

3. Pratical development

3.1 Static behaviour

3.2 Special outputs
3.2.1 Tristate
3.2.2 Open collector

1. Objectives
To study a representative example of bipolar logic family: the TTL (Transistor-Transistor
Logic).
The family study was performed using TTL chips, a prototype board and the necessary
electronic instrumentation.
The chips used belong to the subfamilies LSTTL (Low-power Schottky TTL) and
ALSTTL (Advanced Low-power Schottky TTL).

2. Material
 TTL family
o Integrated circuits and components:
 Resistors: 1kΩ, 22kΩ
 LED diode.
 74LS04 (six totem-pole TTL inverters)
 74LS05 (six open-collector TTL inverters)
 74ALS125 (four TTL tristate buffer)
 Inteconnection wires

Datasheet of integrated circuits (uploaded in PoliformaT)

o Instrumentation:
 Power supply, digital multimeter.
o Prototype board

1
3. Practical development
3.1 Static behaviour
Before to start…

Set the voltage of power supply to 5V and the current limited to 50mA.

Logical levels

(i) Assemble the circuit of Figure 1 (a). Connect the power supply to the 74LS04
chip (0V and +5 V), and select one of the six inverters inside the chip (See the data
sheets of chip in PoliformaT).

+5V
+5V

Vi 74LS04
Vi 74LS04
Vo 1K
Vo V

(a) (b)
Figure 1. Circuit to monitor the output logic levels of LSTTL gates. (a) With the
multimeter. (b) With a LED display.

(Suggested assembly for figure (1a))

Set the input voltage (Vi) to high level. You only have to connect a wire from Vi to
Vcc (+5 V). Measure the output voltage (Vo) with a digital multimeter as shown in
the figure.

2
 Set the input voltage (Vi) at low level, changing the connection and joining Vi to GND
(0V). Measure again the output voltage Vo.

Complete the table, writing down the obtained values. These are values of typical
output voltages of the gate without any load (not connected to any output).

Vi = “1” = Vcc VOL = 0.15V

Vi = “0” = 0V VOH = 4.46V

Check that the outputs are in the correct range. In the data sheets we can see the
LSTTL voltage limits (for limit conditions in the load, temperature and
manufacturing):

VOH min = 2.7V, VOLmax = 0.5V, VILmax = 0.8V, VIHmin = 2.0V

(ii) Calculate the noise margin of LSTTL family.

Vohmin - VIHmin = 2.7V - 2.0V = 0.7V
NMH = ___________

NML = ___________
VILmax - VOLmax = 0.8V-0.5V=0.3V

NM = ____________
min(NML, NMH) = 0.3V

(iii) Assemble the circuit of Figure 1 (b) to monitor the logic levels using a LED.
Observe what is the logic level at the output ("0" or "1") that makes the LED to
bright. LED shines for 1 on input(so 0 on output)

(iv) Analyse how the output voltage is variable depending on the output current.
This can be done by connecting load resistors RL of different values, between the
output and Vcc (+5 V) and between the output and ground (0V) as shown in Figure 2
(without the LED diode).

Measure Vo for each RL filling in the following table:

+5V +5V
IOH 1k: 3.38V
1k: 4.74V 2.2k: 3.46V
2.2k: 4.8V Vi = ‘1’ RL Vi = ‘0’ 22k : 3.7V
22k : 4.87V 74LS04 74LS04 RL

VOL VOH
IOL

Figure 2. Circuit for analyzing the variation of the output voltage depending on the
output current.

3
 RL between Vo and VOL RL between Vo and 0V VOH
+5V
22kΩ 22kΩ
1kΩ 1kΩ

Note that a lower RL implies greater output current IO, and vice versa.

In the assembly of the left IOL is varied. Verify that increasing IOL, VOL increases, ie. VOL
is worse. In the assembly of the right, IOH is varied. Verify that increasing IOH, VOH
decreases, ie. VOH is worse.

This explains why in the Datashets the manufacturer specifies a maximum output
currents (IOHmax, IOLmax) to ensure voltage logic levels.
Look for these values in the data sheets of 74LS04

16
IOLmax = mA IOHmax= -0.4 mA

4
3.2 Special outputs: tristate and open collector

The tristate and open collector outputs let you connect multiple outputs together,
which can not be done with normal (totem-pole) outputs, as it can cause logic
conflicts and degradation of the logic gate by excessive current.

Here are some examples of assemblies with special outputs.

3.2.1 Open collector outputs

Carry out the assembly of Figure 3. The 74LS05 chip consists of 6 inverters with
open collector outputs (see data sheets in PoliformaT). Note the presence of the
pull-up resistor RPU, external to the chip, and connected between the common
output and Vcc.

NOTE: Note that the chip will also have to be connected to the power supply,
although not indicated in the figure for simplicity.

+5V

22k

A 1/6 74LS05

B 1/6 74LS05

Figure 3. Connection of two open collector outputs

(i) Vary the voltage value at the inputs A and B: "0" = 0V, "1" = 5V, and complete
the following truth table, measuring the voltage VF with a digital multimeter:

VA(V) VB (V) VF(V)

0 0 4.96V
0.15V
0 5
5 0 0.15V
5 5 0.15V

Indicate the expression of F in terms of the inputs:

NOT(A+B)
F = ________________

5
Check that the output F is the AND-wired of the outputs. This means the output
connection works as an AND of the outputs, without adding any new gate.

(ii) Remove the Rpu resistor and its connection to +5V, leaving the outputs
connected together. Fill again the following table:

VA(V) VB(V) VF(V)

0 0 0.04V
0 5 0.146V

5 0 0.145V
5 5 0.151V

What do you observe? Why is it necessary the Rpu resistor?

Because without it we can't get HIGH level
on the output

3.2.2 Tristate outputs

Tristate outputs have, as the name suggests, 3 states: the usual "0", "1", and a
special state, the high impedance (Hi-Z), which corresponds to the output
unconnected. By a control terminal (ENABLE), you can select the normal mode or
Hi-Z. This allows sharing a common output (BUS mode), provided that, at any given
time, all outputs except one are in Hi-Z.

(i) To show the operation of tristate outputs, make the assembly of Figure 4,
corresponding to a simple 2x1 Multiplexer. It consists of 2 tristate buffers belonging
to a chip 74ALS125 (See PoliformaT data sheets), and enabled to low level.
Please note that only one integrated circuit must be used in the assembly of
the left, and that the right figure shows only the simplified scheme.

ENABLE signals S and /S (S inverted) are complementary and can be generated by

connecting them directly to 5V and GND, or vice versa. They can also be generated
using a 74LS04 inverter chip.

S is the multiplexer selection signal, responsible for activating one of the two input
channels, A or B.

NOTE: Please note that the chips must be connected to power supply, even if
not shown in the figure.

6
 S

A ¼ 74ALS125
A
F F
Mux 2x1
¼ 74ALS125
B B

/S

Assembly to perform Scheme of the multiplexer

Figure4. 2x1 Multiplexer using con 2 tristate gates

Set A and B to two different logical values, for example: A = '1 '(+5 V) and B =
'0' (GND).

Set S = "1" and /S = "0". What logical value do we have in F? Why?

I get 0 on output because A is
connected to 0

Set S = "0" and /S = "1". What logical value do we have in F? Why?

I get 3.76V on output because B is connected to 5V and its ENABLE is connected to 5V
meanwhile ENABLE of A to 0V

Why there is no logical conflict in F between the outputs of the two buffers?
because we only use one gate at the time and the other one is in
high impedance state

Could we do the same assembly with a 47LS04 chip? Why?

we couldnt because the current from one gate would be flowing to the ouput of the other gate, we
need the high impedance state