Insights on a SYSTEMCONTENTS Chapter 1 i INTRODUCTION TO EMBEDDED SYSTEM 1 Embedded System Overview 1.2. Classification of Embedded System: Classification Based on Generation. Classification Based on Complexity and Pence 1.3. Hardware and Software in a System... 14 Purpose and Application of Embedded Systems. 1.4.1 Purpose of Embedded Systems. 1.4.2. Applications of Embedded Systems... 1.2.1 Chapter 2 HARDWARE DESIGN ISSUES Combination Logic............ 2.1.1 Basic Combinational Logic Design 2.1.2 RT-Level Combinational Components.......... 2 Sequential Logic... _ RT Level Sequential Components 2 Sequential Logic Design... Custom Single-Purpose Processor Design... 2.3.1 Steps for Designing Single-Purpose Processor... 232 233 22.1 20 Design Example of a Single-Purpose Processor..22 RT Level Custom Single- Purpose Processor Design... Optimizing Custom Single-Purpose Processors. Solution to Important Questions... Practice Design Questions... z a Chapter 3 3.1 SOFTWARE DESIGN ISSUES Basic Architecture. 3.2. Operation 3.3. Programmer’s View .. 3.4 Development Environment .... 3.4.1 Tools for Implementation and Verification Phase....54 3.4.2 Design Flow. = 3.5. Application-Specific Instruction Set Processors... 3,6 Selecting a Microprocessor ......c. 3.7 General-Purpose Processor Design .. Chapter 4 MEMORY 4.1 Introduction... 4.2. Memory Write Ability and Storage Permanence 43 Common Memory Types ... 4.4 Composing Memory... 4.5. Memory Hierarchy and Cache . 4.5.1. Memory Hierarchy. 45.2. Cache Memory... Chapter 5 INTERFACING 5.1 Communication Basics.. 5.2 Microprocessor Interfacing . 5.2.1. VO Addressing... 5.3 5.4 5.2.2. 5.2.3. Direct Memory Access - DMA controller Interrupts — Interrupt Driven I/O .. Arbitration ..... Multilevel Bus Architectures ......7.2 Open-Loop and Closed-| 109) LAB n Principles. ¥ cation anced Communicatto Iso oe id Wireless Protocols ..- 5.6 Serial, Parallel an aaa REAL TIME OPERATIN' in | 6.1 Operatin; stem Basics..." 6.1.1. The Kemel 2 6.1.2, Real Time 6.1.3. Kemel Space and User S 6.14, Types of Kemel «-- Task Process and Threads . 6.2.1 Process 62.2. Threads. 63. Multiprocessing and Multitasking 63.1. Context Switching. 6.3.2. Types of Multitaskin; Task Scheduling... Task Synchronization... 6. 65.2. Task Synchronization Techniques. Device Drivers... Solution to Important Questions.. Chapter 7 Task Communication/Synchronization Issues... 6.6 CONTROL SYSTEMS 7.1 Introduction ..158| 158 woe 158) 159 of Open-Loop and Closed Loop ems... = Loop Control Systems Overview Open-Loop Control Systems . 72.2 Closed-Loop Control Systems... 723 Comparison Control Syst 7.21 160 13 7.2.4 Open and Closed Loop Control System Design Example . General Control Systems and PID Controllers .. 73.1 Control Objectives. ee 7.3.2. Modeling Real Physical Systems...... 7.3.3. Controller Design Software Coding of PID Controller .. PID Tuning... ee rere ecetieeeeeeer 176 7.6 Practical Issues Related to Computer-Based Control ....176 7.1 Benefits of Computer-Based Control Implementation...178 Chapter 8 IC TECHNOLOGY 8.1 Introduction. 8.4 8.1.1 IC Manufacturing Process 8.1.2 Photolithography...... Full-Custom (VLSI) IC Technology Semi-Custom (ASIC) IC Technology 8.3.1 Gate Array Semi-Custom IC Technology .. 8.3.2 Standard Cell Semi-Custom IC Technology Programmable Logic Device (PLD) IC Technology . Solution to Important Questions... Chapter 9 MICROCONTROLLERS IN EMBEDDED SYSTEMS oO 9.2 93 Intel 8051 Microcontroller Family, its Architecture and Instruction Sets... Assembly Language Programming. = 9.2.1 Assembly Language Programming Format 9.2.2 Delay Calculation in Assembly Program...... Interfacing with Seven Segment Display Solution to Important Questions.Chapter 10 VHDL 10.1. Introduction .. 10.2. VHDL Code Structure. 10,3. Data types, Data Objects and Operators... 10.4 Statements in VHDL... 10.5. Standard Architectures 10.6 FSM Design. Solution to Important Questions... INTRODUCTION TO EMBEDDED SYSTEM Embedded System Overview Classification of Embedded Systems Hardware and Software in a System Purpose and Application of Embedded Systems Embedded System Overview Introduction ‘An embedded system is a combination of hardware and software designed to perform a specific function. The hardware consists of mechanical parts and electronic circuits while the software represents the program instructions that cause embedded system to operate its functionality. The programs written for the embedded ‘systems can also be referred as firmware which is stored in read-only memory. An example of embedded system can be a digital watch. A digital watch with simple configuration can contain 4-bit processor, registers, counters, real-times clocks as electronic components. And other hardware elements of the watch can be buttons/touch screen for inputs and screen & speaker for output. Embedded systems are used to control, monitor or assist the operation of an equipment, machinery or plant. So, an embedded system may be designed for specific control functions within a larger system, often with real time computing constraints. Hence, in many cases, an embedded system is a component within some larger system. For example, modern cars contain embedded systems like ‘embedded airbag system, navigation system, adaptive cruise control, and few others left unmentioned. Characteristics i. Single functioned: As embedded systems are designed for specific control functions, it usually executes a specific program to carry out the specific function repeatedly. Tightly constrained: In a way, tightly constrained means ‘optimizing the embedded system in various system defining Introduction to Embedded System [1]5 0UUtt™”™” sans of few attributes, an embedded ayy] sire, fast enough to Process day, inimum power. , parameters. In tel must be economic, small i? ume mi general, embedded systems my, ‘in the system’s environment a real time and must const Reactive and real time: |" change’ rocessing without delay. A delay | J may result a fallure in yy, ili. continually respond t0 must perform instant da‘a P computation and slow respons operation of the system: 3. Design Metrics Adesign metrics cost, time for implementation and safe a measurable feature of the system's performancy ty, etc. Some of the common) used metres include: i. NRE cost (non-recurring engineering cost): It represents the monetary cost for designing the system: Since the cost doesn, ‘occur more than once for a particular system, it is termed ag nonrecurring Unit cost: itis the monetary cost of manufacturing each Unit of the system excluding NRE cost. | Size: It is the physical space required by the system. For | software itis measured in terms of bytes and for hardware iti, measured in terms of no of gates or transistors. iv. Performance: |t is measured in terms of the execution time of the system. | Power: The amount of power consumed by the system, which | may determine the lifetime of a battery, or the cooling | requirements of the IC. vi. Flexibility: The ability to change the functionality of the system without incurring heavy NRE cost vi ie to prototype: The time needed to build a working version Of the system, which may be bigger or costlier than the final system implementation, m" Time to market: The time required to develop a system to th point that it can be released and sold to customers, a ix. Maintainability: The ability t cr Y to modify the system after it initial [2| Insights on Embedded System a an check the functionality throughout the Correctness: We © process of designing the system and we can insert test circuitry to check that manufacturing was correct i, Safety: The system is supposed to cause no harm: ‘The Time to Market Design Metric .m to the marketplace significantly lity, The market window, period sales, for products is getting Introduction of an embedded syste affects the overall system profitabil during which the product have highest Shorter, soa short delay on introduction of product to the marketplace can render huge loss. Using a simplified model of revenue a5 shown in the figure below, we will deduce the loss of fevenue that can occur due to delayed entry of @ product 9 the market. Peak Revenue | A a aye / me Na AN \A_ 4 rt Figure 1-1: Market window and simplified revenue model for loss calculation for delayed entry Time” st occurs at the halfway ‘This model assumes the peak of the marke 3k is same for delayed point, denoted as W, of the product life. The peal entry, The revenue for an on-time market entry is the area of the triangle labeled On-time, and for delayed entry is the area of triangle labeled Delayed. The difference between the areas of two triangles gives the revenue loss for a delayed entry. On time - Delayed x 100 venue Loss = Revenue Loss ontine 1 ‘Area of on time triangle =~ x base x height 1 =p xaxwxwxtanB (Assuming, market rise angle is B) ition to Embedded System 131 introducee: i ee te 0)x (WD) tang ‘Assuming B = a, and on solviNB we get, p3W Ue pevenue loss = ag? * 1008 ded system ~ A Digital Camera AA digital camera can be taken 3 embedded system as it per, only a single function of capturing image. It is tightly Constraineg is affordable, portable, and consumes less power. And as it is enough to process numeral images '" milliseconds, it exhibite time feature, But however, 2 simple digital camera may not po«, high degree of reactive attribute. On the contrary, few contempoy, digital cameras are capable of detecting human expressions. 4, Example of an Embed Classification of Embedded Systems Embedded systems can be classified using various aspects jy functionality, application, generation, and compleaity & performance, we will discuss the categorization of embedded systems based 9, generation and complexity & performance in this section. 1.2 1.2.1 Classification based on Generation 1. First Generation Embedded systems were designed using 8-bit microprocessors or 4, bit microcontrollers. Hardware circuits were simple and the firmware was developed using assembly code. Motor controller using 8085 can be taken as an example of first generation embedded system. 2. Second Generation The systems were built using 16-bit microprocessors and 8/16-bit Heese More complex and powerful instructions were| a for the designer to work with. Some systems involved | ae systems for their operation. Data Acquisition example of second generation embedded systems. 3. Third Generation | The systems were desig ence cero) ee microcontrles. long wth complex and power stacey instruction sets, A 14] Insights on Embedded System 41.2.2 Classification Based on Complexity and Performa 1. better performance. introduced for ation ne operating system implement ion, Also, the concept instruction pipelining was Dedicated embedded real tim was another important feature in this generat nal Processors (0SP) of application specific processors like Digital S18 (asic) came into and Application Specific Integrated Circuits existence Fourth Generation Fourth generation was marked with the 3 ‘ors and multicore processors. These yedded dvent of System on Chips (s0C), reconfigurable process embedded systems used high performance real time emb operating systems for its operation. ince ‘Small Scale Embedded Systems ‘are designed with a single S-bit or 16-bit These systems ). They have little microcontroller (8051 family, PICL6F8X, Hitachi H8) hardware and software complexities and involve board level design. ‘They may be battery operated. While developing embedded software for these system, an editor, assembler and cross assembler specific to the microcontroller or processor are used as the main programming Usually C language is used for developing these systems tool. jor a robotics ‘Automatic vending machine, stepper motor controller f system, etc. can be the examples of small scale embedded systems * Medium Scale Embedded Systems 16-bit or 32-bit These systems are designed with a single or few Reduced microcontrollers (B051MX, PIC16F876) or DSPs or suction Set Computers (RISCS). It may also employ the readily Instr wus functions, for available single purpose processors and IPs for vario ‘example: bus interfacing, encryption, deciphering and so on. These systems have both hardware and software complexities. For software design, the programming tools used is RTOS, source code engineering tool, simulator, debugger, and integrated development environment (IDE). Software tools also provide the solutions to the hardware complexities. Some of the examples of medium scale embedded systems are computer networking systems, signal tracking system, ete : Introduction to Embedded System 51 ————16] Insights on Embedded System Sophisticated Embedded systems or Large Embedded Systems ’ ve enormous hardware and SOFtWArE COMpoy, ‘and may need scalable processors OF configurable processors programmable logic arrays. Thev are used for “cutting applications that need hardware 3nd software co-design integration in the final system. They aF6 constrained by rir hardware units. Certain softy, hardware to obtain additg, These systems ha' rh processing speeds available in t functions are implemented in the speed by saving time. Some of the functions of the hardwa resources in the system are also implemented by the software, Th, systems generally implement high performance real time operat; system. Development toois for these systems may not be reag) 1 available at all. In so available at a reasonable cost or may not b cases, a compiler or retargetable compiler might have to developed for these. (A retargetable compiler is one that configura, according to the given target configuration in a system). Embeddeq System for wireles LAN & for convergent technology devices i ong of the sophisticated embedded systems. Hardware and Software ina system Single Purpose Processor Single purpose processor (SPP) is a digital circuit designed to a exactly one program. In other words, it is a circuit that represents al Program or functionality of a specific task. So, it does not require 4 Program memory in its configuration. In general, SPPs are used for simple and less computation intensive operations in which stored | Program concept Is not required. Hence, this simple dedicated task oriented configuration makes SPPs small in size and cons | Power for operation. However, SPP lacks flexibility as mae 7 Configuration cannot be used to perform operations other ha a n the specified one. — =| aa Lvs | register I Functionelll| | Units Data Memory oe J Figure 1.4: Block diagram of a single purpose processor The single purpose processor contains controller, datapath and data memory. Controller is used to generate control signals to carry out operations in datapath. The datapath contains only the essential components for the specified task. And SPP contains data memory for temporary storage during computation. DMA controller can be taken as the examples of single purpose processor. General Purpose Processor ‘The general purpose processor (GPP) is a programmable device that supports wide range of functionality. The required functionality is the processor's. memory. carried out by programming Microprocessors are the examples of general purpose processor GPPs are highly flexible as it supports change of functionality based ‘on requirement to the extent that the given configuration of the processor supports the operation. For complex and high computational operations, GPP can be effective as majority components of the system will be in operation. However, for simple operations, memory access will cause the operation to become slow and additional components might increase power consumpt introduction to Embedded System |7Datapath | Controller | | _—__— rm | [contol | | Register || togicand | | uo | state | | (ream | bata | Memory | Memory Ls Figure The general purpose processor includes controller, and program memory. Block diagram of a general purpose processor datapath, day ‘Controller: Iti used to generate control signals based on the ‘struction provided in the program memory. It consists o fatuction register (R) and program counter (PC). IR is used t hold the instruction that needs to be executed and PC is use to sequence through the instructions. “| Prograr a oram memory ie Program cannot be built or converted valent digital circuit in ger ee Beneral purpose processors unknown. Hence, prograr instructions Y 40 fun on the processor wil be ‘memory is used to store program fii. General Datapath: the ¢. handle a variety of computations a large register file and one arithmetic logic units (ALUs) 3. Application Specific Processors Application specific processors are progr Sota eramMmable ed for a particular class of applications. i alee erally includes s 18] Insights on Embedded System _ program memory, optimized datapath and special functional units These processors provide optimum level of performance maintaining appropriate sie and power consumption. Microcontrollers for controlling application and digital signal processors (DSPs) for huge data processing application are examples of application specific processors, Controller Datapath Control | Logic and | | Registers state | register | | | Custom | | ALU im |[ ec | x a) v ] Program Dae | Memory | Figure 1.6: Block diagram of an application specific processor 1.4 Purpose and Application of Embedded Systems The main purpose of an embedded system is to automate the human driven activities such that the task can be performed with higher reliability and efficiency. And regarding the application of embedded system, it has a wide range of application that varies from consumer electronics to industrial equipment, entertainment to academic devices and medical instruments to weapons and aerospace control systems. 1.4.1 Purpose of Embedded Systems 1, Data collection in embedded systems, the data is collected from other external devices for storage, analysis, manipulation or transmission. Data may be in analog or digital form. Systems working with digital data require analog to digital converters if the collected data is in analog form to Embedded System 9]can be used for meaningful purpose baseq 7 data The colected i. Fr instance, a digital," edded syste! functionality of the emb | ides graphical repres collects data, stores it and finaly ProW pt tay data inthe form of captured image: 2. Data communication ‘An embedded system is requ which may be at close vicinity or at remote location, communication between devites can be done via wired line m, Ne, or wireless medium. Embedded systems are incorporated 4, different wireless modules or wire-line modules for communicay, purpose, For example, if we have to transfer images captured ys, jred to connect (Wo OF more day, camera into Laptop, we can use either WIFI or ser (using data cable) based on which mode of transmission is suppor, by our devices. communica 3, Data Processing The collected data in embedded system is subjected to some sort. processing for which embedded systems are attributed with day processing modules. Speech coder, audio video code, etc can be fy examples of data processing unit. Data processing includes th ‘manipulation of data for appropriate purpose. Monitoring ‘Many embedded systems are incorporated with sensors to check th, State of the different parameters. The parameters can be current voltage, temperature, humidity, etc. which are continuous), monitored and appropriate processing or controlling of devices: Gone. However, the value of the parameters cannot be controlled by the system itself. The values of parameters are used for Controlling purpose or for some graphical representation med simply stored for further analysis and processing nue Control For control purpose, a enti se Te enorme nga eh d jected in i +hange in the desired parameter an: put Port detects the id the actuators at output ports robot, ultrasonic sensor senses the presence of certain kind of object and the motor is rotated accordingly to avoid the collision. Application specific user interface o provide a better user interface based on application has been one of the concerns of contemporary embedded systems. Keypads, simple LCD modules, speakers, etc are basic and common interface for users. However, sensitive touch pad along with high definition display has been the sophisticated interface implemented in current scenario. 1.4.2 Applications of Embedded Systems The applications of embedded systems are: 4. Household appliances: microwave ovens, television, DVD players and recorders. Consumer electronics: camera, video games Office Utility: fax machines, printers, scanners Business equipment: alarm systems, card readers ‘Automobiles: engine controller, fuel injection, antilock brakes Networking: modem, network cards, network switches and routers 7, Medical equipment: MRI scanner, sonography, blood pressure device and glucose test set 8, Security Let us review one example of embedded system related to the household appliances. Microwave Oven: Basically, microwave ovens use electromagnetic waves to generate heat by moving water molecules. When caught in electromagnetic waves, water molecules move very quickly in a counterclockwise then clackwise motion, alternating back and forth at extreme speeds. This movement generates heat energy which causes the food items to warm rapidly The microwave often has a display, keyboard, and a number of sensors and actuators. Sensors can be a temperature sensor or the sensor that detects whether the door is closed. Actuators can be the electronic switch that controls a microwave tube or a system that controls the rotational speed of a turntable within the microwave, Introduction to Embedded System |11|SSE HARDWARE DESIGN ISSUES * Combinational Logic © Sequential Logic + Custom Single-Purpose Processor Design ‘+ Optimizing Custom Single-Purpose Processors Combination Logic Combinational cutis a dial creuit whose output is fonction ofits present inputs. Combination logic circuits are made basic gates or universal gates that are combined or connected t produce more complex switching circuits. In general, logic gotes a buliding blocks of combinational logic circuits. It has no memory bios an TY block, Sy © examples of the combinational circuits are decoder, ™ultpies adder, ROM, ete. len, 2.1.1 Basic Combinational Logic Design |n combinational logic design, output is Purely a function of, Present inputs and has no memory of past inputs. We can use bast og Bates to design combinational circuit. . In such design, outputs are in terms of inputs, ae | 1. General Steps for Combinational Logic Design * The problem description (question) i translated into a tig ‘able with all possible combinations of input values, “The input values ies on the left of the truth table and th Corresponding output values of the in cereponng Puts lies on the right o For each ouput we have to detve the equations, The equation ay contain number of combinations : of the inputs, Th of Combinations depends on the number of high (1) wien al oe “umn of the output, Rows of the ‘inputs are 7 q rive the equation corresponding thd 8 to the high o Column. And the equation must be furtherminimiaeg * — Another: way to derive minimized ec 112] Insights on Embedded System ~ —_ Example 1: simple (when the output column consists of only one high value). # The final equation is translated to an equivalent circut diagram using logic gates. 2, Combinational Logic Design Example In an alarm system of a bank, three sensors are implemented and the alarm is triggered when at least two sensors detect the change. Assuming sensors to output digital values, design a combinational Leta, b,c represent the three sensors and y represents the buzzer for alarm. The output y should be high when two or more than two inputs are high. The truth table and its corresponding combinational design are shown below. Teuth Table KMap be a [etely | N00 on a1 10 ofololo) olofol1{o| olelz{o| slolikala alalebo Y=ac+ be+ab ofa{a]a] Combinational circuit rfojolo bs ¢ ! | Figure 2.3: Truth table, K-map, and combinational circuit for bank alarm system 2.1.2 RT-Level Combinational Components Register-transfer or RT level components are generally used when the design of the circuit becomes complex. As the number of input increase, the complexity of the design increase. One of the ways to reduce design complexities is by using RT-level components. Multiplexers, decoder, adder are the examples of RT-Level Components. Hardware Design Issues |13|—_ bon bk let i 1 | y & Lil Y a a mbit { sy Logia)xn | mat | Decoder ut |] fd Seu | MX | | “ he T 1 5 a , © 0? Opp-r) O10 FY Sum x Y XY | mbit nbitm feSo | Comparator function |S, alu k— Less Equal Greater fn Sen Op Figure: 2-4: Few commonly used RT-evel combinational compone Multiplexer allows only one of its data in a the output. For mx1 multi data output with logym determines which input dat be used for parallel to serial Puts to pass through iplexer, there are m data inputs and o select lines. The value of select q ta to pass throu gh to the 0 I conversion, mat ke Adder is used to add two n-bi with a carry of 1 bit, equal to, or greater th: an another input, function is to be carried out. If there are 2” functions that can be done by ALU then there must be atleast m select lines shifter is another example which is used to shift the bits of the input right or left, It can be used as 2 divider oF multiplier. For example shifting 0110 (6) to the right would give 0012 (3). vi 2.2 Sequential Logic ‘Asequential circuit is @ he present inputs but also the past Tequential logic depends on its present internal state and the present inputs. Hence, 2 sequential logic circuit has some kind of memory. Logic gates ad flipflops ae the basic building blocks ‘of sequential logic circuits. flip-flop isan example of sequential logic circuit. A flip-flop stores le bit, The different types of flipflops are listed below. digital circuit whose outputs are a function of put of not only tt inputs. The outpu' singl D flip-flop: It has two inputs D and clock, when clock is high, value of is stored in flip flop and same will be the value of the output Q. When clock is low, previously stored bit is maintained ignoring the value of input D. ‘SR flip-flop: It has three inputs $ (set), R (reset), and clock. When clock is low, the previously stored bit is maintained ignoring the values of input at S and R. When clock is high, the output varies with inputs S and R. If Sis high, the output Q will be high and hhigh bit (2) will be stored by the flip-flop. IF Ris high, then low bit (0) will be stored, The output will not change if both the inputs are low but the undefined condition will occur if both the inputs are high AK flip-flop: Its operation is similar to that of SR flip-flop but when both the inputs J and K is high, the stored bit toggles either from high to low or low to high 2.2.1 RT Level Sequential Components © Register {A register stores n bits from its n-bit data input which also appears at its output. A register usualy has at least two control inputs, clock and load, For a rising edge triggered register, the inputs-are only stored when load is high and clock is rising from 0 to 1. Another control Hardware Design Issues |15]input clear may be used to resets all bits to 0 rear, 3 afinut, Since all bits of the registers can be storey Sor, ir refer this type of register as a parallel load register, " ary! «Shift Register A sift register stores n bits from its one bit data input, two contol inputs clock and shift. When clock i rising ne « the nth bit of input is stored in the (n-1)” bit, and (n—y' as i is stored in the (n-2)" bit and so on down to the eae Ay stored in the first bit. The first bit is shifted out appear bit ‘output bit. It has one bit output and the input must be pi a the register serially. ifteg iy < Counter Accounter isa r ter that adds binary 1 to its stored bina; general, a counter has a clear, and count as a control input | Qu resets all stored bits to 0 and a count input enables increme ; e ting 4 each clock edge. A common counter feature is both up and « ‘Ounting which required an additional control input to indi i count direction, cate, A small triangle in the sequential logic — ng shift, a sa : => Register bit Shift )unt ‘clear ———_ Register ae mbit he Ts Sp ay op resents the clock input foray Figure 2S: RT-level sequential components 2.2.2 Sequential Logic Design For a sequential logic design, either Moore o Mealy model needs to ial logic design, either be used. However, the design steps remain the same for any m fe 'odel used sed for 1. General steps for Sequential L * Translate the probler Bic Design m descripti iPtion to a state diagram, als also called a finite state machine (FSM) In FSM, each circle re ‘e Assign each state a unique binary valve, «Now, we can have a truth table, wit eee which cause a transition from one state to another are listed next to each arc. and create a truth table for the combinational logic. The external inputs and the bits coming from the state registers are fed to the combinational logic a5 inputs, Whereas, the external output values along with the state bits to be loaded into the state register acts a5 the output of the combinational logic. ‘The output values change only with the current state, so we list the external output values only for each possible state, regardless of the change in external input values. ith the help of which we can proceed with combinational design by generating minimized output equations using K-map. And finaly, drawing the combinational logic circuit. Sequential Logic Design Example Example 1: Design a soda machine controller, given that a soda costs 75 cents and:your machine accepts quarters only. Draw a black-box view, ‘come up with a state diagram and state table, minimize the logic, and then draw the final Solution: The coin must be entered three times to get a soda out of the machine. Throughout the design, Cin represents the coin input and sout indicates the soda output whereas Qi, QO represent current state and I1, 10 represent next state ‘A. Black Box View sodatacrine [224% Controller | Gin Hardware Design Issues |17|‘Eee a. state Table ——T jaeee 1, Datapath Jax ao cin} 10 Sout ‘sit stores and manipulates a system's data. Toyo «sit eontains register units, functional unts ‘and connection units 5 0 like wires & multiplexors. Gh | «The datapath can be configured to read data from particular registers, feed that data through functional uns configured to 2 carry out particular operations like add oF shift, and store the ya ‘operation results back into particular registers. 2 «Examples of data include binary numbers representing external 1 Conditions lke temperature or speed, characters Be displayed [i] \ojelo) 1| ona screen. — 2, Controller It sets the datapath control inputs (like register load and uae At low Truilexor select signals) ofthe register units, functional un endo[olo]i] “on ye o 7 es oon wy ‘and connection units to obtain the desired configuration at 2 selslels Oe eae ede particular time. ieaioo +a satel ata ifofelato : om ee fe croc ucsiorn | Catena «tt monitors external control inputs 2s well as datapath control onal Crest cutputs, known as status signals coming from funcional uns, Qi QO Cin and it sets external control outputs as well. hh External External data a i contains Fi i I a =r (fff \] ion Ce mn LT | cows = rT t=. || Sr 5 (oe) LT De |) Lose 1] a || <= i a soe |) use | A = =p |) P tees \]| = gure 2.6: Soda machi t ime controller | - 2.3 Custom Single-Pu: deen {l A) LA) A basi proces irpose Processor Design —F— : 4 SSOr consists ofa controller and a dat tan —_ Satapath, ntl cams Figure 2.7 Internal view of controller and datapath of single Purpose Processor Hardware Design Issues |19]2.3.1 Steps for Desigt 1. Draw a black box diagram: Black box diagram is ag, external interfaces of a system. It generally includes Smo wy signals along with few control signals. Put an, ” Ni Write the functionality or program: The functionality | r code which provides the solution to the defined problem, tray, The input signals are assigned to a variable. | + Number of temporary variables may be us, requirement. ed bay ‘© The final result is assigned to the output port. 3. Design a finite state machine with data (FSM converted into equivalent complex state diagram wa 3 finite state machine with data. In FSMD, templates - represent : ae various constructs of ‘program. The temple es assignment, branch statement and loop statement are fEMENt are discy, ov, i, Assignme is Aignent eae For this statement, a single state js na representing its action. Generally, a singles. to connect to next state. The templ statement $= A+B is shown as an example, m leary plate used Figure 2.8: Template for assignment sta nt statement Branch stat tement: state ¢, co be tain act - 18 On number of ions. ts t broblem, However, foreach tue copa nations ef template 4 "Yue condition, there cane tn —_ » there can be sever __ ? j 120] insights on Embea, 'S are written a on alon Embedded System a side States representing actions. Condi dition ning Single-PUrpOse Process, TT . h with the arrow that connects the C state and states of ea0 branch. Last states of each branch are connected to the J state. + ¢ a anna carte statements; | 2 1 . | etseif C2) | a a cnher castatements; statements | Statements; Staterett else ia YO ther statements : te for branch statement Loop statement: Its template consists of Condition state State J, and other states representing statements of loop Condition is written alongside arrow connecting condition state snd state of first statement of loop. The last state of loop is aonnected to the J state which is connected back tO condition State. Complement condition is used alongside arrow connecting C state and next statement outside of loop. The plate for the loop statement is shown in the figure below. Figure 2.9: Templat Join temi —— ond c a [onto «| [= ( | wor — Loop statements | Loop statements: LL ) —_—_ Nest statement; }- 4} next statement Figure 2.10: Template for loop statement hh: The datapath is build based on functionality of the Build a datapat! ‘0 considerations system, Following steps are needed to be taken int while developing a datapath. Hardware Design Issues |21|pegoters: The number OF FES to be use | umber of variables used in the functionaf at assigned t inputs, temporary variables ang guy, ty i, Functional units: Blocks representing. aithme . operations are defined within the datapath, ty ii, Connections: The connections among ports functional units are done based on operands assignments and comparison of functionality cog. ah mutiplexor is required when the value in regige assigned from more than one source. The sources my input port, a functional unit, or another register, * Tete, Used jy iv. Control inputs and outputs: Input control signals are required by registers and multiplexor. Register loag used in case of register while selection line Sina Multiplexer. Control output is produced by logical unit datapath. Each control singles are given a unique identifi, 5. Develop a finite state machine (FSM): The states and tran. FSM are same as that of FSMD. However, Seng sitions the complex actions, coneitions of FSMD are replaced by Boolean expressions Using control signals defined within datapath. For eve operations (assignment statement, arithmetic {oad signal is asserted and corresponding activated TY register statements), regi 1 Multiplexor selection ling if there are two or more sources for a given register. y the logical operations are replaced by 'y the control signals of | Corresponding functional block, 2.3.2 Design Example ofa Single-Purpose Processor oo | Design a single purpose processor that calculates the greates lates a (GED) of two __and FSM in the design, Solu - Initially, the black box view dia the functionality which is templates, gram is drawn and they « N followed by ‘onverted into FSMD usin, '8 appropriate [221 insights on Embedded system Figure 1 < 5N0 n. Black Box View: 1 —— | to we 4 ke a xin vie | * Lee GcD 2: -¢ a. Functionality Code ‘ cnet | nie | else | ) 9: [ dows outs: tI = ) _| ~— GCD processor functionality and FSMD diagram of GCD Pp! : ; he datapath, we need to .d, functional blocks for it, and control lines for 21 Datapath for GCD processor: To. construct t! ire determine the number of registers requ! operations, mux and connection requiremen register and mux. dyin assigned to variables sx in an registers: Two inputs x d_out), and leave ee register d for generating output signal (4 and use Be 1s are used. Hence, three regi are required. ee -y and x0} m=m*X; nen-4; ) pout = m; Figure: The black box view, fanetionait, and FSMD for processor that calculates x" Hardware Design Issues 31]eee epee oxen Nile i sxe problem 2: Design a single purpose processor that generates Fibonacci series up to m places. Start with 2 function that computes desired result, rnstate the function into a state diagram, sketch 2 probable ind draw FSM diagram. [2075 Baishakh] tra Figure: Datay J ipath of the Processor that calculates x to th 1 Dower n FSM of the processor that cater ‘ulates x to the power n E Functionality Code int fr st, nt, count, n; while(2)( while(!g0_in); swhile(count <= n){ © Lout= ft; t= ft + st; st counte+; Figure: Fibonacci series generator ~ the black box view, functionality gem the bl i 7 . functionality a — Hardware Design Issues |33]D. _ Datapath of the processor that generates Fibona, 1h) ad) oe (a) om ae count) Figure: Datapath for Fibonacci series generator E. FSM controller for Fibonacci series generator vous or ono 1000 on | Figure: FSM of Fibonacci series generator 134] Insights on Embedded System a a Sey, Problem Design a dual-purpose processor that calculates the median and variance of 5 numbers entered by the user by showing the algorithm, FSMD, FSM, datapath and controller design. (2073 Magh] solution: A. Black Box | ain bincindmem | | | een rmed_out var out 8. Functionality Code int may, ofS MD; float ma, 5, VR: wilt whilst); whi <5 esto bate ) m= sis; 520,19 while <5) tl =m seseett ’ R= 9/4, MO = a2 ‘m_out= MD, v_out= VR; Figure: FSMD of processor that calculates the median and variance Hardware Design Issues [35]1. Datapath Figure: Datapath to calculate the median and variance of five number, FSM Figure: FSM of the processor that calculates the me numbers 136] Insights on Embedded System | ian and variance of ive problem 4: Design a single purpose processor that checks whether an integer 'S prime number or not. Include FSMD, datapath, and FSM in the [2076, Bhadra) sta na eee |e Prime —4 pout sunctionalty Code wate wits: 0, int wie ioe) cnet , peleth pout= ) u — Figure: FSMD to check whether a number i prime or not ——— Hardware Design issues 1371 ees0 0 Figure: Datapath and FSM to check whether a number is prime or not not ‘138| Insights on Embedded System FSM rm problem 5: Design a single purpose processor that calculates factorial of an ‘sar integer. Include FSMD, datapath, and FSM in the design. = 1. — solution: ‘A. Black Box View 1) pin nin Factorial fout [2073 Magh] qT 18, Functionality Code nen wile(2) while ¢0_in) fea; while(m> 0} Figure: The black box view, functionality and FSMD for processor that calculates factorial of an integer. | Hardware Design Issues |39]patapath for the processor that a problem 6: ea culates factorial of ay pevelop algorithm, soluti A. Black Box tiiit ain bin cin din sat draw the state diagrar datapath of a custom single purpose processor that largest of four integers. Propose the block diagram m, and design the determines the of its controller 2073 Bhadral [MAX OF FOUR NUMBERS Figure: Datapath ofthe proceso to caalate the factorial of an inte nce E. _FSMof the processor that calculates factorial of an integer value I 2. Functionality Code x00 int max, 4], | sen wilt . whilst); 7 (01 = a in; es inf] = b_in; nl2] = cin; 6 oe als=4 Lato mat ; max (0); 7{ max= li _ isk; while(i <4) wu ‘An > max) oun max= ni) = ) = im.out= max, — : , 10[ moter om #—— | Figure: pune _ igure: FSM controler y Figure: The black box view, functionality and FSMD for processor that iar Cl ‘calculates maximum of four numbers. Hardware Design Issues 141]eel fo] bet] bet] bee] Become Figure: Datapath to calculate maximum of four numb ers EB FSM of the processor that calculates maximum of four numb, rs, 142| Insights on Embedded Syster m ] problem 7: ine the sum of digits of mnction computing the [2076 Baishakh] esign a single purpose processor to determ ger. Start the design from the fu an inte and controller. desired result, FSMD, datapath c. FSMD start uM OF DIGITS | s.out 8. Functionality Code ints wie hielo 50; white(ao r=n%0; seste n=n/10; s.out= 5; Hardware Design Issues (4314 —_— D. Datapath of the processor that calculates sum of qi ligits value. a) practice Design Questions Design a single purpose processor for the foll the design from the function computing the datapath and controller lowing problems. Start desired result, FSMD, « todetermine the largest among three numbers sto calculate the multiplication table of integer n upto For example; if n= 4 and m = 15 then we need to generate the multiplication table of 4 from 1 to 15 consecutive computation® to generate the sequence: 1,5, 10, 17, 26 upton terms to check whether an integer number is perfect or not. (A ._FSMof the processor that calculates sum of digits of an inte, number is said to be perfect, if the sum of all the factors “BEF Vale ‘excluding the number itself equals to the original number.) [—_} 9, Design a dual purpose processor forthe following Problems start the design from the function computing the desired result, FSMD, Figure: Datapath af the processor to calculate sum of digits of an intege, % 7 datapath and controller Use optimization wherever appiabie. me «stocaleulate the area and perimeter of an rectangle on « todetermine the smallest and highest of three numbers - «sto determine the maximum and minimum of five integers i «so caleuate the sum of odd its ofan integer And aso check whether the calculated sum is even or 0d. oi: «te caleulate the factorial of an integer and als check whether oe the number is prime or not sn wa uf Figure : FSM controle to calculate sum Sum of digits of an it 144] Insights on Embedded System - CEE Value ———ardware Design Issues 1451 aome SOFTWARE DESIGN ISSUES asic Architecture «Operation + Programmer's View + Development Environment + Appicaton-Specfc Instruction Set Processors ‘+ Selecting @ Microprocessor + General-Purpose Processor Design 3.1. Basic Architecture general-purpose processor is a programmable digital syst, tem, consists of a datapath and a controller which are tightly linkeq Wi ‘memory. Figure 3.1 shows the various components in the architecturg. rey general-purpose processor. | Processor | Control Unit. | Datapath Control/Status Figure 3.1: Basic architecture of generat cessor Purpose pro cessor 461 Insights on Embedded System - err Datapath Datapath consists of the circuitry for transforming data and for temporary data storage. It contains an arithmetic‘ogic unit which manipulates data through various operations such as addition, subtraction, logical AND, logical OR, rotating, shifting, etc. ALU alse generates status signals to represent various conditions such a5 ¢4°"¥- zero, sign, parity and so on, Such information is stored in status register. pata path contains registers to store temporary data and different status generated by operations. The temporary data may be the data from memory for ALU to process, or the data that needs to be moved from one memory to another memory, or the data from ALU that needs further processing by ALU or needed storage. For data transfer within datapath, internal bus is used. But movement of data from and to memory is done by external bus. Control Unit The control unit consists of circuitry to general control signals to carry out various operations. It consists of controller, program counter (PC), and instruction register (IR) Controller consists of a state register and control logic. It sequences ‘through the states and generates the control signals to read instructions into the instruction register, and control the flow of data between ALU, registers of datapath and memory. Controller also determines the next value of program counter. For non-branch instruction, the value of program counter is incremented. But for branch instruction, status signals from datapath and content of instruction register are evaluated for next address of program counter, Program counter is used to hold the address of the next program instruction to be fetched, while an instruction register is used to hold the fetched instruction. The bit width of program counter indicates the address size of memory which in turn can be used to determine the number of directly accessible memory locations. For example, 2 16-bit PC represents address sive of 16 bits and 2° = 65536 addressable memory locations. Software Design Issues |47|Memory Memory is Information ¢3° thats sss rentectures based ON Progra “4 to store information for medium , i gata ov proram. Program information "ty ay sed to carry out desired function’ Dat rious purposes, information used fe two memory 3 ‘There at H Princeton Architeg _Princeton Architecay. Harvard ArchtertU emory Data. and program program mk memory space 4 mance: Data and Data and instructions cam) fetched fetched simultaneously space 2. Improved perfor instructions canbe simultaneously 2 Feresres move connecting wires requires Iss connecting y) ™ c-; — eee. n 4 Block Diagram Block Diagram ae i + i} Processor Processor | Program Data Memory. Memory | | Memory (Program and Data) 3.2 Operation 1. __ Instruction Execution Instructions are the s 1 functio are the sets of code that carry out particular functi For each instruction, the controller sequences through 8 tion, lk igh several stag Each stage ma stages or more clock 7 Fetch instruction: The next instructor ee instruction register from me 'mory where instruction resides i li, Decode instruction: instruction in represent vario the instruc /arious operations based on op cod tion register may and ay include to be executed is loaded nO: The address of the ven ‘ven by program counter, 148] Insights on Embedded System ~ eVWreseeee register or memory as operands. In this stage, the operation i bbe done by the instruction is determined Fetch operand: fan be a register or memory. In operations including registers, the required data are loaded into registers as specified by the instruction. i ‘or a given operation, operand c Execute operation: The ALU handles the arithmetic and logical operations defined by the instructions. The loaded registers are fed to the inputs of ALU to carry out the operation. Store results: The destination to store results may be either register or memory. After the execution of operation, the final data is loaded into register or memory as defined by the instruction. Pipelining Pipelining is implemented to increase the throughput of the system in pipeline, the given task is divided into various stages and multiple stages which are independent of each other are executed simultaneously. For efficient instruction pipeline, different stages must be of almost same length and each instruction must require same number of cycles to complete its execution. Branching instructions can be an obstacle for efficient pipeline as next instruction to be executed will only be known after execution stage of branch instruction. This problem, however, can be addressed using various techniques. One simple method is to stall the pipeline when there is an occurrence of branching instruction. The pre-fetch cf next instructions is not done in this method rather waited for execute stage to complete first. Another popular method is to use branch prediction. inthis method, the branch is guessed and the next instruction is fetched correspondingly. If the guess is correct, then it results in efficient pipeline. But, however, if the prediction is not correct then all pre-fetched instructions in the pipeline must be ignored. The following diagram shows af example of an instruction pipeline having five stages.Fetch nstetion Decode fetch overands sxecute sore Resut — \ 3.2 Fight iructons in execution using insrocton Pay Figure: tion pj in Figure 32, there are & instructions in the pipeling instruction divided into five stages and each requiring — ' complete, In absence of pipeline, the total time requireg tod ight instructions would be 8x5 = 40 clock cycles, assum stage to complete in one cycle. However, with ‘ implementation, the total completion time required is a cycles. In this way, pipeline helps to improve the performance, system. % 3. rentretied Very Long Instruction Word vy Muttiple ALU architecture is implemented in sees co the performance of the mend srsens an nae oo: ‘more scalar operations in parallel, yj, pees sre Of ALU in the processor. It may reqy one fares multiple independent instructions th usly. Instructions in such systems are ordered statical (during runtime), architecty 'y (at compile time) or dynamic) Very long instruction word (VLIW) 7 ) a Superscalar architecture oon teeta 8 type of stat Contains multiple independe, instructions 3. ‘3 Programmer's View Instruction Set 1 set is a list of instructions which represent arried out by the t be aware of the ‘he instructio the bit igurations for operations that can be © cont mmer mus processor. Assembly language progra available instruction set, Since embedded system design may ‘equ programmer of some portion of assembly code to be written, le for the embedded system must know the instruction set availabl processor they are working on. ‘ode and operand field Every instruction, in general, consists of op-c jone. An operand field ‘p-code field specifies the operation to be d specifies the location of actual data that takes part in an operation. ‘The number of operands per instructions varies among processors and its instruction type, Addressing modes are used to represent data location and its accessing mechanism. The simple instruction format is shown in the figure below. Figure 3.3: Simple two address instruction format Commonly used addressing modes are explained in the following paragraph, Immediate Addressing Mode: The operand field contains the actual data. Register Direct Addressing Mode: The operand field contains the address of the register. And the register contains the actual data. © Register In the address of a register, which in turn cont address of the actual data in memory. ‘The operand field contains the ion. The direct Addressing Mode: The operand field contains tains the effective Direct Addressing Mode: effective address of operand that is used in operat ‘actual data is available in the memory. «Indirect Addressing Mode: The operand field contains the address of a memory location, which in turn contains the ‘address of a memory location where actual data 's available. Software Design Issues 151]Implicit OF Implied Addressing Mode: The ., used in this mode: the register to be usey eneral, acct in defined implicit In B ‘uMulator jg Useq ‘st register. as % + Displaceme' particular register redex addressing, index registers are used, whet addressing, value of operand is added to the cur, determine the actual address. e the operations of few addressing modes can be vig, aly nt Addressing Mode: The operany ‘ i is to obtain the effective address 0, nt ag following igure. Ares Made _Operand Field Immeiate eg | Fier Direc RegsterAderess +» egies ares Dre Indie grams must be writy (on-chip memor limits. For example, | "Y for program and data a be abl exces le to wri ed the memory limit. "te the code efficiently so as not) within the 1@ defined mer micrcontealers, the onehiy ne fixed. So, one should Available Registers int. eee ructured language gisters used for st be id register 8 is not required for st various special function re tion, and interrupts MU! accumulator an programmer. However, configuring timers, serial communica known to every programmer Input Output Facility Every processor facilitates programm communicate with external devices. must be alert about the number of inpu rallel /O, port can be read OF sister. Also, communications ¢2” th address and data pprts can be ‘er with input output pins t programmer working with processors ft output pins available and their functions. In p: written to using specific function rej be done through system bus in whicl activated by certain instructions. Interrupts Interrupt is a fat serves the device which requires processor to suspend execution of cilty provided to the user in which the processor 13 urgent attention. It causes the current program and starts that does the function required by ‘executing interrupt service routine t! mer should the device which interrupts the processor. The program be aware of the types of interrupts supported by the processor and ferrupt service routine when required, must writs Operating System ‘An operating system is a layer of software that provides low-level services to the application layer. Few services involve loading and ‘executing of programs, sharing and allocating system resources, and synchronization mechanism. Another important service is process scheduling in which the high priority process is executed first. Other services include handling hardware interrupts, and provide device drivers. High level applications invoke operating system When a program requires service from operating system, it generates .d software interrupt that is served by the operating system, Values required to the services are typically passed as the parameters. in the program. CPU registers are involved for information exchange among application programs and operating using system call. a. predefines system. Software Design Issues |53]34 Development Environment Processors along with dierent development t00Is are. development of software or an embedded system. Processoy thatig fy, write and debug the program is commonly referred as “dove ot processor”. Desktop computer can be taken as an example of deve Drocessor. Such processors may not be a part of embeddeg ™, implementations. But the processor in which our program is jg" referred as "target processor’. AVR, 8051, PIC microcontroliers 4, 8086 microprocessor can be few examples of target proceso, ; Processors are always a part of system implementations. Various, Se ‘ol the software development as well as embedded systems Aevelopmen described inthe following paragraphs. ‘ 3. 1 Tools for Implementation and Verification Phase 1. Tools for Implementation Phase During the implementation phase, we need tools to convert hy ‘eveloped code into machine readable code Assembler ms, Assembler converts assembly instructions to binary machin Instructions it replaces op-code and operand mnemonics i, binary equivalent. It also translates symbolic labels Tito.actuy addresses, It generates an equivalent binary code for. a singe machine instruction, soit follows one to one mapping principle Compiler Compiler converts high level programs to machine programs Each high-level constructs may be translated to several machine instructions. Hence, it may not follow one to one mapping principle. Cross compilers are those compiles which run on one Processor but generate the code for a processor with different architecture. Linker Linker combines objet files into a single executable fle, oy another object file. it allows creation of a prog ram in separately assembled or complied fils. t combines machine inshenaye of user code and instructions from standard library, 154] Insights on Embedded System —~ ‘Tools for Verification Phage busin VEEN Base, He eed gy 18 OF device tne code BeMerated for target pry O Hever totes 4 whether Ber the required functionality ot Works, as Debugger Debuggers are programs th; targeted program, These are processor but execute code simulates the function of 4 evaluation and correction processor. These debuggers a simulators (ISS) oF virtual debuggers is fast as compar is coded and tested in deve can, however, lead to inace actual system. 3 9 Used to test an Programs that run on Aesigned for target he Target processors and slows Gf programs. in development e also known as instruction set ‘machines (VM). Design cycle for 640 other tools, since the program opment processor. But, these tools ‘UTACY a5 it does not interact with the id debug the evelopment Processors it Emulator Emulator can be a hardware or software that enables one system to behave like another system. it consists of debugger coupled with a board connected to development grocessr, The board consists of target processor or device similar to target processor and support circuitry. it supports debugging of program while it executes on target processor. It also enables cone to control and monitor the program's execution in actual ‘embedded system circuit. Since the code must be downloaded into emulator hardware in each test, the design cycle is lite longer compared to debugger. But it leads to accurate testing as it interacts with the rest of the system components as wel Device programmer Device programmers are the devices with the help of which binary machine programs are loaded into target processor's memory. Using this tool, the program can be tested in Ee realistic form which results in high accuracy as program mason actual system. The design cycle, however, is longest since : removed from the system, programme: te prowrammer the system. If the device using programmer and returned to ———— rs Software Design Issues [55]ST — ; Le mmer can be made incbuild within the system, the er Me prot duced cycle will Bee 3.4.2 Design Flow software OF implementation and verification various implementation tools SUC verification tools such as debugeerr programm mm development Process ng ly systet , implementation 4 Pha phase. During hh as assembler, compiler are Useq ,* er are used in Verity’ ti phase 1. Software Development Process vara software development, the development PrOcesSOr 25 wey a the target processor may be common And the development tg, are available in a single package which is referred as “Integray, Development Environment (IDE)". = ee iif Compiter/assembler ane ae Object File [ ovject Fe. ( Beecutable Program insenenatontmse | etennise | Mtware development process ne Figure 3.8: 2. Implementat In Phase: Source code i ‘mo is written using an edi a the ee is compiled/assembled using corse aden inally, with the help of link linker all re final executable file. aurea tes iler/assembler. are combined into a 156] Insights on Embedded System verification Phase: The executable file is run und ler the command Mya debueser. All possible inputs, especially bo eed to check the behavior of program, parents can be used for 2 ° vetormance analysis of the program. Time and , F Pin be analyzed. Time complexity includes durat pace complexity carga were Pace COMPLY ne bration of execution of ory usage. gpmbedded System Development Process embedded system design In case of are different the i egos ate afte ines al ayes The mpted pevelopment Environment (IDE) tools for various ecewens are Prmilable for implementation phase, Though the ieee ris phase 0° embedded system is similar to that ene implementation phase, the verification phase differs drastically eee ooo Ny. Implementation Phase | — x Editing w/Assembiing Linking Compl Verification Phase ase > | ure 3.6: Embedded system development process ‘of editing, compiling/ me as that of software Implementation Phase: The process assembling and linking the program is sa development process. However, development processors use cross compilers or cross assembler. As those compilers run on evelopment processor, for example PC, and generate the file for target processor, for example hex file for microcontrollers. ee Software Design Issues 1571 almm works in Conjure, embedded syste ' Vunctig, phase: yas with real time enViron me, M F ny wires control over time and €nVito, Mh gebugging # PrOIT gd availablity, debuggers, emulatg quirement * ysed for verification. Code 5," ent processor using debuggers or coxe, ding into ‘emulator hardware. Also, PrORramy tbe checked by foe" . code directly into the target processo, 4 the + ction Set Processors specific instru instruction set processors Fe SPECIFIC ty 4 they can be programmed baseq meal oe which makes it more flexible. Also Oth constants Such 35 ever, instruction set processor and its associat, bahaonen fala are expensive to develop. It can be categorized 4, microcontrollers, digital signal processors and less general applicatig specific instruction set processors. 35 Application Application-specific 1. Microcontrollers Microcontrollers are specific to applications that perform a large amount of control oriented tasks. The following are few general features of microcontrollers ‘+ It includes several peripheral devices such as timers, analog to digital converters, serial communication devices, and so on, It generally contains program and data memory on the same IC. Various peripherals along with memory incorporated within the same IC result in compact and low-power implementation. 't provides the programmer direct access to number of pins of the IC. Access to pins enable programmer to interface with other devices such as sensor, actuators, LCDs, and other different devices that may be used in the system, Some specialized instructions may be avalble. Such faci improves the performance of the system. cam Digital Signal Processors (DSP) These are processors which af 158) Insights: Wy captured by a camera, voice packet through a network router, a clip played by an instrument. Few features, out of many, are ye may contain numerous register fies, memory blocks, +O itipliers and other arithmetic units, m i facilitates with instructions that are applicable uniquely to + igital signal processing. Filtering and transforming vectors can pe two examples. requently used arithmetic functions are implemented using Meaware. It results in faster execution of arithmetic functions " rpared to software implementation, cor some special digital signal processors allow concurrent ecution of functions which boost the performance of the e system. i incorporates many peripherals specific to signal processing It vy include ADC, DAC, PWN, DMA controllers, timers, and counters: advantages? ; psp provides flexibility: Digital signal processing operations can * be changed by changing the program in digital programmable system. psPs are less susceptible: The digital circuits are less sensitive to tolerances of component values. psp improves performance: It has a better control of accuracy * in digital systems compared to analog systems. + DSP supports complex operation: Sophisticated signal processing algorithms can be implemented by DSP method. hi Less-General ASIP / / These are developed to perform some very domain specific i processing while allowing some degree of programmability. Processors designed for networking hardware can be taken as an example of less-general ASIP. a ‘Software Design Issues 159]‘ cessor icropror 36 selecting WE ven, a designer mUSE SECT ERE icy system ‘nan entet ech se \ n axed on terial 2 cgetion af oes" must be dong " retical ses ns ize, ad Ost, j shin li ing microprocessor, . environment, Prior EXPETTISE OF py awa ing Speed et .d and compared usin, speed of processors can be measure vy methods. speed or i. Clock: of process . . Speed can be compared based on clock speeds of rocessors, by. os of instructions per dock cyele may differ. So, it may noe an effient method unless processors to be compared have sap, rrumber of instructions per cycle. Instruction per second The speed can be evaluated using number of instructions execute Ber second. But the complexity of available instruction sets may differ creating some hindrance in speed comparison. For example, t, perform same operation, one processor may require 200 instructions while another may require 300 instructions, Dhrystone benchmark —* [t's 2 program that runs on different processors and evaluates they performance based on execution of certain operations. Dhrystone benchmark performs no useful work rather checks the integer arithmetic and string-handlng capabilities ofthe processor ‘on which the benchmark runs on. Since processors can execute such Operations thousands of times i asecn, ped of pes so a be expressed in terms of Dhrystones per seconds, " er second (MIPS) iv. Millions of instruction Itis a general measure of comy no ips is based on VAK 11/780 which could execute one milion tructions per Second OF Could execute 1757 Dhrystones per rand. Hence, 1 MIPS = 1757 Ohrystones/see Also, performance of sa ee wre mane ott neral-Purpose Processor Design e eral-purpose Processor can be designed using the design een f single purpose Processor as general-purpose processor is 2 renin pale-purBose processor which process instructions stored in of sine ory. The design starts with the design or selecnon of st om followed by creating a FSMD, and then datapath along with ist ons with control unit and finally a controller or FSM is an 47 pesign a general PUrpOSE processor with four data transfer spLE ‘two arithmetic operations and one jump instruction. . uti ee ne following 46 bit instruction size, which has direct impact on memory and are the considerations made in the design. register selections, instruction Register (IR) and Program Counter (PC) of 16 bit Memory of 64K x 16 bit, Register file of 16 x 16 bit jon SetSelection , a Second Byte Operation [qov Ro, direct Direct igre) |qov direct, Rn|0002 [Rn Direct [Mov @Ra, Rr | MOV Rn, #i im 1) [x00 Rn, Rm | 0100 ‘SUB Rn, Rm jo102 [Rn |Rm | ize Rn Relative _ WZRn, relative [0110 jure 3.7: A simple instruction set2 a sot, the oe data ty ti Je useful in 4, ve instruct 4 which may eve from the BPO be ene “ scatin ar avaible fom ruction MOV RN, direct ang used which is avai instruction MOV @Rn, Rm, the adhe Register: value of reste en bY , mem cto load the instruction into IR) sme valve in eter can be loaded from: ee Memory: in instruction MOV Rn, direct register i loo, “ta aa whose address is given by lower eight bi jm aR. ares isa evenbY «instruction register: In instruction MOV Rn, Himm, 1, immediate value of IR is loaded into register. «ALU: After execution of ADD Rn, Rm and SUB Ra, Rr, 1h final result is stored in register. «Three operations are performed by ALU * Addition, subtraction, and comparison FSMD for Given Instruction Set In FSMD, the basic stages of instruction cycle are implemented a, states. It includes RESET, FETCH, DECODE and EXECUTE state. The RESET, FETCH and DECODE states are common to almost every design. The EXECUTE state, however, differs when the number and type of instructions are different, Aliases: 2p IR(15.12] dir-IR(7.0} m= (11.8) imm ~ 1817.0) = 187.4} rel~1R(7.0} Figure 3.8: Finite state machine with data (FSMD) ‘Software Design Issues |63|tions in D 1 state Machine (FSM) Design it connet ini ez + comenet and f Pear Unit rr . aes vel | | \ Mre=1,Peinc «4 _ ings - ha J Contre Sena Inextstate and —> «— || corr 086 lFgmal || | | seeps) amt ||| | fF a Control | \h 4 signals | oa | vos Me | | REL Ri (ienane ater ee tse elle {| | RFrla =n, RErie=1, Ms=00 Fra = rm, RFr2e= 1, Mwe= 1 ott Rewa Rrlazm,Rfrte=1 LW RFr2a = rm, RFr2e= 1, ALUs=00 RFS = 00, RFwa = rn, RFwe 0100 a Memory D | Figure 39: Datapath of our simple general purpose processor i. Components in datapath Beri | Register file of 16x16 and a general purpose ALU. | __ oo | RFr2a = 1m, RFr2e =1, ALUS= 01 Multiplexer of 4x1, since the register in register file can RFS =00,RFwa =1m, we = 2 hhave three sources; Immediate data from IR, data from | Memory, and data from ALU Components in control unit Controller for next-state and control logic, pcld=Alvt * State register, ai Program Counter, Instruction Register altiplexer of xt, since memory address canbe lected from three sources; address from PC, dret ada |R, and address from register. eu 164] insights on Embedded System DB — OO Software Design Issues |65|to FSM operations a erations Converting FSMD oP = gt ———— a eet RA} = MIM) MEMORY Example 1: MOV Rn, d “pe canter of mary oF 2465 ir (81 Sei ~ read the ile. Value ‘| intro ae reat one ofreitrs of restr Fm ial peor? write Ability and Storage Permanence iR) and weit a of register in register file man © Common Memory Types : ‘of memory is directly avaliable in rane Mi composing Memory © Address from IR. For a me; 0 ct address Moy hy and Cache selection Ms = 01 will ele ra wi Memory Hierarchy ‘operation, Mre must be set (Mre = 1) A RFwa = rm ction ritten into register file, so se trodu eee ee file and RFwe enables the write operation, 4.2 » functionality of any embedded system can be basically divided into ed yming from memory. 1 The Mgorage and communication. And memory is required to address Reeth aaa sens essinB 5 pect of the embedded system's functionality. Furthermore, oe te ee the st0ra8e wn electronic device that is used forthe retention of information =e 7 a Here, information can be program instructions or data for ee ee i of bts of — ——_ for lat tational purposes. And, the instructions represent the group of Example 2: ADD Rn, Rm — RF[en] = RF[rn] + RF{em] como! if Here, values from two registers are read and then added using ayy The final resutis stored in register. Address of registers to be selected, given by m and rm for read operation while value of rn gives the address register for write operation * Selection of registers for read operation: RFrla = mn and RFr2a = m select two registers while RFrle = 1 and RFrze = ‘registers for read operation, enable bot) Adding the value of registers using ALU: ALUs = 00 represent the addition of two registers. Selection of register for write operation: RFwa = on selects the [eester and RFwe = 1 enables the write operation. And RFs = 00 wil connect the output of ALU through the mux to the selected register. Hence, the required Boolean expy ressions are: RFr1a RFrle = 1, RFr2e = =, RFr2a = ALUS = 00, RFS = 00, RFwa m =n, REwe = 166] insights on Embedded System ~ ide along with operands, while data indicates the values of onerstn fe will be used in the operation. In general, the instructions are perand that memory which we refer as read only memory. And the data 2 of sored v ae tation are temporarily stored in registers. for eeu + nbits perword —> > <_m words LT - Figure 4.1: mxn memory : of large numbers of bits. And .d together to Iso, words are stacke oe ory as m words of n bits each. memory is specified as 4096 A memory stores information in form bits are combined to form a w ie represent a memory. So, we refer toa mend And tis represented by m x". For example x8then it holds the following information. + Number of words in the memory (™ 9) 4096 * Number of bits per word (n): 8 = Memory 16717 bits are stored only once during fabrication. Example bits tow End Jd ROM me {on} 32768 = 1ogs(4096) = 10812") <1) aggk- programm + Tobe Ss = = 8 ° Mie Permanence fines = . f Address orag «Number of sataseras® : store permanence refers to the ability of memory to hold its stored Total input/output memory read (retrieve the yo, 51012 bits have been written. Volatile and Nonvolatile attributes . e ony acess may ree! F gore a word in 2 Particular ag,!. anter *Mo ag to divide memory types into two categories along the m : A aia cor memory write " the type of access. Another.) Bs como mene axis. The nonvolatile memory can hold its bits even pac isd coin sused toc the memen ® 1082 er longer supplied. On the contrary, volatile mernory requires yntro! inp serted, rst er i ~ tonreigal abe, wich when a oe wer ova its daa inp. : — ‘nua = jn a ™ TT ten con storage permanence: enable —— eo = memory in this range begins to lose its bits almost we Memory we iow rately after those bits are written and therefore it must be og ee -d periodically. Example: DRAM a ae ange ~ memory holds bit as long as power i applied to the yer Ral a mmory. Example: SRAM 1 oe nge - memory in this range holds bits for days, months, or Middle Raa or the memory power source has been turned off * even year example: NVRAM a rmanence 4.2 Memory Write Ability and Storage Permanet Write Ability Write ability refers to the manner and speed that a particuly memory can be written. It also can be used to represent the number times a memory cari be programmed or written” into. In-systen Programmable is used to categorize memories into two along the write ablity axis. In-system programmable memory can be programmed by 3 Processor whereas non in-system programmable memory must be Programmed by some external means. Range of write abilit + High End ~ processor can write to memory sim setting its address ines, appropriately. Example: RAM Middle Range ~ processor can write to m: compared to high end. Example: EEPROM, FLAS 1 ly and quickly by data input bits and contéol lines eMOTY a bit slower 3H Lower Range - special device called the memory. The device must apply ‘the memory. E.g.: EPROM, OTP ROM BYOBraMMer I Sed 0 wit neg Surtable voltage evel a yin eto 168] Insights on Embedded System 4 —_memory in this end will never lose its bits, as long as the igh En grammed ROM High try chip is not damaged. Example: Mas Pro mem eof soe. Wate bt atl oan Pe nts? ge permanence +s based on write ability and storas Figure 4.3: Various memoriesyo 43 o Types Common Memory ™) RO! 1, Read Only Cesathe that an be ead fom buy ‘or, but it can be programmed 4, sett Traditionally, ROM is programm, hy . ed ned within an embedded systom, itis a nonvolatile me" written to, by process bits within the memory. , when it is not actively invol enable | A ——% 2xnROM Aa Q. Figure 4.4: External block diagram i, Uses of ROM i to store a software program for a general purpose processo, * to store constant data, like large lookup tables of Strings a pr numbers ‘toimplement a combinational circuit ii. Internal View of the ROM It consists of an address lines, word lines, data lines, decoder, OR gate and programmable coni word line and data line. Control in, nections which conneq ‘combinational functions: y et Decoder selection: number of wor decoder required. Number of guys 8: 50 at leat a 3x8 put equal or teater than numpe, mo cad decoder must be ine Horizontal ines = words (8), Verge data (a) Word line connected to da ta in connections "via the programmable Circles on data and word lines ay, togic(2) Wired-OR represents all word lines are op © connected to represent high 'ed together if word 3 needs to be read then t the input Of decoder ig (011 which makes the word 3 line nal, ih and other word lines iow, since the data lines O and 3 are not connectey the high word 3 line, the output of the ROM will be 9139 jmplementation of Combinational Functions using ROM be + abc + abe Thee inputs 2B and cis taken as addres ines So, for three inputs decoder of 3x8 must be used resulting in eight word lines, And there are ec ts, $0 there must be two data ines. Hence, a ROM of 8x is 1 italy if only combinational function given, then its truth table reid. Penal The programming connections are done based on the 7 a re functions based onthe valous combate inputs. ——~ out Inputs | Outputs aibiely jz 0 j|0 jo j1 Jo Ojo jit io ja te | an RES o ja [ajo [a Lat Tle tole te i | fa fo la la [1 L men 1 jo [1 7 Fee tote te te @aaa 1 |i jo Figure 4S: mera view ofa et no (jaa fa a 170] insights on Embedded System — Memory |71|© Figure 44: Tat able forgiven fonction and its implementation using po, iv. Types of ROM ‘.Mask-Programmed ROM © Connection is programmed during fabrication, by crea, ‘an appropiate st of masks + It has extremely low write ability, Once fabricated, ‘content cannot be reprogrammed or ehanged. It has highest storage permanence, Stored bits will nq change uniess the chip is damaged, It is used in such embedded sy been finalized and large numbers ‘manufactured stems whose design by S of unit are needed to 5. One-Time Programmable ROM - OTP ROM * Connection Programmer ee oer eal ae open, arg 10 the fhe prove ae 7 lows fuses by passing a lange St erever a connection is not os ee eared, Tas cannot be reestablished, hence ty rt MOM ct Programmable ROM, (STE sone 172] Insights on Embedded system =o It has lowest write ability of all PROMS, since it can be programmed only once. 4 Ithas very high storage permanence, since its stored bits won't change unless; some more fuses are blown out Using programmer Its cheap which makes it more suitable in final products compared to other types of PROM Erasable Programmable ROM - EPROM + EPROM uses a MOS transistor as its programmable component. The transistor has a floating gate surrounded by insulator. When high voltage (12V - 25V) is applied, i causes electrons to tunnel through the insulator into:the gate. When the high voltage is removed, the electrons cannot escape and hence the gate has been charged and programming has occurred. To erase the program, the electrons must be excited enough to escape the gate which is done by exposing UV light for § ~ 30 minute. For the UVlight to reach the chip, EPROMs are provided with a small quartz window in the package. Reading an EPROM is much faster than writing, since reading doesn’t require programming © EPROMs have improved write ability and can be reprogrammed thousands of times 1 EPROMSs have reduced storage permanence. They hold their stored bits for about 10 years. «Electrical noise or radiations causes stored bits ofthe chip subject to undesirable changes and hence EPROM are scarcely used in production. It offers a better choice in the testing phase ofthe system rather than in production. Internal Operation of EPROM: 2a) Negative charges form a channel between source and drain storing a logic 1 b) Large postive voltage at gate causes negative charges to move out of channel and get trapped in floating gate storing a logic 0 : — Memory 1731Pa f floating on surface © ta, me y shining UY aye FH retin t0 channel fro, contains the ‘culty. and single purpose processor ive craves required to erase and program the word at the use? ea xing te EC specified address ae rs ing quartz win & cage srowind VFO 4. EEPROM provides better write ability compared to EPROM, it can be reprogrammed tens of thousands of times ‘an EPROM ‘, EEPROM has storage permanence on a par with EPROM, about 10 years. writing is slower, since it involves the process of erasing and programming. An extra busy pin is available to indicate that the EEPROM is busy in writing EEPROM can be used to serve as the program memory for a microprocessor. It can also be used to store data than an ‘embedded system should save after the system is off fe. Flash Memory It is an extension of EEPROM which uses the same floating gate principle along with same write ability and storage permanence. tt improves the performance of a system with its fast erase ability, in which large blocks of memory can be erased all at once. Writing to a single word in flash may be slower than writing to a single word in EEPROM, since an entire block I will need to be read, updated and written back. Figure 4.7: Writing and erasing process in EPROM bh random Access Memory ~ RAM 4. Electrically Erasable Programmable ROM ~ EEPROM itisa memory that can be both read and written esi. Typically RAM is i t loses its content after the power i removed. The internal i + EEPROM is programmed and erased electronicalh vate Se iy, ust higher than normal voltage. Bectronic erasing rea ‘tructure of RAM is comparatively complex than of ROMS. scons atte han man ms equa for EPROM iw — foreover, individual words can be er a ble >] > reprogrammed in case of EEPROM, whereas oRoM 7 leet Dyn only be eased in then, ca A aM | ‘*Itisin-system programmable imable since circuit Sat than noma eager ere mpeg en . bunt ened sate eo | lt in memory controller whic with 3 ory conrller which hides itera memy .— access details for the mem memory user and memory interface to 1. The memes the user. The memory cage Figure 4.8: External view of RAM > 174] Insights on Embedded System EE ==a ture of RAM ines (A word lines (output of de¢, ad wtng (control lines (ena i well at each intersection OF wor, ", Internal Stru It consists of address lines for reading (a) decoder, wired-OR, a" } data lines. dw —) 4 | ta Mae Decoder | ml At A rrtye QQ A GQ A Figure 4.9: Internal structure of 6 RAM. Decoder selection is done based on (3x8 decoder for 6 words) miner of words of ly Each word consists of 2 number of me oak 'emory cells, each story ach input data line and out, put dat cellin its column, ie connected to oie Output of a memory cell being of each column, OFet With he out dts i The read/write input is connected to every cel) Wired-OR isnot shown in the figure 4.8, ne 176] insights on Embedded System types of RAM 4. Static RAM ~ SRAM 2 Itusesa memory cell consisting ofa flip flop to store a bit e_ It requires about six transistors to represent a single bit «It holds data as long as power is supplied hence called static RAM, «Generally used for high-performance section of a system. Eg, Cache memory pynamic RAM b. It uses a memory cell consisting of a MOS transistor and capacitor to store abit It requires only one transistor, resulting in more compact memory than SRAM. Each cell must be charged (refreshed) regularly, since the charge stored in capacitor leaks gradually causing the loss of data DRAM access tends to be slower than SRAM, since accessing a DRAM word results in the word's being stored ina buffer and then being written back to the word's cell. paw (@) oO Figure 4.10: (a) SRAM (b) DRAM c._ Pseudo-Static RAM —PSRAM roller built «These are DRAMs with a memory refresh cont in, © PSRAM may be busy could increase access time ans complexity. —O Memory 1771 refreshing itself when accessed, which d add some systemitis popular west high-density memory a, itholds data even after external power is removed patteny-Backed RAM: Contains a static py permanent battery connected. When power is ra, drops below 2 certain threshold, the intermay wt maintains power and the memory continues to bits. There sno limit onthe number of times the ty Backed RAM can be written to Bay «Stat RAM with EEPROM oF FLASH: This type of stores its complete RAM contents into the cement before the power is turned off. The data is reloaday, RAM after the powers turned back in ‘ ‘Advanced RAM. Fast Page Mode Dram (FPM DRAM) FPM DRAM is asynchronously controlled which is designeg, some improvements on the basic DRAM architecture, jn Sesign each row ofthe memory bitaray is viewed as ay Which contains multiple words. Each word is addressed i ssa on ir In its operation, first the row or d is sent and then the corresponding column aan ‘must be sent to read a particular word. In each memory ck three data wi "a words can be read consecutively by providing the ‘required to read three words, 6 ‘ended Data Out ORAM (EDO DRAM) £0 otis isa Feo a the read/write latency, i ee es ‘d while keeping the data ‘out single weds new cuss an al feature tha, route S85 ce canbe * of previous oycle acti Previously selec ns ri prev ected word trom the memos, Mle readin PPIN8 of the operation which rene”: Ts : i Fesults in Which reduces memory acces CESS. However, ‘ tra output latch Introduced in the architecture 178] Insights on Embedded System ~~ é. 3. Memory Management Unit (MMU) ‘Memory management unit is a process address to physical memory address. synchronous DRAM (SDRAM) In SDRAM, the information is latched to and from the controller ‘on the active edge of the clock signal. The time required to detect the strobe signals in asynchronous ORAM is eliminated by SDRAM. This DRAM architecture can have additional column address counter which holds the starting address of the data to be accessed. This counter is incremented internally to provide new data in each clock cycle as long as the data required are consecutive memory locations, The enhanced synchronous DRAM (ESDRAM), is the improved version of the SDRAM. ESDRAM provides faster clocking and lower latency in reading and writing data. Rambus DRAM (RDRAM) ambus represents the bus interface architecture which uses multiplexed address/data lines to connect the processor to the RORAM device. RORAM may be further divided into number of banks with each remain open for access. Multiple open page scheme and fast bus 1/0 can result in high throughput. However, as compared to. other standards, Rambus showed increase in latency, heat output, complexity, and cost. Requirement of heat-spreaders along with packet de rmultiplexors makes it more complex while manufacturing, More complex interface circuitry and more number of memory banks increased the size and resulted to become expensive. Double Data Rate SDRAM (DDR SDRAM) ‘The DDR SDRAM is capable of making higher transfer rates with more strict control of the timing of the data and clock signals. The interface transfers data on both the rising and falling edges ‘of the clock signal to double the data bus bandwidth. DDR SDRAM also known as DDR1 was replaced by DDR2 which ‘operated on same principle but for higher clock frequency and produced double throughput as compared to DORI. ‘Similarly, DDR3 and DDR4 offered better performance for increased bus speed and new features. Jor which translates the logical MMU has important role in. ‘Memory 1791