Lab #10 The Dice Game

Lab #10: The Dice Game

Revised 4_4_11

Overview
We have looked at sequential building blocks as well as begun to look at synchronous sequential circuit
design. This lab will allow us to design a game in hardware. Dice games are very common and easy to
implement in hardware. This dice game will allow the user to roll two die and then compare the sum of
the values with specific values for a win or lose situation. Finite state machine along with datapath and
control circuits will be emphasized.

Before beginning this module, you should… After completing this module, you should…

 Be well practiced in the design of  understand how to design finite state

various circuits. machines that are examples of
 Be familiar with the Xilinx ISE design sequential building blocks
tool suite.  know the Verilog code for the devices

Modules used and created in this lab:

 Dice roller (Two dice whose range is 1-6 by using 3-bit counter and 3-bit adder) – Lab 9
 4-bit register with asynchronous clear – Lab 8
 Test logic block (similar to card checker: 2,3,12 LOSE and 7,11 WIN) – Lab 4
 4-bit comparator
 Control box (Finite State Machine)

This lab exercise requires:

 A BaSYS or BaSYS2 board
 A PC running the Xilinx WebPack or ISE CAD tools

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 Lab #10 The Dice Game

Background
Craps – a dice game
Craps is a dice game in which players place wagers on the outcome of the roll, or a series of rolls, of a pair of
dice. This lab simulates the dice game. The basic rule for craps is like following: if, on the first roll, you make a
7 or 11, you've rolled a "natural" and you win. If you roll a 2, 3 or 12 on your first throw, that is called "craps"
and you lose. If, on the first roll, you shoot a 4, 5, 6, 8, 9 or 10, that is you are established "box point." The
object then is to keep rolling the dice until you make that number again. You lose, however, if you roll a
seven before making your box point.

Procedure
The overview of the game is on the following flow chart.

FIGURE 1 FLOW C HART OF THE DICE GAME

According to the flow chart, we will need dice roller two times, various comparators, register to store the first
result of the two dice, and control statement to handle various conditions depending on the comparisons
between numbers.

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 Lab #10 The Dice Game

So far we have looked at combinational circuits and sequential circuits. In this final lab, we are going to put all
we learn together. Last lab we made a dice roller, the lab before last lab was 4-bit register and card checker
in Lab4 where 7 or 11 produces WIN and 2, 3, or 12 LOSE. Overall system can be drawn like following diagram

FIGURE 2 T HE DIAGRAM OF D ICE GAME

Here narrow signal is 1 bit and bold signal are bus (all are 4 bit except the result from 3-bit counter). As
shown on the diagram, all the signals are controlled by control module. The data flow of this system is: first
control block accept BTN signal generated by the user and generate ROLL signal, and ROLL signal is split into
two independent CLK signals to generate two numbers between 1 which are added together to generate
DICE_SUM signal which is 4 bit hex value. And the DICE_SUM is passed to three different modules; Test Logic,
Register, and Comparator. Depending on the DICE_SUM, Test Logic produces one of among D7, D711, and
D2312. If the signal is D711, Control module generates WIN signal, and if the signal is D2312, LOSE signal. If
the signal is not any of those signals, Control module generates another ROLL signal when BTN is pressed by
user as well as SAVE signal for the register to store the current DICE_SUM. After another DICE_SUM is
generated, it is compared with STORED_SUM which is saved in Comparator. If it is ‘EQUAL’ the Control
generates WIN, or if DICE_SUM is 7 (D7 from Test Logic) the Control generates LOSE.

Because of the time limitation for the lab, we only make ‘dice roller’ and ‘controller’. The other three
modules (Register, Comparator, and Test logic) will be assigned as prelab. However, we already made
register and the circuit similar to Test logic. See the details on circuit design.

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 Lab #10 The Dice Game

Controller: Finite State Machine

As we’ve seen, Control module handles all incoming, outgoing signals. Next diagram shows state transitions
between the state S0 to the state S6. Each state may have the outputs or condition to proceed to next state.
The square boxes represent state which contain outputs such as WIN=0 and SAVE =1. Diamond boxes
represent conditions. These operations are done in ‘always’ statement in Verilog which covered in Lab8.

F IGURE 3 T HE FINITE S TATE MACHINE FOR D ICE GAME

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 Lab #10 The Dice Game

Verilog: Finite State Machine for Dice Game

We use ‘parameters’ declaration to map S0-S5 into actual binary representation 000-101 because it looks
easier for us to distinguish the states. Also we set initial state by using ‘initial’ statement. Always statements
are used first for defining state transition according to CLK signal. Also, ROLL signal is generated when button
is asserted except S2 and S3 state (WIN and LOSE). It should be notice that inside the ‘always’ statement, all
if-else statements and case statements start with ‘begin’ and end with ‘end’.

Example: Controller
module controller(CLK, RESET, BTN, D7, D711, D2312, EQUAL, ROLL, WIN,
LOSE, SAVE, NEXT_STATE);
input CLK, RESET, BTN, D7, D711, D2312, EQUAL;
output ROLL, WIN, LOSE, SAVE, [2:0] NEXT_STATE;

reg WIN,LOSE,SAVE,ROLL;
reg [2:0] STATE, NEXT_STATE;

// Turning binary number representation to S0~S5

parameter S0 = 3'b000;
parameter S1 = 3'b001;
parameter S2 = 3'b010;
parameter S3 = 3'b011;
parameter S4 = 3'b100;
parameter S5 = 3'b101;

initial begin
STATE = S0;
NEXT_STATE = S0;
end

// Defining actions at Clock and RESET

always @(posedge CLK or posedge RESET)
if (RESET == 1) begin
STATE = S0;
end
else begin
STATE = NEXT_STATE;
// Defining actions at button is asserted
// Disabling actions at S2(WIN) and S3(LOSE) state
if (BTN==1 && NEXT_STATE!=S2 && NEXT_STATE!=S3) begin
ROLL = 1;
end
else begin
ROLL = 0;
end
end

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 Lab #10 The Dice Game

// Defining outputs and next state depending on current state and control signal
always @(STATE or ROLL or D7 or D711 or D2312 or EQUAL)
case(STATE) // Needs to set all state(S0~S5) using case statement
S0: begin
// Defining output
WIN = 0;
LOSE = 0;
// Defining next state using if~else statement
if(ROLL != 1) begin
NEXT_STATE = S0;
end
else begin
NEXT_STATE = S1;
end
end
S1: begin
if(ROLL == 1) begin
NEXT_STATE = S1;
end
else begin
//Defining output
SAVE = 1;
// Defining next state using if~else statement
if (D711 == 1) begin
NEXT_STATE = S3;
end
else if (D2312 == 1) begin
NEXT_STATE = S2;
end
else begin
NEXT_STATE = S4;
end
end
end
S2: begin ...

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 Lab #10 The Dice Game

Circuit Design (Verilog)

We mainly have four modules; dice_roller, controller, test_logic, full_adder_3bit, and register_4bit.

Prelab (Three modules)

Implement these modules if you don’t have. Show the testbench waveforms of these functions at the start of
the lab.

 register_4bit: we already made this module in lab 8. If don’t have it, implement it according to Lab8
manual. Names are not matter for inputs and outputs, but the module must have same function of
inputs and outputs.
o input: CLK, CLR, D_IN[3:0], LOAD(or LD)
o output: D_OUT[3:0]
o Verify it with test bench waveform (you can just use the code in Lab 8)

 full_adder_3bit: If you already have it, just check input and output form and generate testbench
waveform according to Apendix
o input: A [2:0], B[2:0]
o output: S [3:0]
o Verify this with testbench waveform according to Apendix

 test_logic: according to lab4, write this function. You can ‘copy and paste’ of the code from the lab.
However, make sure the form of input and output. You need to write a function for D7 which is very
similar to D711. See the win_check and lose_check module in Lab4.
o input: DICE_SUM [3:0]
o output: D7, D711, D2312
o Verify this with testbench waveform by setting 7, 11, 2, 3, and 12 on DICE_SUM

Inlab (Three modules)

Some modules such as display_result and clock_devider will be given in the lab. Those will help you to
concentrate on implementing main functions in hope that you will learn how to combine all modules that we
built.

 dice_roller: This module calls three sub modules; clock divider, two counters from last lab, and
full_adder_3bit. The skeleton code will be given.
o input: CLK, CLR, ROLL
o output: DICE_SUM[3:0]
o test on the BaSYS board (test module will be given)

 controller: Complete the given module according the example above

o input: CLK, RESET, BTN, D7, D711, D2312, EQUAL
o output: output ROLL, WIN, LOSE, SAVE, NEXT_STATE [2:0]
o Verify this with testbench waveform by setting various possible cases.
o One example: D711 is on after ROLL signal

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 Lab #10 The Dice Game

o The result should be following. (check out NEXT_STATE changing S1 to S3 to S0)

o Other cases include D2312 after ROLL signal, EQUAL signal after ROLL signal .

 comparator_4bit: This module compares two hex values and generate true (1) or false (0) signal on
the output, EQUAL. There are many ways to implement this. One of them is first to use ‘xnor’
operator on two signals, and ‘and’ operation on element of the results. (Because ‘xnor’ operator
performs ‘xor’ operation followed by ‘not’ operation. Here ‘xor’ generates 1 if two signals are the
same, otherwise 0)
o input: A[3:0], B[3:0]
o output: EQUAL
o Verify it by setting A and B are equal or different.

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 Lab #10 The Dice Game

Configuring the FPGA and Test

After the implementation and verification, the program should be tested on BaSYS board. Use the skeleton
code ‘dice_game’ which will be given in the lab. As needed, modify the code according to call the submodules
that you made. The setup for this lab is BTN[0] is start signal, BTN[1] is reset or CLR signal. If you win the
game, first 4 LEDs are lit on. If you lose, last 4 LEDs are lit on. Make sure testing all possible cases. Check off
the result with TAs on the designated date that will be informed in the lab.

Appendix: 3-bit adder

1. Start with 1bit full-adder

 Equation After solving K map

s = a'b'c_in + a'bc_in ' + ab'c_in' + abc_in ;

c_out = ab + bc + ca;

 Input and Output Specification for full adder

module full_adder_1bit(a, b, c_in, c_out, s);
input a;
input b;
input c_in;
output c_out;
output s;

// fill out these equation

assign s = ;
assign c_out = ;

endmodule

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 Lab #10 The Dice Game

2. Build the 3bit input- 4bit output full adder

# Input and Output Specification for full adder

module full_adder_3bit(a, b, s);
input [2:0] a;
input [2:0] b;
output [3:0] s;
wire [2:0] c; // use for carry in and out

// you have to put three instantiation of 1bit adder. I put one and write other two.
full_adder_1bit A1 ( a[0], b[0], 0, c[0],s[0] );

assign s[3] = c[2]; // this will put the last carry out to the most significant bit of the results
endmodule

i. Test bench waveform (Check your results)

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