481

Design Guidelines and Control of DC-DC Cascaded

Buck Converters
Fabrı́cio Hoff Dupont, Member, IEEE, José Renes Pinheiro, Member, IEEE, Vinı́cius Foletto Montagner

Abstract—This paper deals with the voltage control of DC-DC S1 S2

cascaded buck converters. A steady-state analysis is presented, iL1 L1 iL2 L2
providing the design guidelines for all the parameters of two
+ +
cascaded buck converters based on analytical expressions. In the
sequence, a state feedback model of the converter is obtained, Vi D1 C1 vC1 D2 C2 vC2 R
and after linearized. A small-signal model in the state space − −
is provided and then augmented with an extra state variable
representing integral action. A state feedback controller is used,
and its gains are computed with the help of a linear quadratic Fig. 1. Two stage cascaded buck converter.
regulator (LQR). The impact of parametric variations over the
dynamic response are investigated and simulation results of the
closed-loop system are presented, confirming good transient and
steady state performances of the converter under load variations. This paper provides a suitable LQR control for the output
voltage of DC-DC cascaded buck converters. The case of two
Index Terms—Cascaded buck, DC analysis, DC-DC converter, converters with switches driven synchronously is investigated.
LQR, Optimal control, Small-signal modeling An averaged model in the state space is obtained. An
integral action is included in the control system to ensure
zero steady state with respect to constant voltage references.
I. I NTRODUCTION
A DC analysis is shown, providing design guidelines for

T HE control of DC-DC converters is important in

several applications in engineering, as machine drives,
supplying of electronic equipment, regulation of input stages
all parameters of the buck converters. The control gains
computation and the control signal implementation are also
detailed. The impact of parametric variations over the open-
in renewable energy systems, etc. [1], [2]. In cases where the loop response of the converter is also investigated, assisting
ratio between the input and output voltages is too high or too the designer in choosing the most suitable parameters. Finally,
low, cascaded boost or cascaded buck converters can be used results illustrate the viability and the noticeable closed-loop
[3]. In these cases, models of higher order, including the state response of the proposed controller.
variables of all the converters, can be necessary to describe the
dynamic behavior of the cascaded converters. Then, control
tools suitable for multivariable systems become of interest, as II. S TEADY-S TATE A NALYSIS
for instance, state feedback control schemes [4], [5].
To investigate the average and the small-signal model for
Among the state feedback control, the linear quadratic the two stage cascaded buck converter depicted by Fig. 1 for
regulator (LQR) is undoubtedly important since it can provide the purpose of this paper, the following assumptions are taken:
suitable gain and phase margins for the system. In the
design of LQRs, the control designer must choose the 1) Switches are considered to be ideal
relative importance of the state variables and also can impose 2) Only the continuous conduction mode is addressed
constraints to the control energy, allowing to avoid control 3) Switches S1 and S2 are assumed to operate
signal saturation [6]–[10]. Moreover, the design of the LQR synchronously
control gains can be made with the help of specialized Another version of this converter is presented by Fig. 2,
programs as the MATLAB, which also provide an environment integrating both controlled switches in a single one. It is worth
to test several responses of the closed-loop system, as time and noticing that all the analysis presented in this paper is valid
frequency responses. for both topologies. However, Fig. 1 is employed as reference
throughout the paper, without loss of generality. From these
Manuscript received July, 28, 2015. This work is supported by the Brazilian assumptions, two topological stages can be observed during
agency CNPq, and by the project 3917 of URI project notice 10/2015.
F. H. Dupont is with the Electrical Engineering Research and Development one switching period Ts and are described next.
Group (GPDEE) of Regional Integrated University of Upper Uruguai and
Missions (URI), Av. Assis Brasil, 709, 98400-000, Frederico Westphalen, RS,
Brazil. Contact: [email protected]
J. R. Pinheiro and V. F.Montagner are with the Power Electronics and A. Stage 1
Control Research Group (GEPOC) of Federal University of Santa Maria
(UFSM), Av. Roraima, 1000, 97105-900, Santa Maria, RS, Brazil. Contact: This stage occurs when switches S1 and S2 are closed
[email protected] and [email protected] from t = 0 to t = DTs , where D is the duty ratio and Ts the
978-1-4673-8756-9/15/$31.00 2015
c IEEE
 482

S1 Similarly, in equilibrium the current across capacitor C1 is

iL1 L1 iL2 L2 zero. Then, from (3) and (7) one has
   
+ IL1 − IL2 IL1
D1 C1 vC1 + DTs + D  Ts = 0 (13)
C1 C1
−
Vi D2 C2 vC2 R leading to
IL1 = IL2 D (14)
D3 −
And finally, for the output capacitor C2 the current at
equilibrium is obtained from (4) and (8) as
   
IL2 VC2 IL2 VC2
Fig. 2. Integrated version of the two stage cascaded buck converter. − DTs + − D  Ts = 0 (15)
C2 C2 R C2 C2 R
switching period. During this period, the voltages across L1 which leads to
VC2
and L2 are given by IL2 = (16)
R
dvL1
L1 = −vC1 + vi (1)
dt
D. Design Guidelines
dvL2
L2 = vC1 − vC,2 (2) From (10) and (12) one has that the static gain of the
dt
converter is obtained by
while the current across C1 and C2 are 
Vo
diC1 D= (17)
C1 = iL1 − iL2 (3) Vi
dt
Due to the small-ripple approximation it can be considered
diC2 1 that (1) also describes the current ripple across the inductor.
C2 = iL2 − vC2 (4)
dt R From this, the minimum value of L1 that satisfies the desired
input current ripple is given by
B. Stage 2
Vi D  D
The second stage occurs when switches S1 and S2 are open L1 = (18)
ΔIL1 fs
from t = DTs to t = Ts . Throughout this period, the voltages
where ΔIL1 is the peak-to-peak current ripple and fs the
across L1 and L2 are given by
switching frequency fs = 1/Ts . Similarly, the design equation
dvL1 to obtain the minimum values needed for C1 and L2 can be
L1 = −vC1 (5)
dt obtained respectively by the manipulation of (3) and (2), which
dvL2 results in
L2= −vC2 (6) Vi D 3 D 
dt C1 = (19)
ΔV1 Rfs
while the current across C1 and C2 are
diC1 Vi D  D 2
C1 = iL1 (7) L2 = (20)
dt ΔIL2 fs
diC2 1 However, the small-ripple approximation is not useful for
C2 = iL2 − vC2 (8) determining the voltage ripple across C2 , which provides zero
dt R
voltage ripple. In this case, the charge balance approach is
used [11], knowing that in steady-state the charge absorbed
C. Steady-State Values
by the capacitor is fully transferred to the load. Analyzing
Using the small-ripple approximation [11], and knowing waveforms of iL1 and vC2 this leads to
that in equilibrium the voltage across L1 is zero, from (1)   
1 Ts ΔiL2
and (5) one has ΔQC2 = (21)
    2 2 2
Vi − VC1 VC1
DTs + − D  Ts = 0 (9) Applying the capacitor relation
L1 L1
Q2 = C2 VC2 (22)
which leads to
VC1 = Vi D (10) and substituting (20) in (21) one can obtain the minimum
capacitance value to attain the required voltage ripple, given by
Also, from (2) and (6) the voltage across L2 at equilibrium is Vi D 2 D 
    C2 = (23)
VC1 − VC2 VC2 8ΔVC2 L2 fs2
DTs + − D  Ts = 0 (11)
L2 L2 providing the guidelines for the main specifications of the two
resulting in stage cascaded buck converters.
VC2 = VC1 D (12)
483

III. S MALL -S IGNAL M ODELLING IV. LQR D ESIGN

From the main equations obtained in Section II, one can To enable disturbance rejection and asymptotic tracking of
derive the state space model for the stage where both switches constant voltage references an LQR controller is designed.
are conducting, which is given by However, may not be achieved employing the small-signal
ẋ = A1 x + B1 Vi (24) model (32) directly. To enable these features an additional
integral state is included, which is given by
where x is the state vector  t
 T 
x = iL1 vC1 iL,2 vC2 (25) θ= vref − vC2 (τ ) dτ (35)
0
where superscript T denotes the matrix transpose, and and leads to the augmented system model
corresponds to the current across L1 , the voltage over C1 , the
current across L2 and the voltage over C2 , respectively, and ξ̇ = Fξ + Gd˜ + Gref vref (36)
⎡ ⎤ ⎡ ⎤
1 1 where
⎢ 0 − 0 0 ⎥ ⎡ ⎤ ⎡ ⎤
⎢ L1 ⎥ ⎢L ⎥ x̃ A 0
⎢ 1 1 ⎥ ⎢ 1⎥
⎢ − 0 ⎥ ⎢ ⎥ ξ=⎣ ⎦ F = ⎣ ⎦
⎢ C1
0
⎥ ⎢ 0 ⎥ 
A1 = ⎢ 1
C 1 ⎥ , B1 = ⎢ ⎥
⎢ ⎥ (26) 0 0 0 0 −1 0
⎢ 0 1 ⎥
− L2 ⎥ ⎢ ⎥
⎢ 0 ⎢ 0 ⎥ ⎡ ⎤ ⎡ ⎤ (37)
⎢ L2 ⎥ ⎣ ⎦
⎣ 1 1 ⎦ B 0
0 0 − 0 G=⎣ ⎦ Gref =⎣ ⎦
C2 RC2
0 1
For the period in which both switches are blocked and
diodes are conducting, the state-space model is given by Assuming that this system is controllable by means of the
control law
ẋ = A0 x + B0 Vi (27)
d˜ = −Kξ (38)
where
⎡ ⎤ being K the gain vector
1 ⎡ ⎤
⎢ 0 − 0 0 ⎥ 0  
⎢ L1 ⎥ ⎢ ⎥ K = KL1 KC1 KL2 KC1 Kθ (39)
⎢ 1 ⎥ ⎢ ⎥
⎢ 0 0 0 ⎥ ⎢0⎥ and ξ the disturbance state vector
⎢ ⎥ ⎢ ⎥
A0 = ⎢ C 1 ⎥
1 ⎥ , B 0 = ⎢ ⎥ (28)  T
⎢ 0 − ⎢0⎥
⎢ 0 0 ⎥ ⎢ ⎥ ξ = ı̃L1 ṽC1 ı̃L2 ṽC2 θ (40)
⎢ L2 ⎥ ⎣ ⎦
⎣ 1 1 ⎦
0 0 − 0 The control structure is detailed in Fig. 3, where it can be
C2 RC2 observed that the equilibrium values of states is subtracted
Thus, the average model is given by from the measured signals to obtain the small-signal values.
 The small-signal control action d˜ is given by the sum of the
ẋ(t) = d(t)A1 + (1 − d(t))A0 x(t) weighted perturbations on the state variables together with the

+ d(t)B1 + (1 − d(t))B0 Vi (29) weighted integral action on the tracking error. Finally, nominal
Rewriting (29) with d(t) as d(t) = D + d(t),˜ ˜ a
being d(t) duty cycle is summed with d˜ in a feed-forward action to help
small disturbance on this value, and x(t) as x(t) = Xq + x̃(t), returning to the equilibrium values faster.
where Xq is the steady state value of the state vector and x̃ a In order to obtain the control gains in (39), here one uses
perturbation on this vector. From this, one gets the equilibrium the well known optimal LQR strategy [4], [6]. This strategy
value of the states minimizes a cost function given by
−1  ∞
Xq = − (A1 − A2 ) D + A2 B1 V i D (30) J= ξ(τ )T QLQR ξ(τ ) + d(τ
˜ )T RLQR d(τ
˜ ) dτ (41)
0
which is the same of
 T where QLQR is the weighting matrix for the state variables
Xq = IL1,q VC1,q IL2,q VC2,q (31) and RLQR is a positive scalar to weight the control signal in
that have been previously defined at (14), (10), (16) and (12), the cost function. Usually one can choose QLQR as a positive
respectively. diagonal matrix.
Also, collecting the disturbance signals the linearized small- The minimization of the this cost function is ensured by the
signal model is obtained, which is given by solution of the Riccati equation
−1
x̃˙ = Ax̃ + Bd˜ (32) FT S + SF − SGRLQR GT S + QLQR = 0 (42)
where and the control gains are given by
A = (A1 − A2 ) D + A2 (33) −1
K = RLQR GT S (43)
B = (A1 − A2 ) Xq + B1 Vi (34)
The solution of the Riccati equation can be easily carried out
by the lqr function of MATLAB, where the control designer
 484

TABLE I
IL1,q KL1 D ESIGN REQUIREMENTS FOR THE CONVERTER .

iL1 Parameter Value

Input voltage (Vi ) 320 V
Output voltage (Vo ) 48 V
VC1,q KC1 Rated power (Po ) 50 W
Switching frequency (fs ) 40 kHz
Input current ripple (ΔIL1 ) 20 %
vC1 Intermediate current ripple (ΔIL2 ) 40 %
Intermediate voltage ripple (ΔVC1 ) 0,1 %
d˜ Output voltage ripple (ΔVC2 ) 0,05 %
IL2,q KL2

iL2
TABLE II
M AIN SPECIFICATIONS OF THE CONVERTER .
VC2,q KC2
D d(t) Parameter Value
vC2 Rated duty cycle (D) 0,387
Rated load resistance (R) 46,08 Ω
Input inductor (L1 ) 25 mH
Vref Kθ Intermediate inductor (L2 ) 1,8 mH
Intermediate capacitor (C1 ) 47 μF
Output capacitor (C2 ) 27 μF

Fig. 3. Block diagram of the signal formation from the state feedback and
integral action.

from 1 μF to 1 mF, a common approach to reduce control

informs the matrix of the model, F and G, the weighting effort, significantly reduces the system performance, bringing
matrices QLQR and RLQR , and the solver provides the control both pair of poles in direction of the origin.
gains K. Substituting parameters of Table II at (32) one obtains the
It is worth to mention that this LQR would be also suitable small-signal model for the cascaded buck converter addressed
to cope with the case where two not synchronous commands in this paper. Then, the LQR controller may be designed.
were used for the switches. In this case, two sets of control Here a conventional approach for designing the controller has
gains as the one in (39) can be computed simultaneously been employed, which is based on trial and error tuning of
the lqr function of MATLAB, only properly augmenting one the matrix QLQR and the scalar RLQR From this procedure a
dimension in the control input matrix G and in the weighting good controller was obtained, and its weighting matrices are
matrix RLQR . given by
 
V. R ESULTS QLQR = diag 1 50 × 103 3000 2000 700 × 109
To evaluate the system performance and stability it is (44)
presented below the design of the converter and the LQR RLQR = 40 × 103 (45)
controller. Simulation results of the closed-loop system in
PSIM will be also presented. The main requirements assumed which leads to the gain vector
for the converter employed in the simulations are defined by  
K = 8.412 1.143 −0.445 0.691 −4183 (46)
Table I, which provide the guidelines for the converter design.
Based on the steady-state analysis presented at Section II the In order to evaluate the system performance and stability,
converter is designed and the obtained parameters are specified simulations of the closed-loop system in PSIM are carried out.
by Table II. The converter topology is implemented as in Fig. 1, and the
The impact of parametric variations over the dynamics of control law in (38) is implemented as in Fig. 3. Each state is
the converter is addressed by Fig. 4, where the trajectories measured by an appropriate sensor and the signal is sent to
of the open-loop poles are shown. It can be seen from the controller.
Fig. 4(a) that increasing L1 from 1 mH to 1 H leads to make The output voltage dynamic response is evaluated by means
a pair of poles faster while the other one gets slower, but of load variations. Initially, the converter starts with its
less oscillatory. Fig. 4(b) depicts the root-locus for variations nominal load and at 30 ms the load is reduced to 50 % of
of C1 , while fixing all other parameters, and one can observe its value (25 W). At 45 ms the load is changed back to the
that increasing values from 1 μF to 1 mF both pair of poles rated power of the converter. Results for the state variables
tends to the left. For increasing values of the intermediate and the control signal are depicted by Fig. 5.
inductor L2 from 1 mH to 23 mH, faster poles decrease its Fig. 5(a) depicts the output voltage, and the dashed lines
frequency while the slower ones became faster, as shown by highlights the ±1 % margin considered for the settling time
Fig. 4(c). Finally, increasing values of the output capacitor C2 evaluation. For this simulation, the worst response measured is
485

10000 49

5000
Imaginary (rad/s)

vout (V)
48
0

−5000 47
30 35 40 45 50 55 60
Time (ms)
−10000 (a)
−400 −300 −200 −100 0
Real (rad/s)
126
(a)

vC1 (V)
10000 124

5000
Imaginary (rad/s)

122

0 30 35 40 45 50 55 60
Time (ms)
(b)
−5000
0.6

−10000
−400 −300 −200 −100 0 0.4

iL1 (A)
Real (rad/s)
(b)
0.2
10000
0
30 35 40 45 50 55 60
5000
Imaginary (rad/s)

Time (ms)
(c)
0
1.5

−5000
iL2 (A)

1.0

−10000 0.5
−400 −300 −200 −100 0
Real (rad/s)
(c) 0
30 35 40 45 50 55 60
Time (ms)
10000
(d)

0.8
5000
Imaginary (rad/s)

0.6
Duty cycle (d)

0
0.4

−5000 0.2

−10000 0
30 35 40 45 50 55 60
−400 −300 −200 −100 0 Time (ms)
Real (rad/s)
(e)
(d)
Fig. 5. Simulation results for load changes from 100 % to 50 % and back;
Fig. 4. Root-locus for increasing values of a single parameter (a) L1 (a) output voltage vout ; (b) voltage at intermediate capacitor vC1 ; (c) input
from 1 mH to 1 H; (b) C1 from 1 μF to 1 mF; (c) L2 from 1 mH to 23 mH; inductor currents iL1 ; (d) intermediate inductor current iL2 ; (e) control
(d) C2 from 1 μF to 1 mF. signal d.

an undershoot of 1,43 % during the transient of load reduction, a maximum deviation of 1,6 % for the considered load step
at 30,25 ms. The overshoot of increasing load reaches 1,31 % simulation. As it can also be observed, inductor currents prove
at 45,18 ms. A settling time of 2 ms is observed for both the converter operates at MCC during all transients, being valid
transients. For the intermediate stage the voltage at C1 has the small-signal model presented above. Finally, at Fig. 5(e)
 486

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