CIW'fatl'M)

✓ External Memory
The i~s.tem designer is not limite d hy the amou nt of insemal RAM
and ROM available
on chap. Two ~ t e external memory spaces are made available by
dlt 16-bit PC and
OPTR ~ b! different contro l pins for enabl ing external ROM and RAM
chips. Internal
control c1rcu1try acxcsscs t h e ~ physical memory. depending apon
gate and lhe opcod e being executed. die machine cycle
There are !ieVCral reason, for addin g external memory. partic ularly progra
m memory.
when apply ing the 8051 in a system. WIien the project is in the
protot ype stage. the
expe nse-i n time and 111D11ey-of having• maskcl internal ROM made
for each program
"try.. is prohibitille. To alleviate this probJem. die manu
facturers make available an
EPROM \'CJ'Sion, the 8751, which hu 4K of on-ch ip EPRO
M Chat may be progr amme d
and erased as nceclcd as the program is developed. The resulting circui
t board ~ will
be identi cal to one that uses a factory-progtammed 8051.
The only draw '-cks to Ille 8751
are the specialized EPROM progr amme n that nast be used
to program the non-s tandar o
40-pin part. and the limit of ..only" 40J6 bytes of program
code.
The 8751 solution works well if the program will tit into 4K bytes.
Unforblnately,
many times. particularly if the program is written in a hig•le wel Jangu
aee. the program
size exceed,; 4K bytes. and an extern al progra m memo ry is neede
d. Again . the manu fac-
ture~ provid e a version for the job. the ROMteu 8031. The EA pin
I is groundr.d when
using the 8031. and all program code is contained in an cxter
ul EPRO M that may be as
I large as 64K bytes and that can be programmed 11sing standard
EPROM programmers.
I Elltemal RAM. which is accessed by the DPTR . may also be
ncedc:d when 128 bytes
of internal data storag e is nor sufficient. Extern al RAM. up
10 64K bytes . may abo be
added to any chip in the 8051 family.

Connecting External Memory

Fi~ 2.8 ~boWs.!f..!e
conncctioDs betv.,:cn ~~ I ~ external ~ :-0
_. - . . .i•-~-
consis ting of 16K bytes of EPRO M and 8K b ~ sta11e ~
nafRA ~-~_!lencVC! certai_n _J?p ~ i~
or
..w~ • ....__, ..._ ,___ .....__ - - • -'-'
ons ~ ~xccutcd. Extrmal ~ i s ~
~ figuration
8051 acces ses extet--
.. •

~ eneve r the EA (e"tem al acce58 ) pin is connected to groun

d or when the PC contains an
~~ hj,g!l~·tllan!fiTastadd~ n the~n~ a) 4~ bytes RO~ (OFff h~ ~8051 design.c.
_
can thus ~ internal and ellttcrnal ROM a■tomatically; lhe 8031. havin
must have EA grouiiaea . .
....,::....:...--.,..._., _...__........ _....._
·-----·------ -
-.-.-._.._..__._
_ g II() internal ROM •
~

., ~
urc f-9 s ~s the
.....J!'!'i' }l_ ~i_a ~ with.!~ ext~ I ~ - ~ cyc!e . ~!-
ing any memory access cycle, port O as tune mult1plexea. That
IS, 11 first provules the
to~ byte of the f6-bit memory address:1fien•actsas - a~ difcciioealc bus to write or
read a by'icof memoiyclata.Axt2 j;ovicleStliefiigh liya€of the IIICl11itid)' address dunng
1Fie'""
effilreniemorv·rcad1write·c~ lc-:- • · · --
., n :.;,;.;;:.::.,c. .......,
••• ...
The lower addRss byte from port O mu.q be latched iato an external
register to save
the byte~ Xddrw iiytc savci 's accomp(ish?f by the ALE
~ k. pulse that provide., the
coh'eUtifning for The ..37:tiype data latcb. Thc'port 0 pillS theft ht.com
a'aia~l>ui.·--·~ · ____ ..__ ..,_., ·-· ,..._ "-- · e fRC to serve a.c. a
- iffflcmemory acces s is for a byte of progr am code in ~ _!t(?M. ~
st<m:c na6fe) pin willg o low to.cnab~
~__§N CJ>l"O!!!m
ROM to placea byte of program code on the
aittb .s: If the
I.
access as
-
for a RAM byte. die\VI' (write ) or 1ffi (rad} pin.~ will go low.
1'

cna~i ng data ro flew,, bc:tW0Cff the RAM and the data bus. ._

•· The ROM may be expanded to 64K by using a 27~ J2 type EPRO

M and connecting
t~ . lf:maining pore 2 upper
add ~ Ii~ A 14-;A15 to the chip. -
At this time the largest mtic RAMs available are 32K in size: RAM
can b e ~
to 64K bJ using two 32K RAMs lhat are COll1ICCfed throo p ~•~
J I'
· - - - ......
~ f4orpoif2. -The
RGURE 2.8 External Memory Connections
16 ......
11 .... ------R
-----JN
29 1 - - - - - - - 4->sEN
R
D
22
26
27
22

26 A) 3
2 Al 2 2
25 Al 2 All' 23
N
24 Al l 23
Al O Zl
1 23
22
Al 0
A9
Zl
24 •A9- 24 6~
25 •AB• 25 BK
21 AS RAM
27128
19 A7• 3 161< ~A7 • 3
- - - - - - t 18 A6• 4
-- 117
-....,. 16 •A6• 4 EPROM
--_-_ _ 14

_....., 15 A5• 5 A5• 5

373 12 •A4• 6 •M• 6
8031
--
_ -_... 13
-4 3 •A3• 7
Latch 2 •A3• 7
5 ·A2' 8 •A2• 8
7 6 •Al• 9 •Al• 9
8 l 11 9 •AO• 1019 16 13 11 •AO- 1018 16 13 11
19 17 15 12 19 17 15 12
30 ~..,._....,....,,.......,_ALE ~
32 A07
I I
33 A06
34 ADS
35 A04
36 A03
37 ADZ
38 AOL
39 ADO

FIGURE 2.9 External Memory Timing

NJ-A7
! x"-_ 00 0
_ - _ ,----'; x__
PM 2 ,=x__~:~A8-·AI_S_ _ _~:x__
ALE Pulse
_____.,I ! ill lAtch Address
I
I
I
PSEN Pulse - - - - - - - - - - - - - - - - I PSEN ,,__
I _ _ __

Enable ROM
R...... IIOII .... PIIN
I
Read Pulse I
l RO j
Write Pulse
---------------~En.t>le Reed
l n jr---
Enattte Wri te
28 CHAPTER TINO

FIGURE 2.10 TCON and TMOD Function Registers

7 6 5 4 3 2 I 0

[m jm I I I
TFD TAO •EI j ,n I •Eo I rro j
lHE TIMER CONTltOl {TCON) SPEOAL RJNCTION REGISTER
Bit Symbol Function
7 TF 1 Timer 1 Overibw flag. Set when timer rolls from all ones to zero. Cleared when processor
vectors to execute interrupt seMCe routine located at program ~ 001 Bh.

6 TR 1 Timer 1 run control bit. Set to 1 by program to enable timer to CDUnt; deared to O l7f
program to halt timer. Does not reset timer.

5 TFO nmer O Overflow flag. Set when timer rolls from an ones to zero. Cleared when processor
vectors to execute interrupt service routine located at program address 0008h.

4 TRO Timer O run control bit. Set to 1 by program to enable timer to count; cleared to O by
program to halt timer. Does not reset timer.

3 IE 1 External interrupt 1 edge flag. Set to 1 when a high to low edge signal is ~ on port 3
pin 3.3 (INT1 ). Cleared when proces.s<>r vecto,s to interrupt service routine
located at program address 0013h. Not related to timer operations.

2 IT1 External interrupt 1 signal type control bit Set to 1 by program to enable external interrupt l
to be triggered by a faffing edge signal. Set to Oby program to enab6e a low level
s,gnal on extemal interrupt l to generate an interrupt

1 IEO External interrupt o edge flag. Set to 1 when a high to low edge signal is received on port 3
ptn 3.2 (INTO). Cleared when processor vectors to interrupt seNice routine located at
program address 0003h. Nol related lo timer operations.
Continued

first 32K RAM {OOOOh - 7FFFh) can ll~n be enabled when A I 5 of port 2 is low. and the
second 32K RAM (8000'1-FFFAI) when AIS is high, by using an inverter.
~ Note lhat the WR and RD signals arc alternate uses for port 3 pins 16 and 17. Also.
port O is usedfor the lower address byte and data; port 2 is ascd for upper address bits. The
u~ of cxtemal me~ consumes many of the port pins. leaving only port I and parts of
port 3 for general J/O.