MCP25625

CAN Controller with Integrated Transceiver

General Features CAN Transceiver Features
• Stand-Alone CAN 2.0B Controller with Integrated • VDDA: 4.5V to 5.5V
CAN Transceiver and Serial Peripheral • Implements ISO-11898-2 and ISO-11898-5
Interface (SPI) Standard Physical Layer Requirements
• Up to 1 Mb/s Operation • CAN Bus Pins are Disconnected when Device is
• Very Low Standby Current (10 µA, typical) Unpowered:
• Up to 10 MHz SPI Clock Speed - An unpowered node or brown-out event will
• Interfaces Directly with Microcontrollers with 2.7V not load the CAN bus
to 5.5V I/Os • Detection of Ground Fault:
• Available in SSOP-28L and 6x6 QFN-28L - Permanent Dominant detection on TXD
• Temperature Ranges: - Permanent Dominant detection on bus
- Extended (E): -40°C to +125°C • Power-on Reset and Voltage Brown-Out
Protection on VDDA Pin
CAN Controller Features • Protection Against Damage Due to Short-Circuit
Conditions (Positive or Negative Battery Voltage)
• VDD: 2.7 to 5.5V
• Protection Against High-Voltage Transients in
• Implements CAN 2.0B (ISO11898-1) Automotive Environments
• Three Transmit Buffers with Prioritization and • Automatic Thermal Shutdown Protection
Abort Features
• Suitable for 12V and 24V Systems
• Two Receive Buffers
• Meets or Exceeds Stringent Automotive Design
• Six Filters and Two Masks with Optional Filtering Requirements, Including “Hardware Require-
on the First Two Data Bytes ments for LIN, CAN and FlexRay Interfaces in
• Supports SPI Modes 0,0 and 1,1 Automotive Applications”, Version 1.3, May 2012
• Specific SPI Commands to Reduce SPI Overhead • High Noise Immunity Due to Differential Bus
• Buffer Full and Request-to-Send Pins are Implementation
Configurable as General Purpose I/Os • High-ESD Protection on CANH and CANL, Meets
• One Interrupt Output Pin IEC61000-4-2 up to ±8 kV

Description
The MCP25625 is a complete, cost-effective and small
footprint CAN solution that can be easily added to a
microcontroller with an available SPI interface.
The MCP25625 interfaces directly with microcontrollers
operating at 2.7V to 5.5V; there are no external level
shifters required. In addition, the MCP25625 connects
directly to the physical CAN bus, supporting all
requirements for CAN high-speed transceivers.
The MCP25625 meets the automotive requirements for
high-speed (up to 1 Mb/s), low quiescent current,
Electromagnetic Compatibility (EMC) and Electrostatic
Discharge (ESD).

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MCP25625
Package Types
MCP25625
6x6 QFN*
MCP25625

24 Rx0BF

23 Rx1BF

22 GND
SSOP

26 SCK

25 INT
28 SO

27 SI
VIO 1 28 RXD
NC 2 27 VDDA CS 1 21 OSC1
CANL 3 26 VSS
CANH 4 25 NC RESET 2 20 OSC2
STBY 5 24 TXD
VDD 3 19 VDDA
Tx1RTS 6 23 Tx0RTS
Tx2RTS 7 22 CLKOUT
TxCAN 4 18 VSS
OSC2 8 21 RxCAN
OSC1 9 20 TxCAN
RxCAN 5 17 NC
GND 10 19 VDD
Rx1BF 11 18 RESET
CLKOUT 6 16 TXD
Rx0BF 12 17 CS
EXP-29
INT 13 16 SO
Tx0RTS 7 15 STBY
SCK 14 15 SI

10

12

13

14
11
8

9
Tx1RTS

Tx2RTS

RXD

VIO

CANL

CANH

NC
* Includes Exposed Thermal Pad (EP); see Table 1-1.

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 MCP25625
1.0 DEVICE OVERVIEW 1.1 Block Diagram
A typical CAN solution consists of a CAN controller that Figure 1-1 shows the block diagram of the MCP25625.
implements the CAN protocol, and a CAN transceiver The CAN transceiver is illustrated in the top half of the
that serves as the interface to the physical CAN bus. block diagram, see Section 6.0 “CAN Transceiver”
The MCP25625 integrates both the CAN controller and for more details.
the CAN transceiver. Therefore, it is a complete CAN The CAN controller is depicted at the bottom half of the
solution that can be easily added to a microcontroller block diagram, and described in more detail in
with an SPI interface. Section 3.0 “CAN Controller”.
FIGURE 1-1: MCP25625 BLOCK DIAGRAM
VIO VDDA

Digital I/O Thermal POR

Supply Protection UVLO

VIO

TXD
Permanent
Dominant Detect
CANH
Driver
VIO and
Slope Control CANL
STBY
Mode
Control

VSS

Wake-up CANH
LP_RX
Filter CANL

RXD
Receiver
CANH
HS_RX
CANL

CS
Tx Handler
Tx RxCAN
SCK Prioritization
CAN
SI SPI IF Protocol
Rx Handler Engine TxCAN
Acceptance
SO Filters and
Masks

VDD
INT

Control Logic
Rx0BF GND
Registers: Configuration, Control and Interrupts

Rx1BF

OSC1
Tx0RTS
OSC2
Tx1RTS Crystal
Oscillator
CLKOUT
Tx2RTS

RESET

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MCP25625
1.2 Pin Out Description
The descriptions of the pins are listed in Table 1-1.

TABLE 1-1: MCP25625 PIN DESCRIPTION

6x6
Pin Name SSOP Block(1) Pin Type Description
QFN
VIO 11 1 CAN Transceiver P Digital I/O Supply Pin for CAN Transceiver
NC 14 2 — — No Connection
CANL 12 3 CAN Transceiver HV I/O CAN Low-Level Voltage I/O
CANH 13 4 CAN Transceiver HV I/O CAN High-Level Voltage I/O
STBY 15 5 CAN Transceiver I Standby Mode Input
Tx1RTS 8 6 CAN Controller I TXB1 Request-to-Send
Tx2RTS 9 7 CAN Controller I TXB2 Request-to-Send
OSC2 20 8 CAN Controller O External Oscillator Output
OSC1 21 9 CAN Controller I External Oscillator Input
GND 22 10 CAN Controller P Ground
Rx1BF 23 11 CAN Controller O RxB1 Interrupt
Rx0BF 24 12 CAN Controller O RxB0 Interrupt
INT 25 13 CAN Controller O Interrupt Output
SCK 26 14 CAN Controller I SPI Clock Input
SI 27 15 CAN Controller I SPI Data Input
SO 28 16 CAN Controller O SPI Data Output
CS 1 17 CAN Controller I SPI Chip Select Input
RESET 2 18 CAN Controller I Reset Input
VDD 3 19 CAN Controller P Power for CAN Controller
TxCAN 4 20 CAN Controller O Transmit Output to CAN Transceiver
RXCAN 5 21 CAN Controller I Receive Input from CAN Transceiver
CLKOUT 6 22 CAN Controller O Clock Output/SOF
Tx0RTS 7 23 CAN Controller I TXB0 Request-to-Send
TXD 16 24 CAN Transceiver I Transmit Data Input from CAN Controller
NC 17 25 — — No Connection
VSS 18 26 CAN Transceiver P Ground
VDDA 19 27 CAN Transceiver P Power for CAN Transceiver
RXD 10 28 CAN Transceiver O Receive Data Output to CAN Controller
EP 29 — — — Exposed Thermal Pad
Legend: P = Power, I = Input, O = Output, HV = High Voltage.
Note 1: See Section 3.0 “CAN Controller” and Section 6.0 “CAN Transceiver” for further information.

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 MCP25625
1.3 Typical Application The TXD and RXD pins of the CAN transceiver must be
externally connected to the TxCAN and RxCAN pins of
Figure 1-2 shows an example of a typical application the CAN controller.
of the MCP25625. In this example, the microcontroller
operates at 3.3V. The SPI interface is used to configure and control the
CAN controller.
VDDA supplies the CAN transceiver and must be
connected to 5V. The INT pin of the MCP25625 signals an interrupt to
the microcontroller. Interrupts need to be cleared by
VDD, VIO of the MCP25625 are connected to the VDD the microcontroller through SPI.
of the microcontroller. The digital supply can range
from 2.7V to 5.5V. Therefore, the I/O of the MCP25625 The usage of RxnBF and TxnRTS is optional, since
is connected directly to the microcontroller, no level the functions of these pins can be accessed through
shifters are required. SPI. The RESET pin can optionally be pulled up to the
VDD of the MCP25625 using a 10 k resistor.
The CLKOUT pin provides the clock to the
microcontroller.

FIGURE 1-2: MCP25625 INTERFACING WITH A 3.3V MICROCONTROLLER

VBAT 5V LDO

3.3V LDO

0.1 μF
0.1 μF 0.1 μF 0.1 μF

VDD VDD VIO VDDA

TXD CANH CANH

RXD 120
Rx CAN CANL CANL

Tx CAN
PIC® Microcontroller

RA0 STBY
RA1 CS
MCP25625

SCK SCK

SDO SI

SDI SO
Optional
INT0 INT
INT1 Rx 0BF
INT2 Rx 1BF
RA2 TxRTS
RA3 TxRTS
22 pF
RA4 TxRTS OSC2

RA5 RESET
22 pF
OSC1 CLKOUT OSC1
VSS GND VSS

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MCP25625
NOTES:

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 MCP25625
2.0 MODES OF OPERATION 2.3 Configuration Mode
The MCP25625 must be initialized before activation. This
2.1 CAN Controller Modes of is only possible if the device is in Configuration mode.
Operation Configuration mode is automatically selected after power-
up, a Reset or can be entered from any other mode by
The CAN controller has five modes of operation:
setting the REQOPx bits in the CANCTRL register. When
• Configuration mode Configuration mode is entered, all error counters are
• Normal mode cleared. Configuration mode is the only mode where the
• Sleep mode following registers are modifiable:
• Listen-Only mode • CNF1, CNF2, CNF3
• Loopback mode • TXRTSCTRL
• Acceptance Filter registers
The operational mode is selected via the
REQOP[2:0] bits in the CANCTRL register (see
Register 4-34). 2.4 Normal Mode
When changing modes, the mode will not actually Normal mode is the standard operating mode of the
change until all pending message transmissions are MCP25625. In this mode, the device actively monitors
complete. The requested mode must be verified by all bus messages and generates Acknowledge bits,
reading the OPMOD[2:0] bits in the CANSTAT register error frames, etc. This is also the only mode in which
(see Register 4-35). the MCP25625 transmits messages over the CAN bus.
Both the CAN controller and the CAN transceiver must
2.2 CAN Transceiver Modes of be in Normal mode.
Operation
The CAN transceiver has two modes of operation:
2.5 Sleep/Standby Mode
• Normal mode The CAN controller has an internal Sleep mode that is
• Standby mode used to minimize the current consumption of the
device. The SPI interface remains active for reading
Normal mode is selected by applying a low level to the even when the MCP25625 is in Sleep mode, allowing
STBY pin. The driver block is operational and can drive access to all registers.
the bus pins. The slopes of the output signals on CANH
and CANL are optimized to produce minimal Electro- Sleep mode is selected via the REQOPx bits in the
magnetic Emissions (EME). The high-speed differential CANCTRL register. The OPMODx bits in the CANSTAT
receiver is active. register indicate the operation mode. These bits should
be read after sending the SLEEP command to the
Standby mode is selected by applying a high level to MCP25625. The MCP25625 is active and has not yet
the STBY pin. In Standby mode, the transmitter and the entered Sleep mode until these bits indicate that Sleep
high-speed part of the receiver are switched off to min- mode has been entered.
imize power consumption. The low-power receiver and
the wake-up filter are enabled in order to monitor the When in Sleep mode, the MCP25625 stops its internal
bus for activity. The receive pin (RXD) will show a oscillator. The MCP25625 will wake-up when bus
delayed representation of the CAN bus, due to the activity occurs or when the microcontroller sets via the
wake-up filter. SPI interface. The WAKIF bit in the CANINTF register
will “generate” a wake-up attempt (the WAKIE bit in the
CANINTE register must also be set in order for the
wake-up interrupt to occur).
The CAN transceiver must be in Standby mode in order
to take advantage of the low standby current of the
transceiver. After a wake-up, the microcontroller must
put the transceiver back into Normal mode using the
STBY pin.

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MCP25625
2.5.1 WAKE-UP FUNCTIONS For Auto-Baud Detection (ABD), it is necessary that at
least two other nodes are communicating with each
The CAN transceiver will monitor the CAN bus for activity.
other. The baud rate can be detected empirically by
The wake-up filter inside the transceiver is enabled to
testing different values until valid messages are
avoid a wake-up due to noise. In case there is activity on
received.
the CAN bus, the RXD pin will go low. The CAN bus wake-
up function requires both CAN transceiver supply volt- Listen-Only mode is a silent mode, meaning no
ages to be in a valid range: VDDA and VIO. messages will be transmitted while in this mode
(including error flags or Acknowledge signals). In
The CAN controller will detect a falling edge on the
Listen-Only mode, both valid and invalid messages will
RxCAN pin and interrupt the microcontroller if the
be received regardless of filters and masks or
wake-up interrupt is enabled.
RXM[1:0] bits in the RXBxCTRL registers. The error
Since the internal oscillator is shut down while in Sleep counters are reset and deactivated in this state. The
mode, it will take some amount of time for the oscillator Listen-Only mode is activated by setting the REQOPx
to start-up and the device to enable itself to receive bits in the CANCTRL register.
messages. This Oscillator Start-up Timer (OST) is
defined as 128 TOSC. 2.7 Loopback Mode
The device will ignore the message that caused the Loopback mode will allow internal transmission of
wake-up from Sleep mode, as well as any messages messages from the transmit buffers to the receive
that occur while the device is “waking up”. The device buffers without actually transmitting messages on the
will wake-up in Listen-Only mode. CAN bus. This mode can be used in system
The microcontroller must set both the CAN controller development and testing.
and CAN transceiver to Normal mode before the In this mode, the ACK bit is ignored and the device will
MCP25625 will be able to communicate on the bus. allow incoming messages from itself, just as if they
were coming from another node. The Loopback mode
2.6 Listen-Only Mode is a silent mode, meaning no messages will be trans-
mitted while in this state (including error flags or
Listen-Only mode provides a means for the MCP25625
Acknowledge signals). The TxCAN pin will be in a
to receive all messages (including messages with
Recessive state.
errors) by configuring the RXM[1:0] bits in the
RXBxCTRL register. This mode can be used for bus The filters and masks can be used to allow only
monitor applications or for detecting the baud rate in particular messages to be loaded into the receive
“hot plugging” situations. registers. The masks can be set to all zeros to provide
a mode that accepts all messages. The Loopback
mode is activated by setting the REQOPx bits in the
CANCTRL register.

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 MCP25625
3.0 CAN CONTROLLER 3.2 Control Logic
The CAN controller implements the CAN protocol The control logic block controls the setup and operation
Version 2.0B. It is compatible with the ISO 11898-1 of the MCP25625 and contains the registers.
standard. Interrupt pins are provided to allow greater system
Figure 3-1 illustrates the block diagram of the CAN flexibility. There is one multipurpose interrupt pin (as
controller. The CAN controller consists of the following well as specific interrupt pins) for each of the receive
major blocks: registers that can be used to indicate a valid message
has been received and loaded into one of the receive
• CAN protocol engine
buffers. Use of the specific interrupt pins is optional.
• TX handler The general purpose interrupt pin, as well as Status
• RX handler registers (accessed via the SPI interface), can also be
• SPI interface used to determine when a valid message has been
• Control logic with registers and interrupt logic received.
• I/O pins Additionally, there are three pins available to initiate
• Crystal oscillator immediate transmission of a message that has been
loaded into one of the three transmit registers. Use of
3.1 CAN Module these pins is optional, as initiating message transmis-
sions can also be accomplished by utilizing control
The CAN protocol engine, together with the TX and RX registers accessed via the SPI interface.
handlers, provide all the functions required to receive and
transmit messages on the CAN bus. Messages are trans- 3.3 SPI Protocol Block
mitted by first loading the appropriate message buffers
The microcontroller interfaces to the device via the SPI
and control registers. Transmission is initiated by using
interface. Registers can be accessed using the SPI
control register bits via the SPI interface or by using the
READ and WRITE commands. Specialized SPI
transmit enable pins. Status and errors can be checked by
commands reduce the SPI overhead.
reading the appropriate registers. Any message detected
on the CAN bus is checked for errors and then matched
against the user-defined filters to see if it should be moved
into one of the two receive buffers.

FIGURE 3-1: CAN CONTROLLER BLOCK DIAGRAM

CS
Tx Handler
Tx RxCAN
SCK Prioritization
CAN
SI SPI IF Protocol
Rx Handler Engine TxCAN
Acceptance
SO Filters and
Masks

VDD
INT

Control Logic
Rx0BF Registers: Configuration, Control and Interrupts GND

Rx1BF

OSC1
Tx0RTS
OSC2
Tx1RTS Crystal
Oscillator
CLKOUT
Tx2RTS

RESET

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MCP25625
3.4 CAN Buffers and Filters
Figure 3-2 shows the CAN buffers and filters in more
detail. The MCP25625 has three transmit and two
receive buffers, two acceptance masks (one per
receive buffer) and a total of six acceptance filters.

FIGURE 3-2: CAN BUFFERS AND PROTOCOL ENGINE

BUFFERS Acceptance Mask

RXM1
Acceptance Filter
RXF2
A
A Acceptance Mask Acceptance Filter c
TXB0 TXB1 TXB2 RXM0 RXF3
c c
MESSAGE

MESSAGE

MESSAGE
c Acceptance Filter Acceptance Filter e
e
TXREQ

TXREQ

TXREQ

p
TXERR

TXERR

TXERR RXF0 RXF4

MLOA

MLOA

MLOA
ABTF

ABTF

ABTF

p t
Acceptance Filter Acceptance Filter
t RXF1 RXF5

R R
M
X Identifier Identifier X
Message A
B B
Queue B
0 1
Control
Transmit Byte Sequencer Data Field Data Field

PROTOCOL Receive REC

Error
ENGINE Counter TEC

Transmit ErrPas
Error BusOff
Counter
Transmit[7:0] Receive[7:0]
Shift[14:0]
{Transmit[5:0], Receive[8:0]}
Comparator
Protocol
Finite SOF
State
CRC[14:0] Machine

Bit
Transmit
Timing Clock
Logic
Logic Generator

TX RX
Configuration
Registers

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 MCP25625
3.5 CAN Protocol Engine 3.5.3 ERROR MANAGEMENT LOGIC
The CAN protocol engine combines several functional The Error Management Logic (EML) is responsible for
blocks, shown in Figure 3-3 and described below. the Fault confinement of the CAN device. Its two count-
ers, the Receive Error Counter (REC) and the Transmit
3.5.1 PROTOCOL FINITE STATE MACHINE Error Counter (TEC), are incremented and decremented
by commands from the bit stream processor. Based on
The heart of the engine is the Finite State Machine
the values of the error counters, the CAN controller is set
(FSM). The FSM is a sequencer that controls the
into the states: error-active, error-passive or bus-off.
sequential data stream between the TX/RX Shift
register, the CRC register and the bus line. The FSM 3.5.4 BIT TIMING LOGIC
also controls the Error Management Logic (EML) and
the parallel data stream between the TX/RX Shift The Bit Timing Logic (BTL) monitors the bus line input
registers and the buffers. The FSM ensures that the and handles the bus-related bit timing according to the
processes of reception, arbitration, transmission and CAN protocol. The BTL synchronizes on a Recessive-
error signaling are performed according to the CAN to-Dominant bus transition at Start-of-Frame (hard
protocol. The automatic retransmission of messages synchronization) and on any further Recessive-to-
on the bus line is also handled by the FSM. Dominant bus line transition if the CAN controller itself
does not transmit a Dominant bit (resynchronization).
3.5.2 CYCLIC REDUNDANCY CHECK The BTL also provides programmable time segments
to compensate for the propagation delay time, phase
The Cyclic Redundancy Check register generates the
shifts and to define the position of the sample point
Cyclic Redundancy Check (CRC) code, which is
within the bit time. The programming of the BTL
transmitted after either the control field (for messages
depends on the baud rate and external physical delay
with 0 data bytes) or the data field and is used to check
times.
the CRC field of incoming messages.

FIGURE 3-3: CAN PROTOCOL ENGINE BLOCK DIAGRAM

RX TX
Bit Timing Logic Transmit Logic

SAM

REC
Sample[2:0] Receive
Error Counter
TEC
StuffReg[5:0]
Transmit
ErrPas
Majority Error Counter
Decision BusOff

BusMon

Comparator

CRC[14:0]

Protocol SOF
FSM
Comparator

Shift[14:0]
(Transmit[5:0], Receive[7:0])

Receive[7:0] Transmit[7:0]

RecData[7:0] TrmData[7:0]
Interface to Standard Buffer Rec/Trm Addr.

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MCP25625
3.6 Message Transmission The TXP[1:0] bits in the TXBxCTRL register (see
Register 4-1) allow the selection of four levels of transmit
The transmit registers are described in Section 4.1 priority for each transmit buffer individually. A buffer with
“Message Transmit Registers”. the TXPx bits equal to ‘11’ has the highest possible
priority, while a buffer with the TXPx bits equal to ‘00’ has
3.6.1 TRANSMIT BUFFERS the lowest possible priority.
The MCP25625 implements three transmit buffers.
Each of these buffers occupies 14 bytes of SRAM and 3.6.3 INITIATING TRANSMISSION
is mapped into the device memory map. In order to initiate message transmission, the TXREQ
The first byte, TXBxCTRL, is a control register bit in the TXBxCTRL register must be set for each
associated with the message buffer. The information in buffer to be transmitted. This can be accomplished by:
this register determines the conditions under which the • Writing to the register via the SPI WRITE
message will be transmitted and indicates the status of command
the message transmission (see Register 4-1).
• Sending the SPI RTS command
Five bytes are used to hold the Standard and Extended • Setting the TxnRTS pin low for the particular
Identifiers, as well as other message arbitration transmit buffer(s) that is to be transmitted
information (see Registers 4-3 through 4-7). The last
eight bytes are for the eight possible data bytes of the If transmission is initiated via the SPI interface, the
message to be transmitted (see Register 4-8). TXREQ bit can be set at the same time as the TXPx
priority bits.
At a minimum, the TXBxSIDH, TXBxSIDL and
TXBxDLC registers must be loaded. If data bytes are When the TXREQ is set, the ABTF, MLOA and TXERR
present in the message, the TXBxDn registers must also bits in the TXBxCTRL register will be cleared
be loaded. If the message is to use Extended Identifiers, automatically.
the TXBxEIDn registers must also be loaded and the Note: Setting the TXREQ bit in the TXBxCTRL
EXIDE bit in the TXBxSIDL register should be set. register does not initiate a message
Prior to sending the message, the microcontroller must transmission. It merely flags a message
initialize the TXxIE bit in the CANINTE register to buffer as being ready for transmission.
enable or disable the generation of an interrupt when Transmission will start when the device
the message is sent. detects that the bus is available.

Note: The TXREQ bit in the TXBxCTRL register Once the transmission has completed successfully, the
must be clear (indicating the transmit buf- TXREQ bit will be cleared, the TXxIF bit in the
fer is not pending transmission) before CANINTF register will be set and an interrupt will be
writing to the transmit buffer. generated if the TXxIE bit in the CANINTE register is
set.
3.6.2 TRANSMIT PRIORITY If the message transmission fails, the TXREQ bit will
remain set. This indicates that the message is still
Transmit priority is a prioritization within the CAN
pending for transmission and one of the following
controller of the pending transmittable messages. This
condition flags will be set:
is independent from, and not necessarily related to, any
prioritization implicit in the message arbitration scheme • If the message started to transmit but
built into the CAN protocol. encountered an error condition, the TXERR bit in
the TXBxCTRL register and the MERRF bit in the
Prior to sending the Start-of-Frame (SOF), the priority
CANINTF register will be set, and an interrupt will
of all buffers that are queued for transmission are com-
be generated on the INT pin if the MERRE bit in
pared. The transmit buffer with the highest priority will
the CANINTE register is set.
be sent first. For example, if Transmit Buffer 0 has a
higher priority setting than Transmit Buffer 1, Buffer 0 • If arbitration is lost, the MLOA bit in the
will be sent first. TXBxCTRL register will be set.

If two buffers have the same priority setting, the buffer Note: If One-Shot mode is enabled (OSM bit in
with the highest buffer number will be sent first. For the CANCTRL register), the above condi-
example, if Transmit Buffer 1 has the same priority tions will still exist. However, the TXREQ bit
setting as Transmit Buffer 0, Buffer 1 will be sent first. will be cleared and the message will not
attempt transmission a second time.

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 MCP25625
3.6.4 ONE-SHOT MODE 3.6.6 ABORTING TRANSMISSION
One-Shot mode ensures that a message will only The MCU can request to abort a message in a specific
attempt to transmit one time. Normally, if a CAN message buffer by clearing the associated TXREQ bit.
message loses arbitration or is destroyed by an error In addition, all pending messages can be requested to
frame, the message is retransmitted. With One-Shot be aborted by setting the ABAT bit in the CANCTRL
mode enabled, a message will only attempt to transmit register. This bit MUST be reset (typically, after the
one time, regardless of arbitration loss or error frame. TXREQ bits have been verified to be cleared) to con-
One-Shot mode is required to maintain time slots in tinue transmitting messages. The ABTF flag in the
deterministic systems, such as TTCAN. TXBxCTRL register will only be set if the abort was
requested via the ABAT bit in the CANCTRL register.
3.6.5 TxnRTS PINS Aborting a message by resetting the TXREQ bit does
The TxnRTS pins are input pins that can be configured NOT cause the ABTF bit to be set.
as: Note 1: Messages that were transmitting when
• Request-to-Send inputs, which provide an the abort was requested will continue to
alternative means of initiating the transmission of transmit. If the message does not suc-
a message from any of the transmit buffers cessfully complete transmission (i.e., lost
• Standard digital inputs arbitration or was interrupted by an error
frame), it will then be aborted.
Configuration and control of these pins is accomplished
using the TXRTSCTRL register (see Register 4-2). The 2: When One-Shot mode is enabled, if the
TXRTSCTRL register can only be modified when message is interrupted due to an error
the CAN controller is in Configuration mode (see frame or loss of arbitration, the ABTF bit
Section 2.0 “Modes of Operation”). If configured to in the TXBxCTRL register will be set.
operate as a Request-to-Send pin, the pin is mapped
into the respective TXREQ bit in the TXBxCTRL regis-
ter for the transmit buffer. The TXREQ bit is latched by
the falling edge of the TxnRTS pin. The TxnRTS pins
are designed to allow them to be tied directly to the
RxnBF pins to automatically initiate a message
transmission when the RxnBF pin goes low.
The TxnRTS pins have internal pull-up resistors of
100 k (nominal).

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MCP25625
FIGURE 3-4: TRANSMIT MESSAGE FLOWCHART

Start
The message transmission
sequence begins when the
device determines that the
TXREQ bit in the TXBxCTRL
register for any of the transmit
registers has been set.
No
Are Any TXREQ
Bits = 1?

Yes
Clearing the TXREQ bit in TXBxCTRL
Clear: register while it is set, or setting the
ABTF
MLOA ABAT bit in the CANCTRL register
TXERR before the message has started
in TXBxCTRL Register transmission, will abort the message.

Is Is
CAN Bus Available to No No
TXREQ = 0
Start Transmission? or ABAT = 1?

Yes Yes

Examine TXP[1:0] in the TXBxCTRL Register

to Determine Highest Priority Message

Transmit Message

Message
Was No Message Error or Error
Message Transmitted Lost Arbitration?
Successfully?
Set TXERR
Yes Lost
Clear TXREQ Arbitration

MERRE = 1 in Yes
CANINTE Register?
Yes
Generate Set MLOA
Interrupt TXxIE = 1?
No
Generate
Interrupt
No

Set Set MERRF in

TXxIF in CANTINF Register CANTINF Register
The TXxIE bit in the CANINTE
register determines if an
interrupt should be generated
when a message is
successfully transmitted.

GO TO START

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 MCP25625
3.7 Message Reception 3.7.2 RECEIVE PRIORITY
The registers required for message reception RXB0, the higher priority buffer, has one mask and two
are described in Section 4.2 “Message Receive message acceptance filters associated with it. The
Registers”. received message is applied to the mask and filters for
RXB0 first.
3.7.1 RECEIVE MESSAGE BUFFERING RXB1 is the lower priority buffer, with one mask and
The MCP25625 includes two full receive buffers with four acceptance filters associated with it.
multiple acceptance filters for each. There is also a In addition to the message being applied to the RB0
separate Message Assembly Buffer (MAB) that acts as mask and filters first, the lower number of acceptance
a third receive buffer (see Figure 3-6). filters makes the match on RXB0 more restrictive and
implies a higher priority for that buffer.
3.7.1.1 Message Assembly Buffer
When a message is received, the RXBxCTRL[3:0] bits
Of the three receive buffers, the MAB is always will indicate the acceptance filter number that enabled
committed to receiving the next message from the bus. reception and whether the received message is a
The MAB assembles all messages received. These remote transfer request.
messages will be transferred to the RXBx buffers (see
Registers 4-12 to 4-17) only if the acceptance filter 3.7.2.1 Rollover
criteria is met.
Additionally, the RXB0CTRL register can be configured
3.7.1.2 RXB0 and RXB1 such that, if RXB0 contains a valid message and
another valid message is received, an overflow error
The remaining two receive buffers, called RXB0 and will not occur and the new message will be moved into
RXB1, can receive a complete message from the RXB1, regardless of the acceptance criteria of RXB1.
protocol engine via the MAB. The MCU can access one
buffer, while the other buffer is available for message 3.7.2.2 RXM[1:0] Bits
reception, or for holding a previously received
The RXM[1:0] bits in the RXBxCTRL register set
message.
special Receive modes. Normally, these bits are
Note: The entire content of the MAB is moved cleared to ‘00’ to enable reception of all valid messages
into the receive buffer once a message is as determined by the appropriate acceptance filters. In
accepted. This means that regardless of this case, the determination of whether or not to receive
the type of identifier (Standard or standard or extended messages is determined by the
Extended) and the number of data bytes EXIDE bit in the RFXxSIDL register.
received, the entire receive buffer is If the RXMx bits are set to ‘11’, the buffer will receive all
overwritten with the MAB contents. messages, regardless of the values of the acceptance
Therefore, the contents of all registers in filters. Also, if a message has an error before the End-
the buffer must be assumed to have been of-Frame (EOF), that portion of the message
modified when any message is received. assembled in the MAB before the error frame will be
loaded into the buffer. This mode has some value in
3.7.1.3 Receive Flags/interrupts debugging a CAN system and would not be used in an
When a message is moved into either of the receive actual system environment.
buffers, the appropriate RXxIF bit in the CANINTF reg- Setting the RXMx bits to ‘01’ or ‘10’ is not
ister is set. This bit must be cleared by the MCU in recommended.
order to allow a new message to be received into the
buffer. This bit provides a positive lockout to ensure
that the MCU has finished with the message before the
CAN controller attempts to load a new message into
the receive buffer.
If the RXxIE bit in the CANINTE register is set, an inter-
rupt will be generated on the INT pin to indicate that a
valid message has been received. In addition, the
associated RxnBF pin will drive low if configured as a
receive buffer full pin. See Section 3.7.4 “Rx0BF and
Rx1BF Pins” for details.

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MCP25625
3.7.3 START-OF-FRAME SIGNAL 3.7.4.1 Disabled
If enabled, the Start-of-Frame signal is generated on The RxnBF pins can be disabled to the high-
the SOF bit at the beginning of each CAN message impedance state by clearing the BxBFE bit in the
detected on the RxCAN pin. BFPCTRL register.
The RxCAN pin monitors an Idle bus for a Recessive-
3.7.4.2 Configured as Buffer Full
to-Dominant edge. If the Dominant condition remains
until the sample point, the MCP25625 interprets this as The RxnBF pins can be configured to act as either
a SOF and a SOF pulse is generated. If the Dominant buffer full interrupt pins or as standard digital outputs.
condition does not remain until the sample point, the Configuration and status of these pins is available via
MCP25625 interprets this as a glitch on the bus and no the BFPCTRL register (Register 4-11). When set to
SOF signal is generated. Figure 3-5 illustrates SOF operate in Interrupt mode (by setting the BxBFE and
signaling and glitch filtering. BxBFM bits in the BFPCTRL register), these pins are
active-low and are mapped to the RXxIF bit in the
As with One-Shot mode, one use for SOF signaling is
CANINTF register for each receive buffer. When this bit
for TTCAN-type systems. In addition, by monitoring
goes high for one of the receive buffers (indicating that
both the RxCAN pin and the SOF bit, an MCU can
a valid message has been loaded into the buffer), the
detect early physical bus problems by detecting small
corresponding RxnBF pin will go low. When the RXxIF
glitches before they affect the CAN communication.
bit is cleared by the MCU, the corresponding interrupt
3.7.4 Rx0BF AND Rx1BF PINS pin will go to the logic-high state until the next message
is loaded into the receive buffer.
In addition to the INT pin, which provides an interrupt
signal to the MCU for many different conditions, the
Receive Buffer Full pins (Rx0BF and Rx1BF) can be
used to indicate that a valid message has been loaded
into RXB0 or RXB1, respectively. The pins have three
different configurations (see Table 3-1):
1. Disabled
2. Buffer Full Interrupt
3. Digital Output

FIGURE 3-5: START-OF-FRAME SIGNALING

Normal SOF Signaling

START-OF-FRAME BIT ID BIT

Sample
Point
RxCAN

SOF

Glitch Filtering
EXPECTED START-OF-FRAME BIT

Expected Sample
Point BUS IDLE

RxCAN

SOF

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 MCP25625
3.7.4.3 Configured as Digital Output TABLE 3-1: CONFIGURING RxnBF PINS
When used as digital outputs, the BxBFM bits in the
BnBFE BnBFM BnBFS Pin Status
BFPCTRL register must be cleared and the BxBFE bits
must be set for the associated buffer. In this mode, the 0 X X Disabled, high-impedance
state of the pin is controlled by the BxBFS bits in the 1 1 X Receive buffer interrupt
same register. Writing a ‘1’ to the BxBFS bits will cause
1 0 0 Digital output = 0
a high level to be driven on the associated buffer full
pin, while a ‘0’ will cause the pin to drive low. When 1 0 1 Digital output = 1
using the pins in this mode, the state of the pin should
be modified only by using the SPI BIT MODIFY
command to prevent glitches from occurring on either
of the buffer full pins.

FIGURE 3-6: RECEIVE BUFFER BLOCK DIAGRAM

Acceptance Mask
RXM1

Acceptance Filter
RXF2

Acceptance Mask Acceptance Filter

RXM0 RXF3
A
c
Acceptance Filter Acceptance Filter c
RXF0 RXF4 e
A p
c t
c Acceptance Filter Acceptance Filter
e RXF1 RXF5
p
t

R R
Identifier M Identifier
X X
A
B B
B
0 1

Data Field Data Field

Note: Messages received in the MAB are initially applied to the mask and filters of RXB0. In addition,
only one filter match occurs (e.g., if the message matches both RXF0 and RXF2, the match will
be for RXF0 and the message will be moved into RXB0).

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MCP25625
FIGURE 3-7: RECEIVE FLOW FLOWCHART

Start

No Detect Start of
Message?

Yes

Begin Loading Message into

Message Assembly Buffer (MAB)

Generate Valid
No Message
Error
Frame Received?

Yes

Meets Meets
Yes No Yes
a Filter Criteria a Filter Criteria
for RXB0? for RXB1?

No

Go to Start
Determines if the Receive
register is empty and able
to accept a new message.

Determines if RXB0 can roll

over into RXB1 if it is full.

Is No Is Yes
RX0IF = 0? BUKT = 1?

Yes No

Generate Overflow Error: Generate Overflow Error: No Is

Move Message into RXB0 RX1IF = 0?
Set RX0OVR in EFLG Reg. Set RX1OVRin EFLG Reg.

Set RX0IF = 1 in CANINTF Reg. Yes

Is Move Message into RXB1

ERRIE = 1 No
Set FILHIT0 in RXB0CTRL Register
in CANINTE
According to which Filter Criteria Set RX1IF = 1 in CANINTF Reg.
Register?

Yes Set FILHIT[2:0] in RXB1CTRL

Register According to which
Generate Filter Criteria was Met
Interrupt on INT Go to Start

RX0IE = 1 Yes RX1IE = 1 in

Yes Generate
in CANINTE Interrupt on INT CANINTE Register?
Register?

Set CANSTAT[3:0] according RXB1

RXB0
No to which receive buffer the No
message was loaded into.

Are B0BFM = 1 Yes Are B1BFM = 1

Yes
in BFPCTRL Reg. and Set RXBF0 Set RXBF1 in BFPCTRL Reg. and
B0BFE = 1 Pin = 0 Pin = 0 B1BFE = 1
in BF1CTRL Reg.? in BF1CTRL Reg.?

No
No

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 MCP25625
3.7.5 MESSAGE ACCEPTANCE FILTERS 3.7.5.2 Filter Matching
AND MASKS The filter masks (see Registers 4-22 through 4-25)
The message acceptance filters and masks are used to are used to determine which bits in the identifier are
determine if a message in the Message Assembly examined with the filters. A truth table is shown in
Buffer should be loaded into either of the receive Table 3-2 that indicates how each bit in the identifier is
buffers (see Figure 3-9). Once a valid message has compared to the masks and filters to determine if the
been received into the MAB, the identifier fields of the message should be loaded into a receive buffer. The
message are compared to the filter values. If there is a mask essentially determines which bits to apply the
match, that message will be loaded into the appropriate acceptance filters to. If any mask bit is set to a zero,
receive buffer. that bit will automatically be accepted, regardless of
the filter bit.
The registers required for message filtering are described
in Section 4.3 “Acceptance Filter Registers”. TABLE 3-2: FILTER/MASK TRUTH TABLE
3.7.5.1 Data Byte Filtering Message
Accept or
Mask Bit n Filter Bit n Identifier
When receiving standard data frames (11-bit identifier), Reject Bit n
Bit
the MCP25625 automatically applies 16 bits of masks
and filters, normally associated with Extended 0 x x Accept
Identifiers, to the first 16 bits of the data field (data 1 0 0 Accept
bytes 0 and 1). Figure 3-8 illustrates how masks and 1 0 1 Reject
filters apply to extended and standard data frames.
1 1 0 Reject
Data byte filtering reduces the load on the MCU when
1 1 1 Accept
implementing Higher Layer Protocols (HLPs) that filter
on the first data byte (e.g., DeviceNet™). Note: x = Don’t care.

As shown in the Receive Buffer Block Diagram

(Figure 3-6), acceptance filters, RXF0 and RXF1 (and
filter mask, RXM0), are associated with RXB0. Filters,
RXF2, RXF3, RXF4, RXF5 and RXM1 mask, are
associated with RXB1.

FIGURE 3-8: MASKS AND FILTERS APPLIED TO CAN FRAMES

Extended Frame

ID10 ID0 EID17 EID0

Masks and Filters Apply to the Entire 29-Bit ID Field

Standard Data Frame

ID10 ID0 * Data Byte 0 Data Byte 1

11-Bit ID Standard Frame 16-Bit Data Filtering*

* The two MSbs’ (EID17 and EID16) mask and filter bits are not used.

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MCP25625
3.7.5.3 FILHIT Bits If the BUKT bit is clear, there are six codes
corresponding to the six filters. If the BUKT bit is set,
Filter matches on received messages can be deter-
there are six codes corresponding to the six filters, plus
mined by the FILHIT[2:0] bits in the associated
two additional codes corresponding to the RXF0 and
RXBxCTRL register. The FILHIT0 bit in the RXB0CTRL
RXF1 filters that roll over into RXB1.
register is associated with Buffer 0 and the FILHIT[2:0]
bits in the RXB1CTRL register are associated with
3.7.5.4 Multiple Filter Matches
Buffer 1.
If more than one acceptance filter matches, the
The three FILHITx bits for Receive Buffer 1 (RXB1) are
FILHITx bits will encode the binary value of the lowest
coded as follows:
numbered filter that matched. For example, if filters,
• 101 = Acceptance Filter 5 (RXF5) RXF2 and RXF4, match, FILHITx will be loaded with
• 100 = Acceptance Filter 4 (RXF4) the value for RXF2. This essentially prioritizes the
• 011 = Acceptance Filter 3 (RXF3) acceptance filters with a lower numbered filter having
higher priority. Messages are compared to filters in
• 010 = Acceptance Filter 2 (RXF2)
ascending order of filter number. This also ensures that
• 001 = Acceptance Filter 1 (RXF1) the message will only be received into one buffer. This
• 000 = Acceptance Filter 0 (RXF0) implies that RXB0 has a higher priority than RXB1.

Note: ‘000’ and ‘001’ can only occur if the BUKT 3.7.5.5 Configuring the Masks and Filters
bit in RXB0CTRL is set, allowing RXB0
The Mask and Filter registers can only be modified
messages to roll over into RXB1.
when the MCP25625 is in Configuration mode (see
RXB0CTRL contains two copies of the BUKT bit Section 2.0 “Modes of Operation”).
(BUKT1) and the FILHIT[0] bit.
The coding of the BUKT bit enables these three bits to Note: The Mask and Filter registers read all ‘0’s
be used similarly to the FILHITx bits in the RXB1CTRL when in any mode except Configuration
register and to distinguish a hit on filters, RXF0 and mode.
RXF1, in either RXB0 or after a rollover into RXB1.
• 111 = Acceptance Filter 1 (RXB1)
• 110 = Acceptance Filter 0 (RXB0)
• 001 = Acceptance Filter 1 (RXB1)
• 000 = Acceptance Filter 0 (RXB0)

FIGURE 3-9: MESSAGE ACCEPTANCE MASK AND FILTER OPERATION

Acceptance Filter Register Acceptance Mask Register

RXFx0 RXMx0

RXMx1 RxRqst
RXFx1

RXMxi
RXFxi

Message Assembly Buffer

Identifier

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 MCP25625
3.8 CAN Bit Time Figure 3-10 illustrates how the Nominal Bit Time is
made up of four segments:
The Nominal Bit Rate (NBR) is the number of bits per
second transmitted on the CAN bus (see Equation 3-1). • Synchronization Segment (SYNC) –
Synchronizes the different nodes connected on
the CAN bus. A bit edge is expected to be within
EQUATION 3-1: NOMINAL BIT RATE/TIME
this segment. Based on the CAN protocol, the
1 Synchronization Segment is 1 TQ. See
NBR = -----------
NBT Section 3.8.3 “Synchronization” for more
details on synchronization.
The Nominal Bit Time (NBT) is made up of four • Propagation Segment (PRSEG) – Compensates
non-overlapping segments. Each of these segments is for the propagation delay on the bus. It is
made up of an integer number of so called Time programmable from 1 to 8 TQ.
Quanta (TQ). • Phase Segment 1 (PHSEG1) – This time
The length of each Time Quantum is based on the segment compensates for errors that may occur
oscillator period (TOSC). Equation 3-2 illustrates how due to phase shifts in the edges. The time
the Time Quantum can be programmed using the Baud segment may be automatically lengthened during
Rate Prescaler (BRP): resynchronization to compensate for the phase
shift. It is programmable from 1 to 8 TQ.
EQUATION 3-2: TIME QUANTA • Phase Segment 2 (PHSEG2) – This time
segment compensates for errors that may occur
due to phase shifts in the edges. The time
TQ = 2  (BRP<5:0> + 1)  TOSC = 2  (BRP<5:0> + 1) segment may be automatically shortened during
FOSC
resynchronization to compensate for the phase
shift. It is programmable from 2 to 8 TQ.
The total number of Time Quanta in a Nominal Bit Time
is programmable and can be calculated using
Equation 3-3.

EQUATION 3-3: TQ PER NBT

NBT
= SYNC + PRSEG + PHSEG1 + PHSEG2
TQ

FIGURE 3-10: ELEMENTS OF A NOMINAL BIT TIME

TOSC

TBRPCLK

SYNC PRSEG PHSEG1 PHSEG2

NBT (1 TQ) (1-8 TQ) (1-8 TQ) (2-8 TQ)

TQ
Sample Point

Nominal Bit Time

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MCP25625
3.8.1 SAMPLE POINT For a more detailed description of the CAN synchroni-
zation, please refer to AN754, “Understanding
The sample point is the point in the Nominal Bit Time at
Microchip’s CAN Module Bit Timing” (DS00754) and
which the logic level is read and interpreted. The CAN
ISO11898-1.
bus can be sampled once or three times, as configured
by the SAM bit in the CNF2 register:
3.8.4 SYNCHRONIZATION JUMP WIDTH
• SAM = 0: The sample point is located between
The Synchronization Jump Width (SJW) is the maxi-
PHSEG1 and PHSEG2.
mum amount PHSEG1 and PHSEG2 can be adjusted
• SAM = 1: One sample point is located between during resynchronization. SJW is programmable from
PHSEG1 and PHSEG2. Additionally, two samples 1 to 4 TQ.
are taken at one-half TQ intervals prior to the end
of PHSEG1, with the value of the bit being 3.8.5 OSCILLATOR TOLERANCE
determined by a majority decision.
According to the CAN specification, the bit timing
The sample point in percent can be calculated using requirements allow ceramic resonators to be used in
Equation 3-4. applications with transmission rates of up to 125 kbps,
as a rule of thumb. For the full bus speed range of the
EQUATION 3-4: SAMPLE POINT CAN protocol, a quartz oscillator is required. A
maximum node-to-node oscillator variation of 1.58% is
PRSEG + PHSEG1
SP =  100 allowed.
NBT
The oscillator tolerance (df), around the nominal
TQ
frequency of the oscillator (fnom), is defined in
Equation 3-5.
3.8.2 INFORMATION PROCESSING TIME Equation 3-6 and Equation 3-7 describe the conditions
The Information Processing Time (IPT) is the time for the maximum tolerance of the oscillator.
required for the CAN controller to determine the bit
level of a sampled bit. The IPT for the MCP25625 is EQUATION 3-5: OSCILLATOR TOLERANCE
2 TQ. Therefore, the minimum of PHSEG2 is also 2 TQ.  1 – df    fnom  F OSC   1 + df   fnom 
3.8.3 SYNCHRONIZATION
To compensate for phase shifts between the oscillator EQUATION 3-6: CONDITION 1
frequencies of the nodes on the bus, each CAN controller SJW
must be able to synchronize to the relevant edge of the df 
NBT
incoming signal. 2  10 
TQ
The CAN controller expects an edge in the received
signal to occur within the SYNC segment. Only EQUATION 3-7: CONDITION 2
Recessive-to-Dominant edges are used for
synchronization. min(PHSEG1, PHSEG2)
df 
There are two mechanisms used for synchronization: 2  13  NBT – PHSEG2
 TQ 
• Hard Synchronization – Forces the edge that
has occurred to lie within the SYNC segment. The
bit time counter is restarted with SYNC.
• Resynchronization – If the edge falls outside the
SYNC segment, PHSEG1 and PHSEG2 will be
adjusted.

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 MCP25625
3.8.6 PROPAGATION DELAY Equation 3-8 describes the maximum propagation
delay; where tTXD – RXD is the propagation delay of the
Figure 3-11 illustrates the propagation delay between
transceiver, 235 ns for the MCP25625; TBUS is the
two CAN nodes on the bus. Assuming Node A is
delay on the CAN bus, approximately 5 ns/m. The
transmitting a CAN message, the transmitted bit will
factor two comes from the worst case, when Node B
propagate from the transmitting CAN Node A,
starts transmitting exactly when the bit from Node A
through the transmitting CAN transceiver, over the
arrives.
CAN bus, through the receiving CAN transceiver into
the receiving CAN Node B.
EQUATION 3-8: MAXIMUM PROPAGATION
During the arbitration phase of a CAN message, the DELAY
transmitter samples the bus and checks if the transmit-
ted bit matches the received bit. The transmitting node T PROP = 2   t TXD – RXD + T BUS 
has to place the sample point after the maximum
propagation delay.

FIGURE 3-11: PROPAGATION DELAY

Delay: Node A to B (TPROPAB)

TxCAN CANH CANH RxCAN

Node A Node B
RxCAN CANL CANL TxCAN
CAN Bus (TBUS)
Transceiver Propagation Transceiver Propagation
Delay (tTXD – RXD) Delay (tTXD – RXD)

Delay: Node B to A (TPROPBA)

TPROP = TPROPAB + TPROPBA = 2  (tTXD – RXD + TBUS)

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MCP25625
3.8.7 BIT TIME CONFIGURATION Table 3-3 illustrates how the bit time parameters are
EXAMPLE calculated. Since the parameters depend on multiple
constraints and equations, and are calculated using an
The following example illustrates the configuration of
iterative process, it is recommended to enter the
the CAN Bit Time registers. Assuming we want to set
equations into a spread sheet.
up a CAN network in an automobile with the following
parameters: A detailed description of the Bit Time Configuration
registers can be found in Section 4.4 “Bit Time
• 500 kbps Nominal Bit Rate (NBR)
Configuration Registers”.
• Sample point between 60 and 80% of the Nominal
Bit Time (NBT)
• 40 meters minimum bus length

TABLE 3-3: STEP-BY-STEP REGISTER CONFIGURATION EXAMPLE

Parameter Register Constraint Value Unit Equations and Comments
NBT — NBT  1 µs 2 µs Equation 3-1
FOSC — FOSC  25 MHz 16 MHz Select crystal or resonator frequency;
usually 16 or 20 MHz work
TQ/Bit — 5 to 25 16 The sum of the TQ of all four segments must
be between 5 and 25; selecting 16 TQ per
bit is a good starting point
TQ — NBT, FOSC 125 ns Equation 3-3
BRP[5:0] CNF1 0 to 63 0 Equation 3-2
SYNC — Fixed 1 TQ Defined in ISO 11898-1
PRSEG CNF2 1 to 8 TQ; 7 TQ Equation 3-8: TPROP = 870 ns,
PRSEG > TPROP minimum PRSEG = TPROP/TQ = 6.96 TQ;
selecting 7 will allow 40m bus length
PHSEG1 CNF2 1 to 8 TQ; 4 TQ There are 8 TQ remaining for
PHSEG1  SJW[1:0] PHSEG1 + PHSEG2; divide the remaining
TQ in half to maximize SJW[1:0]
PHSEG2 CNF3 2 to 8 TQ; 4 TQ There are 4 TQ remaining
PHSEG2  SJW[1:0]
SJW[1:0] CNF1 1 to 4 TQ; 4 TQ Maximizing SJW[1:0] lessens the
SJW[1:0]  min(PHSEG1, requirement for the oscillator tolerance
PHSEG2)
Sample Point — Usually between 60 and 80% 69 % Use Equation 3-4 to double check the
sample point
Oscillator Tolerance — Double Check 1.25 % Equation 3-6
Condition 1
Oscillator Tolerance — Double Check 0.98 % Equation 3-7; better than 1% crystal
Condition 2 oscillator required

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 MCP25625
3.9 Error Detection 3.9.6 ERROR STATES
The CAN protocol provides sophisticated error Detected errors are made known to all other nodes via
detection mechanisms. The following errors can be error frames. The transmission of the erroneous mes-
detected. sage is aborted and the frame is repeated as soon as
possible. Furthermore, each CAN node is in one of the
The registers required for error detection are described three error states according to the value of the internal
in Section 4.5 “Error Detection Registers”. error counters:
3.9.1 CRC ERROR • Error-active
With the Cyclic Redundancy Check (CRC), the • Error-passive
transmitter calculates special check bits for the bit • Bus-off (transmitter only)
sequence from the Start-of-Frame until the end of the The error-active state is the usual state where the node
data field. This CRC sequence is transmitted in the can transmit messages and active error frames (made
CRC field. The receiving node also calculates the CRC of Dominant bits) without any restrictions.
sequence using the same formula and performs a com-
In the error-passive state, messages and passive error
parison to the received sequence. If a mismatch is
frames (made of Recessive bits) may be transmitted.
detected, a CRC error has occurred and an error frame
is generated; the message is repeated. The bus-off state makes it temporarily impossible for
the station to participate in the bus communication.
3.9.2 ACKNOWLEDGE ERROR During this state, messages can neither be received
In the Acknowledge field of a message, the transmitter nor transmitted. Only transmitters can go bus-off.
checks if the Acknowledge slot (which has been sent
out as a Recessive bit) contains a Dominant bit. If not,
3.10 Error Modes and Error Counters
no other node has received the frame correctly. An The MCP25625 contains two error counters: the
Acknowledge error has occurred, an error frame is Receive Error Counter (REC) (see Register 4-30) and
generated and the message will have to be repeated. the Transmit Error Counter (TEC) (see Register 4-29).
The values of both counters can be read by the MCU.
3.9.3 FORM ERROR These counters are incremented/decremented in
If a node detects a Dominant bit in one of the four accordance with the CAN bus specification.
segments (including End-of-Frame, inter-frame space, The MCP25625 is error-active if both error counters are
Acknowledge delimiter or CRC delimiter), a form error below the error-passive limit of 128.
has occurred and an error frame is generated. The
message is repeated. The device is error-passive if at least one of the error
counters equals or exceeds 128.
3.9.4 BIT ERROR The device goes to bus-off if the TEC exceeds the bus-
A bit error occurs if a transmitter detects the opposite off limit of 255. The device remains in this state until the
bit level to what it transmitted (i.e., transmitted a bus-off recovery sequence is received. The bus-off
Dominant and detected a Recessive, or transmitted a recovery sequence consists of 128 occurrences of
Recessive and detected a Dominant). 11 consecutive Recessive bits (see Figure 3-12).
Exception: In the case where the transmitter sends a Note: The MCP25625, after going bus-off, will
Recessive bit, and a Dominant bit is detected during recover back to error-active without any
the arbitration field and the Acknowledge slot, no bit intervention by the MCU if the bus
error is generated because normal arbitration is remains Idle for 128 x 11 bit times. If this is
occurring. not desired, the error Interrupt Service
Routine (ISR) should address this.
3.9.5 STUFF ERROR
The current Error mode of the MCP25625 can be read
lf, between the Start-of-Frame and the CRC delimiter,
by the MCU via the EFLG register (see Register 4-31).
six consecutive bits with the same polarity are
detected, the bit-stuffing rule has been violated. A stuff Additionally, there is an error state warning flag bit
error occurs and an error frame is generated; the (EWARN bit in the EFLG register), which is set if at
message is repeated. least one of the error counters equals or exceeds the
error warning limit of 96. EWARN is reset if both error
counters are less than the error warning limit.

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MCP25625
FIGURE 3-12: ERROR MODES STATE DIAGRAM

Reset

REC < 127 or Error-Active

TEC < 127
128 Occurrences of
11 Consecutive
REC > 127 or “Recessive” Bits
TEC > 127

Error-Passive

TEC > 255

Bus-Off

3.11 Interrupts 3.11.1 INTERRUPT CODE BITS

The MCP25625 has eight sources of interrupts. The The source of a pending interrupt is indicated in the
CANINTE register contains the individual interrupt ICOD[2:0] (Interrupt Code) bits in the CANSTAT register,
enable bits for each interrupt source. The CANINTF as indicated in Register 4-35. In the event that multiple
register contains the corresponding interrupt flag bit for interrupts occur, the INT pin will remain low until all inter-
each interrupt source. When an interrupt occurs, the rupts have been reset by the MCU. The ICOD bits will
INT pin is driven low by the MCP25625 and will remain reflect the code for the highest priority interrupt that is
low until the interrupt is cleared by the MCU. An currently pending. Interrupts are internally prioritized,
interrupt can not be cleared if the respective condition such that the lower the ICODx value, the higher the
still prevails. interrupt priority. Once the highest priority interrupt
condition has been cleared, the code for the next highest
It is recommended that the BIT MODIFY command be priority interrupt that is pending (if any) will be reflected
used to reset the flag bits in the CANINTF register, by the ICODx bits (see Table 3-4). Only those interrupt
rather than normal write operations. This is done to sources that have their associated CANINTE enable bit
prevent unintentionally changing a flag that changes set will be reflected in the ICODx bits.
during the WRITE command, potentially causing an
interrupt to be missed.
TABLE 3-4: ICOD[2:0] DECODE
It should be noted that the CANINTF flags are
read/write and an interrupt can be generated by the ICOD[2:0] Boolean Expression
microcontroller setting any of these bits, provided the 000 ERR•WAK•TX0•TX1•TX2•RX0•RX1
associated CANINTE bit is also set.
001 ERR
The Interrupt registers are described in Section 4.6
010 ERR•WAK
“Interrupt Registers”.
011 ERR•WAK•TX0
100 ERR•WAK•TX0•TX1
101 ERR•WAK•TX0•TX1•TX2
110 ERR•WAK•TX0•TX1•TX2•RX0
111 ERR•WAK•TX0•TX1•TX2•RX0•RX1
Note: ERR is associated with the ERRIE bit in
the CANINTE register.

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 MCP25625
3.11.2 TRANSMIT INTERRUPT 3.12.2.2 Receiver Warning
When the transmit interrupt is enabled (TXxIE = 1 in the The REC has reached the MCU warning limit of 96.
CANINTE register), an interrupt will be generated on the
INT pin once the associated transmit buffer becomes 3.12.2.3 Transmitter Warning
empty and is ready to be loaded with a new message. The TEC has reached the MCU warning limit of 96.
The TXxIF bit in the CANINTF register will be set to indi-
cate the source of the interrupt. The interrupt is cleared 3.12.2.4 Receiver Error-Passive
by clearing the TXxIF bit.
The REC has exceeded the error-passive limit of 127
3.11.3 RECEIVE INTERRUPT and the device has gone to error-passive state.

When the receive interrupt is enabled (RXxIE = 1 in the 3.12.2.5 Transmitter Error-Passive
CANINTE register), an interrupt will be generated on
The TEC has exceeded the error-passive limit of 127
the INT pin once a message has been successfully
and the device has gone to error-passive state.
received and loaded into the associated receive buffer.
This interrupt is activated immediately after receiving
3.12.2.6 Bus-Off
the EOF field. The RXxIF bit in the CANINTF register
will be set to indicate the source of the interrupt. The The TEC has exceeded 255 and the device has gone
interrupt is cleared by clearing the RXxIF bit. to bus-off state.

3.12 Message Error Interrupt 3.12.3 INTERRUPT ACKNOWLEDGE

Interrupts are directly associated with one or more
When an error occurs during the transmission or
status flags in the CANINTF register. Interrupts are
reception of a message, the message error flag
pending as long as one of the flags is set. Once an
(MERRF bit in the CANINTF register) will be set, and if
interrupt flag is set by the device, the flag can not be
the MERRE bit in the CANINTE register is set, an
reset by the MCU until the interrupt condition is
interrupt will be generated on the INT pin. This is
removed.
intended to be used to facilitate baud rate determination
when used in conjunction with Listen-Only mode.
3.13 Oscillator
3.12.1 BUS ACTIVITY WAKE-UP
The MCP25625 is designed to be operated with a crystal
INTERRUPT or ceramic resonator connected to the OSC1 and OSC2
When the CAN controller is in Sleep mode and the bus pins. The MCP25625 oscillator design requires the use
activity wake-up interrupt is enabled (WAKIE = 1 in the of a parallel cut crystal. Use of a series cut crystal may
CANINTE register), an interrupt will be generated on the give a frequency out of the crystal manufacturer’s
INT pin and the WAKIF bit in the CANINTF register will be specifications. A typical oscillator circuit is shown in
set when activity is detected on the CAN bus. This Figure 3-13. The MCP25625 may also be driven by an
interrupt causes the CAN controller to exit Sleep mode. external clock source connected to the OSC1 pin, as
The interrupt is reset by clearing the WAKIF bit. shown in Figure 3-14 and Figure 3-15.
Note: The CAN controller wakes up into 3.13.1 OSCILLATOR START-UP TIMER
Listen-Only mode.
The MCP25625 utilizes an Oscillator Start-up Timer
(OST) that holds the MCP25625 in Reset to ensure that
3.12.2 ERROR INTERRUPT the oscillator has stabilized before the internal state
When the error interrupt is enabled (ERRIE = 1 in the machine begins to operate. The OST keeps the device
CANINTE register), an interrupt is generated on the in a Reset state for 128 OSC1 clock cycles after the
INT pin if an overflow condition occurs, or if the error occurrence of a Power-on Reset, SPI Reset, after the
state of the transmitter or receiver has changed. The assertion of the RESET pin, and after a wake-up from
Error Flag (EFLG) register will indicate one of the Sleep mode. Note that no SPI protocol operations are
following conditions. to be attempted until after the OST has expired.

3.12.2.1 Receiver Overflow

An overflow condition occurs when the MAB has
assembled a valid receive message (the message meets
the criteria of the acceptance filters) and the receive buf-
fer associated with the filter is not available for loading a
new message. The associated RXxOVR bit in the EFLG
register will be set to indicate the overflow condition. This
bit must be cleared by the microcontroller.

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MCP25625
3.13.2 CLKOUT PIN When Sleep mode is requested, the CAN controller will
drive sixteen additional clock cycles on the CLKOUT
The CLKOUT pin is provided to the system designer for
pin before entering Sleep mode. The Idle state of the
use as the main system clock or as a clock input for other
CLKOUT pin in Sleep mode is low. When the CLKOUT
devices in the system. The CLKOUT has an internal
function is disabled (CLKEN = 0 in the CANCTRL
prescaler, which can divide FOSC by 1, 2, 4 and 8. The
register), the CLKOUT pin is in a high-impedance state.
CLKOUT function is enabled and the prescaler is
selected via the CANCTRL register (see Register 4-34). The CLKOUT function is designed to ensure that
tHCLKOUT and tLCLKOUT timings are preserved when the
Note: The maximum frequency on CLKOUT is CLKOUT pin function is enabled, disabled or the
specified as 25 MHz (see Table 7-5). prescaler value is changed.
The CLKOUT pin will be active upon system Reset and
default to the slowest speed (divide-by-8) so that it can
be used as the MCU clock.

FIGURE 3-13: CRYSTAL/CERAMIC RESONATOR OPERATION

OSC1

C1 To Internal Logic

XTAL Sleep
RF(2)

RS(1)
C2 OSC2

Note 1: A Series Resistor (RS) may be required for AT strip-cut crystals.

2: The Feedback Resistor (RF ) is typically in the range of 2 to 10 M.

FIGURE 3-14: EXTERNAL CLOCK SOURCE

Clock from
OSC1
External System

Open(1) OSC2

Note 1: A resistor to ground may be used to reduce system noise. This may increase system current.
2: Duty cycle restrictions must be observed (see Table 7-2).

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 MCP25625
FIGURE 3-15: EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT(1)

330 k 330 k To Other

Devices
74AS04 74AS04 74AS04 MCP25625

OSC1
0.1 mF

XTAL

Note 1: Duty cycle restrictions must be observed (see Table 7-2).

TABLE 3-5: CAPACITOR SELECTION FOR TABLE 3-6: CAPACITOR SELECTION FOR
CERAMIC RESONATORS CRYSTAL OSCILLATOR
Typical Capacitor Values Used: Typical Capacitor
Osc Crystal Values Tested:
Mode Freq. OSC1 OSC2 Type(1)(4) Freq.(2)
C1 C2
HS 8.0 MHz 27 pF 27 pF
HS 4 MHz 27 pF 27 pF
16.0 MHz 22 pF 22 pF
8 MHz 22 pF 22 pF
Capacitor values are for design guidance only:
20 MHz 15 pF 15 pF
These capacitors were tested with the resonators
Capacitor values are for design guidance only:
listed below for basic start-up and operation. These
values are not optimized. These capacitors were tested with the crystals listed
below for basic start-up and operation. These values
Different capacitor values may be required to produce
are not optimized.
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected Different capacitor values may be required to produce
VDD and temperature range for the application. acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
See the notes following Table 3-6 for additional VDD and temperature range for the application.
information.
See the notes following this table for additional
Resonators Used: information.
4.0 MHz Crystals Used(3):
8.0 MHz 4.0 MHz
16.0 MHz 8.0 MHz
20.0 MHz

Note 1: While higher capacitance increases the

stability of the oscillator, it also increases
the start-up time.
2: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for
appropriate values of external components.
3: RS may be required to avoid overdriving
crystals with low drive level specification.
4: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.

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MCP25625
3.14 Reset their default state. A hardware Reset can be achieved
automatically by placing an RC on the RESET pin (see
The MCP25625 differentiates between two Resets: Figure 3-16). The values must be such that the device
1. Hardware Reset – Low on RESET pin is held in Reset for a minimum of 2 µs after VDD
2. SPI Reset – Reset via SPI command (see reaches the operating voltage, as indicated in the
Section 5.1 “RESET Instruction”) electrical specification (tRL).

Both of these Resets are functionally equivalent. It is

important to provide one of these two Resets after
power-up to ensure that the logic and registers are in

FIGURE 3-16: RESET PIN CONFIGURATION EXAMPLE

VDD VDD

D(1) R
R1(2)
RESET
C

Note 1: The diode, D, helps discharge the capacitor quickly when VDD powers down.
2: R1 = 1 k to 10 k will limit any current flowing into RESET from external capacitor, C, in the event
of RESET pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS).

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 MCP25625
4.0 REGISTER MAP reading and writing of data. Some specific control and
status registers allow individual bit modification using
The register map for the MCP25625 is shown in the SPI BIT MODIFY command. The registers that
Table 4-1. Address locations for each register are allow this command are shown as shaded locations in
determined by using the column (higher order four Table 4-1. A summary of the MCP25625 control
bits) and row (lower order four bits) values. The regis- registers is shown in Table 4-2.
ters have been arranged to optimize the sequential

TABLE 4-1: CAN CONTROLLER REGISTER MAP(1)

Lower Higher Order Address Bits
Address
Bits 0000 xxxx 0001 xxxx 0010 xxxx 0011 xxxx 0100 xxxx 0101 xxxx 0110 xxxx 0111 xxxx

0000 RXF0SIDH RXF3SIDH RXM0SIDH TXB0CTRL TXB1CTRL TXB2CTRL RXB0CTRL RXB1CTRL

0001 RXF0SIDL RXF3SIDL RXM0SIDL TXB0SIDH TXB1SIDH TXB2SIDH RXB0SIDH RXB1SIDH
0010 RXF0EID8 RXF3EID8 RXM0EID8 TXB0SIDL TXB1SIDL TXB2SIDL RXB0SIDL RXB1SIDL
0011 RXF0EID0 RXF3EID0 RXM0EID0 TXB0EID8 TXB1EID8 TXB2EID8 RXB0EID8 RXB1EID8
0100 RXF1SIDH RXF4SIDH RXM1SIDH TXB0EID0 TXB1EID0 TXB2EID0 RXB0EID0 RXB1EID0
0101 RXF1SIDL RXF4SIDL RXM1SIDL TXB0DLC TXB1DLC TXB2DLC RXB0DLC RXB1DLC
0110 RXF1EID8 RXF4EID8 RXM1EID8 TXB0D0 TXB1D0 TXB2D0 RXB0D0 RXB1D0
0111 RXF1EID0 RXF4EID0 RXM1EID0 TXB0D1 TXB1D1 TXB2D1 RXB0D1 RXB1D1
1000 RXF2SIDH RXF5SIDH CNF3 TXB0D2 TXB1D2 TXB2D2 RXB0D2 RXB1D2
1001 RXF2SIDL RXF5SIDL CNF2 TXB0D3 TXB1D3 TXB2D3 RXB0D3 RXB1D3
1010 RXF2EID8 RXF5EID8 CNF1 TXB0D4 TXB1D4 TXB2D4 RXB0D4 RXB1D4
1011 RXF2EID0 RXF5EID0 CANINTE TXB0D5 TXB1D5 TXB2D5 RXB0D5 RXB1D5
1100 BFPCTRL TEC CANINTF TXB0D6 TXB1D6 TXB2D6 RXB0D6 RXB1D6
1101 TXRTSCTRL REC EFLG TXB0D7 TXB1D7 TXB2D7 RXB0D7 RXB1D7
1110 CANSTAT CANSTAT CANSTAT CANSTAT CANSTAT CANSTAT CANSTAT CANSTAT
1111 CANCTRL CANCTRL CANCTRL CANCTRL CANCTRL CANCTRL CANCTRL CANCTRL
Note 1: Shaded register locations indicate that these allow the user to manipulate individual bits using the BIT MODIFY command.

TABLE 4-2: CONTROL REGISTER SUMMARY

Register Address POR/RST
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name (Hex) Value

BFPCTRL 0C — — B1BFS B0BFS B1BFE B0BFE B1BFM B0BFM --00 0000

TXRTSCTRL 0D — — B2RTS B1RTS B0RTS B2RTSM B1RTSM B0RTSM --xx x000
CANSTAT xE OPMOD2 OPMOD1 OPMOD0 — ICOD2 ICOD1 ICOD0 — 100- 000-
CANCTRL xF REQOP2 REQOP1 REQOP0 ABAT OSM CLKEN CLKPRE1 CLKPRE0 1000 0111
TEC 1C Transmit Error Counter (TEC) 0000 0000
REC 1D Receive Error Counter (REC) 0000 0000
CNF3 28 SOF WAKFIL — — — PHSEG2[2:0] 00-- -000
CNF2 29 BTLMODE SAM PHSEG1[2:0] PRSEG2 PRSEG1 PRSEG0 0000 0000
CNF1 2A SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 0000 0000
CANINTE 2B MERRE WAKIE ERRIE TX2IE TX1IE TX0IE RX1IE RX0IE 0000 0000
CANINTF 2C MERRF WAKIF ERRIF TX2IF TX1IF TX0IF RX1IF RX0IF 0000 0000
EFLG 2D RX1OVR RX0OVR TXBO TXEP RXEP TXWAR RXWAR EWARN 0000 0000
TXB0CTRL 30 — ABTF MLOA TXERR TXREQ — TXP1 TXP0 -000 0-00
TXB1CTRL 40 — ABTF MLOA TXERR TXREQ — TXP1 TXP0 -000 0-00
TXB2CTRL 50 — ABTF MLOA TXERR TXREQ — TXP1 TXP0 -000 0-00
RXB0CTRL 60 — RXM1 RXM0 — RXRTR BUKT BUKT1 FILHIT0 -00- 0000
RXB1CTRL 70 — RXM1 RXM0 — RXRTR FILHIT2 FILHIT1 FILHIT0 -00- 0000

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MCP25625
4.1 Message Transmit Registers

REGISTER 4-1: TXBxCTRL: TRANSMIT BUFFER x CONTROL REGISTER

(ADDRESS: 30h, 40h, 50h)
U-0 R-0 R-0 R-0 R/W-0 U-0 R/W-0 R/W-0
— ABTF MLOA TXERR TXREQ — TXP1 TXP0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6 ABTF: Message Aborted Flag bit
1 = Message was aborted
0 = Message completed transmission successfully
bit 5 MLOA: Message Lost Arbitration bit
1 = Message lost arbitration while being sent
0 = Message did not lose arbitration while being sent
bit 4 TXERR: Transmission Error Detected bit
1 = A bus error occurred while the message was being transmitted
0 = No bus error occurred while the message was being transmitted
bit 3 TXREQ: Message Transmit Request bit
1 = Buffer is currently pending transmission (MCU sets this bit to request message be transmitted –
bit is automatically cleared when the message is sent)
0 = Buffer is not currently pending transmission (MCU can clear this bit to request a message abort)
bit 2 Unimplemented: Read as ‘0’
bit 1-0 TXP[1:0]: Transmit Buffer Priority bits
11 = Highest message priority
10 = High intermediate message priority
01 = Low intermediate message priority
00 = Lowest message priority

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 MCP25625
REGISTER 4-2: TXRTSCTRL: TxnRTS PIN CONTROL AND STATUS REGISTER (ADDRESS: 0Dh)
U-0 U-0 R-x R-x R-x R/W-0 R/W-0 R/W-0
— — B2RTS B1RTS B0RTS B2RTSM B1RTSM B0RTSM
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5 B2RTS: Tx2RTS Pin State bit
- Reads state of Tx2RTS pin when in Digital Input mode
- Reads as ‘0’ when pin is in ‘Request-to-Send’ mode
bit 4 B1RTS: Tx1RTX Pin State bit
- Reads state of Tx1RTS pin when in Digital Input mode
- Reads as ‘0’ when pin is in ‘Request-to-Send’ mode
bit 3 B0RTS: Tx0RTS Pin State bit
- Reads state of Tx0RTS pin when in Digital Input mode
- Reads as ‘0’ when pin is in ‘Request-to-Send’ mode
bit 2 B2RTSM: Tx2RTS Pin mode bit
1 = Pin is used to request message transmission of TXB2 buffer (on falling edge)
0 = Digital input
bit 1 B1RTSM: Tx1RTS Pin mode bit
1 = Pin is used to request message transmission of TXB1 buffer (on falling edge)
0 = Digital input
bit 0 B0RTSM: Tx0RTS Pin mode bit
1 = Pin is used to request message transmission of TXB0 buffer (on falling edge)
0 = Digital input

REGISTER 4-3: TXBxSIDH: TRANSMIT BUFFER x STANDARD IDENTIFIER HIGH REGISTER

(ADDRESS: 31h, 41h, 51h)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
SID[10:3]
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 SID[10:3]: Standard Identifier bits

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MCP25625
REGISTER 4-4: TXBxSIDL: TRANSMIT BUFFER x STANDARD IDENTIFIER LOW REGISTER
(ADDRESS: 32h, 42h, 52h)
R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x
SID2 SID1 SID0 — EXIDE — EID17 EID16
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 SID[2:0]: Standard Identifier bits

bit 4 Unimplemented: Read as ‘0’
bit 3 EXIDE: Extended Identifier Enable bit
1 = Message will transmit the Extended Identifier
0 = Message will transmit the Standard Identifier
bit 2 Unimplemented: Read as ‘0’
bit 1-0 EID[17:16]: Extended Identifier bits

REGISTER 4-5: TXBxEID8: TRANSMIT BUFFER x EXTENDED IDENTIFIER HIGH REGISTER

(ADDRESS: 33h, 43h, 53h)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
EID[15:8]
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 EID[15:8]: Extended Identifier bits

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 MCP25625
REGISTER 4-6: TXBxEID0: TRANSMIT BUFFER x EXTENDED IDENTIFIER LOW REGISTER
(ADDRESS: 34h, 44h, 54h)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
EID[7:0]
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 EID[7:0]: Extended Identifier bits

REGISTER 4-7: TXBxDLC: TRANSMIT BUFFER x DATA LENGTH CODE REGISTER

(ADDRESS: 35h, 45h, 55h)
U-0 R/W-x U-0 U-0 R/W-x R/W-x R/W-x R/W-x
— RTR — — DLC3(1) DLC2(1) DLC1(1) DLC0(1)
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6 RTR: Remote Transmission Request bit
1 = Transmitted message will be a Remote Transmit Request
0 = Transmitted message will be a data frame
bit 5-4 Unimplemented: Read as ‘0’
bit 3-0 DLC[3:0]: Data Length Code bits(1)
Sets the number of data bytes to be transmitted (0 to 8 bytes).

Note 1: It is possible to set the DLC[3:0] bits to a value greater than eight; however, only eight bytes are transmitted.

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MCP25625
REGISTER 4-8: TXBxDn: TRANSMIT BUFFER x DATA BYTE n REGISTER
(ADDRESS: 36h-3Dh, 46h-4Dh, 56h-5Dh)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
TXBxDn[7:0]
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 TXBxDn[7:0]: Transmit Buffer x Data Field Bytes n bits

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 MCP25625
4.2 Message Receive Registers

REGISTER 4-9: RXB0CTRL: RECEIVE BUFFER 0 CONTROL REGISTER (ADDRESS: 60h)

U-0 R/W-0 R/W-0 U-0 R-0 R/W-0 R-0 R-0
— RXM1 RXM0 — RXRTR BUKT BUKT1 FILHIT0(1)
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6-5 RXM[1:0]: Receive Buffer Operating mode bits
11 = Turns mask/filters off; receives any message
10 = Reserved
01 = Reserved
00 = Receives all valid messages using either Standard or Extended Identifiers that meet filter criteria;
Extended ID Filter registers, RXFxEID8 and RXFxEID0, are applied to the first two bytes of data in
the messages with standard IDs.
bit 4 Unimplemented: Read as ‘0’
bit 3 RXRTR: Received Remote Transfer Request bit
1 = Remote Transfer Request received
0 = No Remote Transfer Request received
bit 2 BUKT: Rollover Enable bit
1 = RXB0 message will roll over and be written to RXB1 if RXB0 is full
0 = Rollover is disabled
bit 1 BUKT1: Read-Only Copy of BUKT bit (used internally by the MCP25625)
bit 0 FILHIT0: Filter Hit bit(1)
Indicates which acceptance filter enabled the reception of a message.
1 = Acceptance Filter 1 (RXF1)
0 = Acceptance Filter 0 (RXF0)

Note 1: If a rollover from RXB0 to RXB1 occurs, the FILHIT0 bit will reflect the filter that accepted the message
that rolled over.

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MCP25625
REGISTER 4-10: RXB1CTRL: RECEIVE BUFFER 1 CONTROL REGISTER (ADDRESS: 70h)
U-0 R/W-0 R/W-0 U-0 R-0 R-0 R-0 R-0
— RXM1 RXM0 — RXRTR FILHIT2 FILHIT1 FILHIT0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6-5 RXM[1:0]: Receive Buffer Operating mode bits
11 = Turns mask/filters off; receives any message
10 = Reserved
01 = Reserved
00 = Receives all valid messages using either Standard or Extended Identifiers that meet filter criteria
bit 4 Unimplemented: Read as ‘0’
bit 3 RXRTR: Received Remote Transfer Request bit
1 = Remote Transfer Request received
0 = No Remote Transfer Request received
bit 2-0 FILHIT[2:0]: Filter Hit bits
Indicates which acceptance filter enabled the reception of a message.
101 = Acceptance Filter 5 (RXF5)
100 = Acceptance Filter 4 (RXF4)
011 = Acceptance Filter 3 (RXF3)
010 = Acceptance Filter 2 (RXF2)
001 = Acceptance Filter 1 (RXF1) (only if the BUKT bit is set in RXB0CTRL)
000 = Acceptance Filter 0 (RXF0) (only if the BUKT bit is set in RXB0CTRL)

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 MCP25625
REGISTER 4-11: BFPCTRL: RxnBF PIN CONTROL AND STATUS REGISTER (ADDRESS: 0Ch)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — B1BFS B0BFS B1BFE B0BFE B1BFM B0BFM
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5 B1BFS: Rx1BF Pin State bit (Digital Output mode only)
- Reads as ‘0’ when Rx1BF is configured as an interrupt pin
bit 4 B0BFS: Rx0BF Pin State bit (Digital Output mode only)
- Reads as ‘0’ when Rx0BF is configured as an interrupt pin
bit 3 B1BFE: Rx1BF Pin Function Enable bit
1 = Pin function is enabled, operation mode is determined by the B1BFM bit
0 = Pin function is disabled, pin goes to the high-impedance state
bit 2 B0BFE: Rx0BF Pin Function Enable bit
1 = Pin function is enabled, operation mode is determined by the B0BFM bit
0 = Pin function is disabled, pin goes to the high-impedance state
bit 1 B1BFM: Rx1BF Pin Operation mode bit
1 = Pin is used as an interrupt when a valid message is loaded into RXB1
0 = Digital Output mode
bit 0 B0BFM: Rx0BF Pin Operation mode bit
1 = Pin is used as an interrupt when a valid message is loaded into RXB0
0 = Digital Output mode

 2014-2019 Microchip Technology Inc. DS20005282C-page 39

MCP25625
REGISTER 4-12: RXBxSIDH: RECEIVE BUFFER x STANDARD IDENTIFIER HIGH REGISTER
(ADDRESS: 61h, 71h)
R-x R-x R-x R-x R-x R-x R-x R-x
SID[10:3]
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 SID[10:3]: Standard Identifier bits

These bits contain the eight Most Significant bits of the Standard Identifier for the received message.

REGISTER 4-13: RXBxSIDL: RECEIVE BUFFER x STANDARD IDENTIFIER LOW REGISTER

(ADDRESS: 62h, 72h)
R-x R-x R-x R-x R-x U-0 R-x R-x
SID2 SID1 SID0 SRR IDE — EID17 EID16
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 SID[2:0]: Standard Identifier bits

These bits contain the three Least Significant bits of the Standard Identifier for the received message.
bit 4 SRR: Standard Frame Remote Transmit Request bit (valid only if the IDE bit = 0)
1 = Standard frame Remote Transmit Request received
0 = Standard data frame received
bit 3 IDE: Extended Identifier Flag bit
This bit indicates whether the received message was a standard or an extended frame.
1 = Received message was an extended frame
0 = Received message was a standard frame
bit 2 Unimplemented: Read as ‘0’
bit 1-0 EID[17:16]: Extended Identifier bits
These bits contain the two Most Significant bits of the Extended Identifier for the received message.

DS20005282C-page 40  2014-2019 Microchip Technology Inc.

 MCP25625
REGISTER 4-14: RXBxEID8: RECEIVE BUFFER x EXTENDED IDENTIFIER HIGH REGISTER
(ADDRESS: 63h, 73h)
R-x R-x R-x R-x R-x R-x R-x R-x
EID[15:8]
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 EID[15:8]: Extended Identifier bits

These bits hold bits 15 through 8 of the Extended Identifier for the received message.

REGISTER 4-15: RXBxEID0: RECEIVE BUFFER x EXTENDED IDENTIFIER LOW REGISTER

(ADDRESS: 64h, 74h)
R-x R-x R-x R-x R-x R-x R-x R-x
EID[7:0]
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 EID[7:0]: Extended Identifier bits

These bits hold the Least Significant eight bits of the Extended Identifier for the received message.

 2014-2019 Microchip Technology Inc. DS20005282C-page 41

MCP25625
REGISTER 4-16: RXBxDLC: RECEIVE BUFFER x DATA LENGTH CODE REGISTER
(ADDRESS: 65h, 75h)
U-0 R-x R-x R-x R-x R-x R-x R-x
— RTR RB1 RB0 DLC3 DLC2 DLC1 DLC0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6 RTR: Extended Frame Remote Transmission Request bit
(valid only when the IDE bit in the RXBxSIDL register is ‘1’)
1 = Extended frame Remote Transmit Request received
0 = Extended data frame received
bit 5 RB1: Reserved Bit 1
bit 4 RB0: Reserved Bit 0
bit 3-0 DLC[3:0]: Data Length Code bits
Indicates the number of data bytes that were received.

REGISTER 4-17: RXBxDn: RECEIVE BUFFER x DATA BYTE n REGISTER

(ADDRESS: 66h-6Dh, 76h-7Dh)
R-x R-x R-x R-x R-x R-x R-x R-x
RBxD[7:0]
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 RBxD[7:0]: Receive Buffer x Data Field Bytes n bits

Eight bytes containing the data bytes for the received message.

DS20005282C-page 42  2014-2019 Microchip Technology Inc.

 MCP25625
4.3 Acceptance Filter Registers

REGISTER 4-18: RXFxSIDH: FILTER x STANDARD IDENTIFIER HIGH REGISTER

(ADDRESS: 00h, 04h, 08h, 10h, 14h, 18h)(1)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
SID[10:3]
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 SID[10:3]: Standard Identifier Filter bits

These bits hold the filter bits to be applied to bits[10:3] of the Standard Identifier portion of a received
message.

Note 1: The Mask and Filter registers read all ‘0’s when in any mode, except Configuration mode.

REGISTER 4-19: RXFxSIDL: FILTER x STANDARD IDENTIFIER LOW REGISTER

(ADDRESS: 01h, 05h, 09h, 11h, 15h, 19h)(1)
R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x
SID2 SID1 SID0 — EXIDE — EID17 EID16
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 SID[2:0]: Standard Identifier Filter bits

These bits hold the filter bits to be applied to bits[2:0] of the Standard Identifier portion of a received
message.
bit 4 Unimplemented: Read as ‘0’
bit 3 EXIDE: Extended Identifier Enable bit
1 = Filter is applied only to extended frames
0 = Filter is applied only to standard frames
bit 2 Unimplemented: Read as ‘0’
bit 1-0 EID[17:16]: Extended Identifier Filter bits
These bits hold the filter bits to be applied to bits[17:16] of the Extended Identifier portion of a received
message.

Note 1: The Mask and Filter registers read all ‘0’s when in any mode, except Configuration mode.

 2014-2019 Microchip Technology Inc. DS20005282C-page 43

MCP25625
REGISTER 4-20: RXFxEID8: FILTER x EXTENDED IDENTIFIER HIGH REGISTER
(ADDRESS: 02h, 06h, 0Ah, 12h, 16h, 1Ah)(1)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
EID[15:8]
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 EID[15:8]: Extended Identifier bits

These bits hold the filter bits to be applied to bits[15:8] of the Extended Identifier portion of a received
message or to Byte 0 in received data if corresponding with RXM[1:0] = 00 and EXIDE = 0.

Note 1: The Mask and Filter registers read all ‘0’s when in any mode, except Configuration mode.

REGISTER 4-21: RXFxEID0: FILTER x EXTENDED IDENTIFIER LOW REGISTER

(ADDRESS: 03h, 07h, 0Bh, 13h, 17h, 1Bh)(1)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
EID[7:0]
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 EID[7:0]: Extended Identifier bits

These bits hold the filter bits to be applied to bits[7:0] of the Extended Identifier portion of a received
message or to Byte 1 in received data if corresponding with RXM[1:0] = 00 and EXIDE = 0.

Note 1: The Mask and Filter registers read all ‘0’s when in any mode, except Configuration mode.

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 MCP25625
REGISTER 4-22: RXMxSIDH: MASK x STANDARD IDENTIFIER HIGH REGISTER
(ADDRESS: 20h, 24h)(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SID[10:3]
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 SID[10:3]: Standard Identifier Mask bits

These bits hold the mask bits to be applied to bits[10:3] of the Standard Identifier portion of a received
message.

Note 1: The Mask and Filter registers read all ‘0’s when in any mode, except Configuration mode.

REGISTER 4-23: RXMxSIDL: MASK x STANDARD IDENTIFIER LOW REGISTER

(ADDRESS: 21h, 25h)(1)
R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0
SID2 SID1 SID0 — — — EID17 EID16
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 SID[2:0]: Standard Identifier Mask bits

These bits hold the mask bits to be applied to bits[2:0] of the Standard Identifier portion of a received
message.
bit 4-2 Unimplemented: Read as ‘0’
bit 1-0 EID[17:16]: Extended Identifier Mask bits
These bits hold the mask bits to be applied to bits[17:16] of the Extended Identifier portion of a received
message.

Note 1: The Mask and Filter registers read all ‘0’s when in any mode, except Configuration mode.

 2014-2019 Microchip Technology Inc. DS20005282C-page 45

MCP25625
REGISTER 4-24: RXMxEID8: MASK x EXTENDED IDENTIFIER HIGH REGISTER
(ADDRESS: 22h, 26h)(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
EID[15:8]
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 EID[15:8]: Extended Identifier bits

These bits hold the filter bits to be applied to bits[15:8] of the Extended Identifier portion of a received
message. If corresponding with RXM[1:0] = 00 and EXIDE = 0, these bits are applied to Byte 0 in
received data.

Note 1: The Mask and Filter registers read all ‘0’s when in any mode, except Configuration mode.

REGISTER 4-25: RXMxEID0: MASK x EXTENDED IDENTIFIER LOW REGISTER

(ADDRESS: 23h, 27h)(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
EID[7:0]
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 EID[7:0]: Extended Identifier Mask bits

These bits hold the filter bits to be applied to bits[7:0] of the Extended Identifier portion of a received
message. If corresponding with RXM[1:0] = 00 and EXIDE = 0, these bits are applied to Byte 1 in
received data.

Note 1: The Mask and Filter registers read all ‘0’s when in any mode, except Configuration mode.

DS20005282C-page 46  2014-2019 Microchip Technology Inc.

 MCP25625
4.4 Bit Time Configuration Registers

REGISTER 4-26: CNF1: CONFIGURATION 1 REGISTER (ADDRESS: 2Ah)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 SJW[1:0]: Synchronization Jump Width Length bits

11 = Length = 4 x TQ
10 = Length = 3 x TQ
01 = Length = 2 x TQ
00 = Length = 1 x TQ
bit 5-0 BRP[5:0]: Baud Rate Prescaler bits
TQ = 2 x (BRP[5:0] + 1)/FOSC

REGISTER 4-27: CNF2: CONFIGURATION 2 REGISTER (ADDRESS: 29h)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BTLMODE SAM PHSEG1[2:0] PRSEG2 PRSEG1 PRSEG0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 BTLMODE: PS2 Bit Time Length bit

1 = Length of PS2 is determined by the PHSEG2[2:0] bits of CNF3
0 = Length of PS2 is the greater of PS1 and IPT (2 TQ)
bit 6 SAM: Sample Point Configuration bit
1 = Bus line is sampled three times at the sample point
0 = Bus line is sampled once at the sample point
bit 5-3 PHSEG1[2:0]: PS1 Length bits
(PHSEG1[2:0] + 1) x TQ
bit 2-0 PRSEG[2:0]: Propagation Segment Length bits
(PRSEG[2:0] + 1) x TQ

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MCP25625
REGISTER 4-28: CNF3: CONFIGURATION 3 REGISTER (ADDRESS: 28h)
R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
SOF WAKFIL — — — PHSEG2[2:0]
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SOF: Start-of-Frame Signal bit

If CLKEN (CANCTRL[2]) = 1:
1 = CLKOUT pin is enabled for SOF signal
0 = CLKOUT pin is enabled for clock out function
If CLKEN (CANCTRL[2]) = 0:
Bit is don’t care.
bit 6 WAKFIL: Wake-up Filter bit
1 = Wake-up filter is enabled
0 = Wake-up filter is disabled
bit 5-3 Unimplemented: Read as ‘0’
bit 2-0 PHSEG2[2:0]: PS2 Length bits
(PHSEG2[2:0] + 1) x TQ
Minimum valid setting for PS2 is 2 TQ.

DS20005282C-page 48  2014-2019 Microchip Technology Inc.

 MCP25625
4.5 Error Detection Registers

REGISTER 4-29: TEC: TRANSMIT ERROR COUNTER REGISTER (ADDRESS: 1Ch)

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
TEC[7:0]
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 TEC[7:0]: Transmit Error Count bits

REGISTER 4-30: REC: RECEIVER ERROR COUNTER REGISTER (ADDRESS: 1Dh)

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
REC[7:0]
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 REC[7:0]: Receive Error Count bits

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MCP25625
REGISTER 4-31: EFLG: ERROR FLAG REGISTER (ADDRESS: 2Dh)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
RX1OVR RX0OVR TXBO TXEP RXEP TXWAR RXWAR EWARN
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 RX1OVR: Receive Buffer 1 Overflow Flag bit

- Sets when a valid message is received for RXB1 and the RX1IF bit in the CANINTF register is ‘1’
- Must be reset by MCU
bit 6 RX0OVR: Receive Buffer 0 Overflow Flag bit
- Sets when a valid message is received for RXB0 and the RX0IF bit in the CANINTF register is ‘1’
- Must be reset by MCU
bit 5 TXBO: Bus-Off Error Flag bit
- Bit sets when TEC reaches 255
- Resets after a successful bus recovery sequence
bit 4 TXEP: Transmit Error-Passive Flag bit
- Sets when TEC is equal to or greater than 128
- Resets when TEC is less than 128
bit 3 RXEP: Receive Error-Passive Flag bit
- Sets when REC is equal to or greater than 128
- Resets when REC is less than 128
bit 2 TXWAR: Transmit Error Warning Flag bit
- Sets when TEC is equal to or greater than 96
- Resets when TEC is less than 96
bit 1 RXWAR: Receive Error Warning Flag bit
- Sets when REC is equal to or greater than 96
- Resets when REC is less than 96
bit 0 EWARN: Error Warning Flag bit
- Sets when TEC or REC is equal to or greater than 96 (TXWAR or RXWAR = 1)
- Resets when both REC and TEC are less than 96

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 MCP25625
4.6 Interrupt Registers
.

REGISTER 4-32: CANINTE: CAN INTERRUPT ENABLE REGISTER (ADDRESS: 2Bh)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
MERRE WAKIE ERRIE TX2IE TX1IE TX0IE RX1IE RX0IE
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 MERRE: Message Error Interrupt Enable bit

1 = Interrupt on error during message reception or transmission
0 = Disabled
bit 6 WAKIE: Wake-up Interrupt Enable bit
1 = Interrupt on CAN bus activity
0 = Disabled
bit 5 ERRIE: Error Interrupt Enable bit (multiple sources in the EFLG register)
1 = Interrupt on EFLG error condition change
0 = Disabled
bit 4 TX2IE: Transmit Buffer 2 Empty Interrupt Enable bit
1 = Interrupt on TXB2 becoming empty
0 = Disabled
bit 3 TX1IE: Transmit Buffer 1 Empty Interrupt Enable bit
1 = Interrupt on TXB1 becoming empty
0 = Disabled
bit 2 TX0IE: Transmit Buffer 0 Empty Interrupt Enable bit
1 = Interrupt on TXB0 becoming empty
0 = Disabled
bit 1 RX1IE: Receive Buffer 1 Full Interrupt Enable bit
1 = Interrupt when message is received in RXB1
0 = Disabled
bit 0 RX0IE: Receive Buffer 0 Full Interrupt Enable bit
1 = Interrupt when message is received in RXB0
0 = Disabled

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MCP25625
REGISTER 4-33: CANINTF: CAN INTERRUPT FLAG REGISTER (ADDRESS: 2Ch)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
MERRF WAKIF ERRIF TX2IF TX1IF TX0IF RX1IF RX0IF
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 MERRF: Message Error Interrupt Flag bit

1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)
0 = No interrupt pending
bit 6 WAKIF: Wake-up Interrupt Flag bit
1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)
0 = No interrupt pending
bit 5 ERRIF: Error Interrupt Flag bit (multiple sources in the EFLG register)
1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)
0 = No interrupt pending
bit 4 TX2IF: Transmit Buffer 2 Empty Interrupt Flag bit
1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)
0 = No interrupt pending
bit 3 TX1IF: Transmit Buffer 1 Empty Interrupt Flag bit
1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)
0 = No interrupt pending
bit 2 TX0IF: Transmit Buffer 0 Empty Interrupt Flag bit
1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)
0 = No interrupt pending
bit 1 RX1IF: Receive Buffer 1 Full Interrupt Flag bit
1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)
0 = No interrupt pending
bit 0 RX0IF: Receive Buffer 0 Full Interrupt Flag bit
1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)
0 = No interrupt pending

DS20005282C-page 52  2014-2019 Microchip Technology Inc.

 MCP25625
4.7 CAN Control Register
REGISTER 4-34: CANCTRL: CAN CONTROL REGISTER (ADDRESS: XFh)
R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1
REQOP2 REQOP1 REQOP0 ABAT OSM CLKEN CLKPRE1 CLKPRE0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 REQOP[2:0]: Request Operation mode bits

000 = Sets Normal Operation mode
001 = Sets Sleep mode
010 = Sets Loopback mode
011 = Sets Listen-Only mode
100 = Sets Configuration mode
All other values for the REQOPx bits are invalid and should not be used. On power-up, REQOP = b’100.
bit 4 ABAT: Abort All Pending Transmissions bit
1 = Requests abort of all pending transmit buffers
0 = Terminates request to abort all transmissions
bit 3 OSM: One-Shot Mode bit
1 = Enabled: Message will only attempt to transmit one time
0 = Disabled: Messages will reattempt transmission if required
bit 2 CLKEN: CLKOUT Pin Enable bit
1 = CLKOUT pin is enabled
0 = CLKOUT pin is disabled (pin is in a high-impedance state)
bit 1-0 CLKPRE[1:0]: CLKOUT Pin Prescaler bits
00 = FCLKOUT = System Clock/1
01 = FCLKOUT = System Clock/2
10 = FCLKOUT = System Clock/4
11 = FCLKOUT = System Clock/8

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MCP25625
REGISTER 4-35: CANSTAT: CAN STATUS REGISTER (ADDRESS: XEh)
R-1 R-0 R-0 U-0 R-0 R-0 R-0 U-0
OPMOD2 OPMOD1 OPMOD0 — ICOD2 ICOD1 ICOD0 —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 OPMOD[2:0]: Operation Mode bits

000 = Device is in the Normal Operation mode
001 = Device is in Sleep mode
010 = Device is in Loopback mode
011 = Device is in Listen-Only mode
100 = Device is in Configuration mode
bit 4 Unimplemented: Read as ‘0’
bit 3-1 ICOD[2:0]: Interrupt Flag Code bits
000 = No Interrupt
001 = Error interrupt
010 = Wake-up interrupt
011 = TXB0 interrupt
100 = TXB1 interrupt
101 = TXB2 interrupt
110 = RXB0 interrupt
111 = RXB1 interrupt
bit 0 Unimplemented: Read as ‘0’

DS20005282C-page 54  2014-2019 Microchip Technology Inc.

 MCP25625
5.0 SPI INTERFACE Table 5-1 shows the instruction bytes for all operations.
Refer to Figures 5-10 and 5-11 for detailed input and
The MCP25625 is designed to interface directly with output timing diagrams for both Mode 0,0 and Mode 1,1
the Serial Peripheral Interface (SPI) port available on operation.
many microcontrollers and supports Mode 0,0 and
Mode 1,1. Note 1: The MCP25625 expects the first byte,
Commands and data are sent to the device via the SI after lowering CS, to be the instruction/
pin, with data being clocked in on the rising edge of command byte. This implies that CS must
SCK. Data is driven out by the MCP25625 (on the SO be raised and then lowered again to
line) on the falling edge of SCK. The CS pin must be invoke another command.
held low while any operation is performed.

TABLE 5-1: SPI INSTRUCTION SET

Instruction
Instruction Name Description
Format
RESET 1100 0000 Resets the internal registers to the default state, sets Configuration mode.
READ 0000 0011 Reads data from the register beginning at the selected address.
READ RX BUFFER 1001 0nm0 When reading a receive buffer, reduces the overhead of a normal READ
command by placing the Address Pointer at one of four locations, as
indicated by ‘nm’.(1)
WRITE 0000 0010 Writes data to the register beginning at the selected address.
LOAD TX BUFFER 0100 0abc When loading a transmit buffer, reduces the overhead of a normal WRITE
command by placing the Address Pointer at one of six locations, as
indicated by ‘abc’.
RTS 1000 0nnn Instructs the controller to begin the message transmission sequence for
(Message any of the transmit buffers.
Request-to-Send)
1000 0nnn
Request-to-Send for TXB2 Request-to-Send for TXBO
Request-to-Send for TXB1

READ STATUS 1010 0000 Quick polling command that reads several Status bits for transmit and
receive functions.
RX STATUS 1011 0000 Quick polling command that indicates a filter match and message type
(standard, extended and/or remote) of the received message.
BIT MODIFY 0000 0101 Allows the user to set or clear individual bits in a particular register.(2)
Note 1: The associated RX flag bit (RXxIF bits in the CANINTF register) will be cleared after bringing CS high.
2: Not all registers can be bit modified with this command. Executing this command on registers that are not
bit modifiable will force the mask to FFh. See the register map in Section 4.0 “Register Map” for a list of
the registers that apply.

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MCP25625
5.1 RESET Instruction 5.5 LOAD TX BUFFER Instruction
The RESET instruction can be used to re-initialize the The LOAD TX BUFFER instruction (Figure 5-5) elimi-
internal registers of the MCP25625 and set Configuration nates the 8-bit address required by a normal WRITE
mode. This command provides the same functionality, command. The 8-bit instruction sets the Address
via the SPI interface, as the RESET pin. Pointer to one of six addresses to quickly write to a
The RESET instruction is a single byte instruction that transmit buffer that points to the “ID” or “data” address
requires selecting the device by pulling CS low, of any of the three transmit buffers.
sending the instruction byte and then raising CS. It is
highly recommended that the RESET command be sent 5.6 Request-to-Send (RTS) Instruction
(or the RESET pin be lowered) as part of the power-on
The RTS command can be used to initiate message
initialization sequence.
transmission for one or more of the transmit buffers.
5.2 READ Instruction The MCP25625 is selected by lowering the CS pin. The
RTS command byte is then sent. Shown in Figure 5-6,
The READ instruction is started by lowering the CS pin. the last three bits of this command indicate which
The READ instruction is then sent to the MCP25625, transmit buffer(s) are enabled to send.
followed by the 8-bit address (A7 through A0). Next, the
data stored in the register at the selected address will This command will set the TXREQ bit in the TXBxCTRL
be shifted out on the SO pin. register for the respective buffer(s). Any or all of the last
three bits can be set in a single command. If the RTS
The internal Address Pointer is automatically incremented command is sent with nnn = 000, the command will be
to the next address once each byte of data is shifted out. ignored.
Therefore, it is possible to read the next consecutive
register address by continuing to provide clock pulses.
5.7 READ STATUS Instruction
Any number of consecutive register locations can be read
sequentially using this method. The READ operation is The READ STATUS instruction allows single instruction
terminated by raising the CS pin (Figure 5-2). access to some of the often used Status bits for
message reception and transmission.
5.3 READ RX BUFFER Instruction
The MCP25625 is selected by lowering the CS pin and
The READ RX BUFFER instruction (Figure 5-3) pro- the READ STATUS command byte, shown in Figure 5-8,
vides a means to quickly address a receive buffer for is sent to the MCP25625. Once the command byte is
reading. This instruction reduces the SPI overhead by sent, the MCP25625 will return eight bits of data that
one byte: the address byte. The command byte actually contain the status.
has four possible values that determine the Address If additional clocks are sent after the first eight bits are
Pointer location. Once the command byte is sent, the transmitted, the MCP25625 will continue to output the
controller clocks out the data at the address location Status bits as long as the CS pin is held low and clocks
the same as the READ instruction (i.e., sequential reads are provided on SCK.
are possible). This instruction further reduces the SPI
overhead by automatically clearing the associated Each Status bit returned in this command may also be
receive flag (RXxIF bit in the CANINTF register) when read by using the standard READ command with the
CS is raised at the end of the command. appropriate register address.

5.4 WRITE Instruction 5.8 RX STATUS Instruction

The WRITE instruction is started by lowering the CS The RX STATUS instruction (Figure 5-9) is used to
pin. The WRITE instruction is then sent to the quickly determine which filter matched the message
MCP25625, followed by the address and at least one and message type (standard, extended, remote). After
byte of data. the command byte is sent, the controller will return
eight bits of data that contain the status data. If more
It is possible to write to sequential registers by clocks are sent after the eight bits are transmitted, the
continuing to clock in data bytes, as long as CS is held controller will continue to output the same Status bits as
low. Data will actually be written to the register on the long as the CS pin stays low and clocks are provided.
rising edge of the SCK line for the D0 bit. If the CS line
is brought high before eight bits are loaded, the write
will be aborted for that data byte and previous bytes in
the command will have been written. Refer to the timing
diagram in Figure 5-4 for a more detailed illustration of
the byte WRITE sequence.

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 MCP25625
5.9 BIT MODIFY Instruction The data byte determines what value the modified bits
in the register will be changed to. A ‘1’ in the data byte
The BIT MODIFY instruction provides a means for will set the bit and a ‘0’ will clear the bit, provided that
setting or clearing individual bits in specific status and the mask for that bit is set to a ‘1’ (see Figure 5-7).
control registers. This command is not available for all
registers. See Section 4.0 “Register Map” to FIGURE 5-1: BIT MODIFY
determine which registers allow the use of this command.
Mask Byte 0 0 1 1 0 1 0 1
Note: Executing the BIT MODIFY command on
registers that are not bit-modifiable will
force the mask to FFh. This will allow byte
writes to the registers, not BIT MODIFY. Data Byte x x 1 0 x 0 x 1

The part is selected by lowering the CS pin and the BIT

Previous
MODIFY command byte is then sent to the MCP25625. Register 0 1 0 1 0 0 0 1
The command is followed by the address of the Contents
register, the mask byte, and finally, the data byte.
The mask byte determines which bits in the register will Resulting
Register 0 1 1 0 0 0 0 1
be allowed to change. A ‘1’ in the mask byte will allow Contents
a bit in the register to change, while a ‘0’ will not (see
Figure 5-1).

FIGURE 5-2: READ INSTRUCTION

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK

Instruction Address Byte

SI 0 0 0 0 0 0 1 1 A7 6 5 4 3 2 1 A0 Don’t Care

Data Out
High-Impedance
SO 7 6 5 4 3 2 1 0

FIGURE 5-3: READ RX BUFFER INSTRUCTION

CS
n m Address Points to Address
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 Receive Buffer 0, 0x61
SCK Start at RXB0SIDH
0 1 Receive Buffer 0, 0x66
Instruction Start at RXB0D0
SI 1 0 0 1 0 n m 0 Don’t Care 1 0 Receive Buffer 1, 0x71
Start at RXB1SIDH
Data Out 1 1 Receive Buffer 1, 0x76
High-Impedance Start at RXB1D0
SO 7 6 5 4 3 2 1 0

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MCP25625
FIGURE 5-4: BYTE WRITE INSTRUCTION

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK

Instruction Address Byte Data Byte

SI 0 0 0 0 0 0 1 0 A7 6 5 4 3 2 1 A0 7 6 5 4 3 2 1 0

High-Impedance
SO

FIGURE 5-5: LOAD TX BUFFER INSTRUCTION

a b c Address Points to Addr

CS 0 0 0 TX Buffer 0, Start at 0x31
TXB0SIDH
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 1 TX Buffer 0, Start at 0x36
SCK TXB0D0
0 1 0 TX Buffer 1, Start at 0x41
Instruction Data In TXB1SIDH

SI 0 1 0 0 0 a b c 7 6 5 4 3 2 1 0 0 1 1 TX Buffer 1, Start at 0x46

TXB1D0
1 0 0 TX Buffer 2, Start at 0x51
High-Impedance TXB2SIDH
SO
1 0 1 TX Buffer 2, Start at 0x56
TXB2D0

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 MCP25625
FIGURE 5-6: REQUEST-TO-SEND (RTS) INSTRUCTION

CS

0 1 2 3 4 5 6 7
SCK

Instruction

SI 1 0 0 0 0 T2 T1 T0

High-Impedance
SO

FIGURE 5-7: BIT MODIFY INSTRUCTION

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCK

Instruction Address Byte Mask Byte Data Byte

SI 0 0 0 0 0 1 0 1 A7 6 5 4 3 2 1 A0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

High-Impedance
SO

Note: Not all registers can be accessed with this command. See the register map for a list of the registers that apply.

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MCP25625
FIGURE 5-8: READ STATUS INSTRUCTION

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK

Instruction
SI 1 0 1 0 0 0 0 0 Don’t Care

Repeat
Data Out Data Out
High-Impedance
SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

RX0IF (CANINTF Register)

RX1IF (CANINTF Register)
TXREQ (TXB0CTRL Register)
TX0IF (CANINTF Register)
TXREQ (TXB1CTRL Register)
TX1IF (CANINTF Register)
TXREQ (TXB2CTRL Register)
TX2IF (CANINTF Register)

FIGURE 5-9: RX STATUS INSTRUCTION

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK

Instruction

SI 1 0 1 1 0 0 0 0 Don’t Care

Repeat
Data Out Data Out
High-Impedance
SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

7 6 Received Message 4 3 Msg Type Received 2 1 0 Filter Match

0 0 No RX Message 0 0 Standard Data Frame 0 0 0 RXF0

0 1 Message in RXB0 0 1 Standard Remote Frame 0 0 1 RXF1
1 0 Message in RXB1 1 0 Extended Data Frame 0 1 0 RXF2
1 1 Messages in Both Buffers* 1 1 Extended Remote Frame 0 1 1 RXF3
RXxIF (CANINTF) bits are mapped to The extended ID bit is mapped to 1 0 0 RXF4
bits 7 and 6. bit 4. The RTR bit is mapped to bit 3. 1 0 1 RXF5
1 1 0 RXF0 (rollover to RXB1)
1 1 1 RXF1 (rollover to RXB1)

* Buffer 0 has higher priority; therefore, RXB0 status is reflected in bits[4:0].

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 MCP25625
FIGURE 5-10: SPI INPUT TIMING

CS
11
1 6 10
Mode 1,1 7 2
SCK Mode 0,0

4 5

SI MSB In LSB In

High-Impedance
SO

FIGURE 5-11: SPI OUTPUT TIMING

CS

2
8 9
Mode 1,1
SCK Mode 0,0

12
14
13

SO MSB Out LSB Out

Don’t Care
SI

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MCP25625
NOTES:

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 MCP25625
6.0 CAN TRANSCEIVER The CAN transceiver meets the stringent automotive
EMC and ESD requirements.
The CAN transceiver is a differential, high-speed, Fault
Figure 6-1 illustrates the block diagram of the CAN
tolerant interface to the CAN physical bus. It is fully
transceiver.
compatible with the ISO-11898-2 and ISO-11898-5
standards. It operates at speeds of up to 1 Mb/s.
The CAN transceiver converts the digital TxCAN signal
generated by the CAN controller to signals suitable for
transmission over the physical CAN bus (differential out-
put). It also translates the differential CAN bus voltage to
the RxCAN input signal of the CAN controller.

FIGURE 6-1: CAN TRANSCEIVER BLOCK DIAGRAM

VIO VDDA

Digital I/O Thermal POR

Supply Protection UVLO

VIO

TXD
Permanent
Dominant Detect
CANH
Driver
VIO and
Slope Control CANL
STBY
Mode
Control

VSS

CANH
Wake-up LP_RX
Filter CANL

RXD
Receiver
CANH
HS_RX
CANL

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MCP25625
6.1 Transmitter Function 6.5 Power-on Reset (POR) and
The CAN bus has two states: Dominant and Recessive.
Undervoltage Detection
A Dominant state occurs when the differential voltage The MCP25625 has undervoltage detection on both
between CANH and CANL is greater than VDIFF(D)(I). A supply pins: VDDA and VIO. Typical undervoltage
Recessive state occurs when the differential voltage is thresholds are 1.2V for VIO and 4V for VDDA.
less than VDIFF(R)(I). The Dominant and Recessive
When the device is powered on, CANH and CANL
states correspond to the low and high state of the TXD
remain in a high-impedance state until both VDDA and
input pin, respectively. However, a Dominant state
VIO exceed their undervoltage levels. In addition,
initiated by another CAN node will override a Recessive
CANH and CANL will remain in a high-impedance state
state on the CAN bus.
if TXD is low when both undervoltage thresholds are
reached. CANH and CANL will become active only
6.2 Receiver Function after TXD is asserted high. Once powered on, CANH
In Normal mode, the RXD output pin reflects the differ- and CANL will enter a high-impedance state if the volt-
ential bus voltage between CANH and CANL. The low age level at VDDA drops below the undervoltage level,
and high states of the RXD output pin correspond to the providing voltage brown-out protection during normal
Dominant and Recessive states of the CAN bus, operation.
respectively. In Normal mode, the receiver output is forced to a
Recessive state during an undervoltage condition on
6.3 Internal Protection VDDA. In Standby mode, the low-power receiver is only
enabled when both VDDA and VIO supply voltages rise
CANH and CANL are protected against battery short above their respective undervoltage thresholds. Once
circuits and electrical transients that can occur on the these threshold voltages are reached, the low-power
CAN bus. This feature prevents destruction of the receiver is no longer controlled by the POR comparator
transmitter output stage during such a Fault condition. and remains operational down to about 2.5V on the
The device is further protected from excessive current VDDA supply. The CAN transceiver transfers data to the
loading by thermal shutdown circuitry that disables the RXD pin down to 1V on the VIO supply.
output drivers when the junction temperature exceeds
a nominal limit of +175°C. All other parts of the chip 6.6 Pin Description
remain operational and the chip temperature is lowered
due to the decreased power dissipation in the 6.6.1 TRANSMITTER DATA
transmitter outputs. This protection is essential to INPUT PIN (TXD)
protect against bus line short-circuit induced damage.
The CAN transceiver drives the differential output pins,
CANH and CANL, according to TXD. The transceiver is
6.4 Permanent Dominant Detection connected to the TxCAN pin of the CAN controller.
The CAN transceiver device prevents two conditions: When TXD is low, CANH and CANL are in the Dominant
state. When TXD is high, CANH and CANL are in the
• Permanent Dominant condition on TXD Recessive state, provided that another CAN node is
• Permanent Dominant condition on the bus not driving the CAN bus with a Dominant state. TXD is
In Normal mode, if the CAN transceiver detects an connected to an internal pull-up resistor (nominal
extended low state on the TXD input, it will disable the 33 k) to VIO.
CANH and CANL output drivers in order to prevent the
corruption of data on the CAN bus. The drivers will 6.6.2 GROUND SUPPLY PIN (VSS)
remain disabled until TXD goes high. Ground supply pin.
In Standby mode, if the CAN transceiver detects an
extended Dominant condition on the bus, it will set the 6.6.3 SUPPLY VOLTAGE PIN (VDDA)
RXD pin to the Recessive state. This allows the Positive supply voltage pin. Supplies transmitter and
attached controller to go to Low-Power mode until the receiver, including the wake-up receiver.
Dominant issue is corrected. RXD is latched high until a
Recessive state is detected on the bus and the
wake-up function is enabled again.
Both conditions have a time-out of 1.25 ms (typical).
This implies a maximum bit time of 69.44 µs
(14.4 kHz), allowing up to 18 consecutive Dominant
bits on the bus.

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 MCP25625
6.6.4 RECEIVER DATA 6.6.8 STANDBY MODE INPUT PIN (STBY)
OUTPUT PIN (RXD) This pin selects between Normal or Standby mode of
RXD is a CMOS compatible output that drives high or the CAN transceiver. In Standby mode, the transmitter
low depending on the differential signals on the CANH and the high-speed receiver are turned off, only the
and CANL pins, and is usually connected to the low-power receiver and wake-up filter are active. STBY
receiver data input of the CAN controller device. RXD is is connected to an internal MOS pull-up resistor to VIO.
high when the CAN bus is Recessive and low in the The value of the MOS pull-up resistor depends on the
Dominant state. RXD is supplied by VIO. supply voltage. Typical values are 660 k for 5V,
1.1 M for 3.3V and 4.4 M for 1.8V
6.6.5 VIO PIN
6.6.9 EXPOSED THERMAL PAD (EP)
Supply for digital I/O pins of the CAN transceiver.
It is recommended to connect this pad to VSS to
6.6.6 CAN LOW PIN (CANL) enhance electromagnetic immunity and thermal
The CANL output drives the low side of the CAN resistance.
differential bus. This pin is also tied internally to the
receive input comparator. CANL disconnects from the
bus when VDDA is not powered.

6.6.7 CAN HIGH PIN (CANH)

The CANH output drives the high side of the CAN
differential bus. This pin is also tied internally to the
receive input comparator. CANH disconnects from the
bus when VDDA is not powered.

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MCP25625
NOTES:

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 MCP25625
7.0 ELECTRICAL CHARACTERISTICS

7.1 Absolute Maximum Ratings†

VDD.............................................................................................................................................................................7.0V
VDDA...........................................................................................................................................................................7.0V
VIO ..............................................................................................................................................................................7.0V
DC Voltage at CANH, CANL ........................................................................................................................ -58V to +58V
DC Voltage at TXD, RXD, STBY w.r.t VSS ............................................................................................-0.3V to VIO + 0.3V
DC Voltage at All Other I/Os w.r.t GND ..............................................................................................-0.3V to VDD + 0.3V
Transient Voltage on CANH, CANL (ISO-7637) (Figure 7-5) ................................................................... -150V to +100V
Storage temperature ............................................................................................................................... -55°C to +150°C
Operating Ambient Temperature ............................................................................................................. -40°C to +125°C
Virtual Junction Temperature, TVJ (IEC60747-1) .................................................................................... -40°C to +150°C
Soldering Temperature of Leads (10 seconds) ..................................................................................................... +300°C
ESD Protection on CANH and CANL Pins (IEC 61000-4-2) .................................................................................... ±8 kV
ESD Protection on CANH and CANL Pins (IEC 801; Human Body Model)............................................................. ±8 kV
ESD Protection on All Other Pins (IEC 801; Human Body Model)........................................................................... ±4 kV
ESD Protection on All Pins (IEC 801; Machine Model)...........................................................................................±300V
ESD Protection on All Pins (IEC 801; Charge Device Model).................................................................................±750V

† NOTICE: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at those or any other conditions above those indicated
in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.

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MCP25625
7.2 CAN Controller Characteristics

TABLE 7-1: DC CHARACTERISTICS

Electrical Characteristics: Extended (E): TAMB = -40°C to +125°C; VDD = 2.7V to 5.5V

Sym. Characteristic Min. Max. Units Conditions

VDD Supply Voltage 2.7 5.5 V
VRET Register Retention Voltage 2.4 — V
High-Level Input Voltage
VIH RxCAN 2 VDD + 1 V
SCK, CS, SI, TxnRTS Pins 0.7 VDD VDD + 1 V
OSC1 0.85 VDD VDD V
RESET 0.85 VDD VDD V
Low-Level Input Voltage
VIL RxCAN, TxnRTS Pins -0.3 0.15 VDD V
SCK, CS, SI -0.3 0.4 VDD V
OSC1 VSS 0.3 VDD V
RESET VSS 0.15 VDD V
Low-Level Output Voltage
VOL TxCAN — 0.6 V IOL = +6.0 mA, VDD = 4.5V
RxnBF Pins — 0.6 V IOL = +8.5 mA, VDD = 4.5V
SO, CLKOUT — 0.6 V IOL = +2.1 mA, VDD = 4.5V
INT — 0.6 V IOL = +1.6 mA, VDD = 4.5V
High-Level Output Voltage
VOH TxCAN, RxnBF Pins VDD – 0.7 — V IOH = -3.0 mA, VDD = 4.5V
SO, CLKOUT VDD – 0.5 — V IOH = -400 µA, VDD = 4.5V
INT VDD – 0.7 — V IOH = -1.0 mA, VDD = 4.5V
Input Leakage Current
ILI All I/Os except OSC1 and -1 +1 µA CS = RESET = VDD,
TxnRTS Pins VIN = VSS to VDD
OSC1 Pin -5 +5 µA
CINT Internal Capacitance — 7 pF TAMB = +25°C, fC = 1.0 MHz,
(all inputs and outputs) VDD = 0V (Note 1)
IDD Operating Current — 10 mA VDD = 5.5V, FOSC = 25 MHz,
FCLK = 1 MHz, SO = Open
IDDS Standby Current (Sleep mode) — 8 µA CS, TxnRTS = VDD, Inputs tied
to VDD or VSS, -40°C to +125°C
Note 1: Characterized, not 100% tested.

TABLE 7-2: OSCILLATOR TIMING CHARACTERISTICS

Oscillator Timing Characteristics(1) Extended (E): TAMB = -40°C to +125°C; VDD = 2.7V to 5.5V

Sym. Characteristic Min. Max. Units Conditions

FOSC Clock In Frequency 1 25 MHz
TOSC Clock In Period 40 1000 ns
tDUTY Duty Cycle (External Clock input) 0.45 0.55 — TOSH/(TOSH + TOSL)
Note 1: Characterized, not 100% tested.

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 MCP25625
TABLE 7-3: CAN INTERFACE AC CHARACTERISTICS
CAN Interface AC Characteristics Extended (E): TAMB = -40°C to +125°C; VDD = 2.7V to 5.5V

Sym. Characteristic Min. Max. Units Conditions

tWF Wake-up Noise Filter 100 — ns

TABLE 7-4: RESET AC CHARACTERISTICS

RESET AC Characteristics Extended (E): TAMB = -40°C to +125°C; VDD = 2.7V to 5.5V

Sym. Characteristic Min. Max. Units Conditions

tRL RESET Pin Low Time 2 — µs

TABLE 7-5: CLKOUT PIN AC CHARACTERISTICS

CLKOUT Pin AC/DC Characteristics Extended (E): TAMB = -40°C to +125°C; VDD = 2.7V to 5.5V

Param.
Sym. Characteristic Min. Max. Units Conditions
No.
tHCLKOUT CLKOUT Pin High Time 10 — ns TOSC = 40 ns (Note 1)
tLCLKOUT CLKOUT Pin Low Time 10 — ns TOSC = 40 ns (Note 1)
tRCLKOUT CLKOUT Pin Rise Time — 10 ns Measured from 0.3 VDD
to 0.7 VDD (Note 1)
tFCLKOUT CLKOUT Pin Fall Time — 10 ns Measured from 0.7 VDD
to 0.3 VDD (Note 1)
tDCLKOUT CLKOUT Propagation — 100 ns (Note 1)
Delay
15 tHSOF Start-of-Frame High Time — 2 TOSC ns (Note 1)
16 tDSOF Start-of-Frame Propagation — 2 TOSC + 0.5 TQ ns Measured from CAN bit
Delay sample point, device is a
receiver, BRP[5:0] = 0 in the
CNF1 register (Note 2)
Note 1: All CLKOUT mode functionality and output frequency are tested at device frequency limits; however,
the CLKOUT prescaler is set to divide-by-one. Characterized, not 100% tested.
2: Characterized, not 100% tested.

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MCP25625
TABLE 7-6: SPI INTERFACE AC CHARACTERISTICS
SPI Interface AC Characteristics Extended (E): TAMB = -40°C to +125°C; VDD = 2.7V to 5.5V

Param.
Sym. Characteristic Min. Max. Units Conditions
No.
FCLK Clock Frequency — 10 MHz
1 tCSS CS Setup Time 50 — ns
2 tCSH CS Hold Time 50 — ns
3 tCSD CS Disable Time 50 — ns
4 tSU Data Setup Time 10 — ns
5 tHD Data Hold Time 10 — ns
6 tR Clock Rise Time — 2 µs (Note 1)
7 tF Clock Fall Time — 2 µs (Note 1)
8 tHI Clock High Time 45 — ns
9 tLO Clock Low Time 45 — ns
10 tCLD Clock Delay Time 50 — ns
11 tCLE Clock Enable Time 50 — ns
12 tV Output Valid from Clock Low — 45 ns
13 tHO Output Hold Time 0 — ns
14 tDIS Output Disable Time — 100 ns
Note 1: Characterized, not 100% tested.

FIGURE 7-1: START-OF-FRAME PIN AC CHARACTERISTICS

16
RxCAN Sample Point

15

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 MCP25625
7.3 CAN Transceiver Characteristics
TABLE 7-7: DC CHARACTERISTICS
Electrical Characteristics: Extended (E): TAMB = -40°C to +125°C; VDDA = 4.5V to 5.5V, VIO = 2.7V to 5.5V,
RL = 60; unless otherwise specified.

Characteristic Sym. Min. Typ. Max. Units Conditions

SUPPLY
VDDA Pin
Voltage Range VDDA 4.5 — 5.5
Supply Current IDD — 5 10 mA Recessive; VTXD = VDDA
— 45 70 Dominant; VTXD = 0V
Standby Current IDDS — 5 15 µA Includes IIO
High Level of the POR Comparator VPORH 3.8 — 4.3 V
Low Level of the POR Comparator VPORL 3.4 — 4.0 V
Hysteresis of POR Comparator VPORD 0.3 — 0.8 V
VIO Pin
Digital Supply Voltage Range VIO 2.7 — 5.5 V
Supply Current on VIO IIO — 4 30 µA Recessive; VTXD = VIO
— 85 500 Dominant; VTXD = 0V
Standby Current IDDS — 0.3 1 µA (Note 1)
Undervoltage Detection on VIO VUVD(IO) — 1.2 — V (Note 1)
BUS LINE (CANH, CANL) TRANSMITTER
CANH, CANL: VO(R) 2.0 0.5 VDDA 3.0 V VTXD = VDDA; No load
Recessive Bus Output Voltage
CANH, CANL: VO(S) -0.1 0.0 +0.1 V STBY = VTXD = VDDA; No load
Bus Output Voltage in Standby
Recessive Output Current IO(R) -5 — +5 mA -24V < VCAN < +24V
CANH: Dominant Output Voltage VO(D) 2.75 3.50 4.50 V TXD = 0; RL = 50 to 65
CANL: Dominant Output Voltage 0.50 1.50 2.25 RL = 50 to 65
Symmetry of Dominant VO(D)(M) -400 0 +400 mV VTXD = VSS (Note 1)
Output Voltage
(VDD – VCANH – VCANL)
Dominant: Differential VO(DIFF) 1.5 2.0 3.0 V VTXD = VSS; RL = 50 to 65
Output Voltage Figure 7-2, Figure 7-4
Recessive: -120 0 12 mV VTXD = VDDA,
Differential Output Voltage Figure 7-2, Figure 7-4
-500 0 50 mV VTXD = VDDA; No load,
Figure 7-2, Figure 7-4
CANH: Short-Circuit Output Current IO(SC) -120 85 — mA VTXD = VSS; VCANH = 0V;
CANL: floating
-100 — — mA Same as above, but VDDA = 5V,
TAMB = +25°C (Note 1)
CANL: Short-Circuit Output Cur- — 75 +120 mA VTXD = VSS; VCANL = 18V;
rent CANH: floating
— — +100 mA Same as above, but VDD = 5V,
TAMB = +25°C (Note 1)
Note 1: Characterized; not 100% tested.
2: -12V to 12V is ensured by characterization, tested from -2V to 7V.

 2014-2019 Microchip Technology Inc. DS20005282C-page 71

MCP25625
TABLE 7-7: DC CHARACTERISTICS (CONTINUED)
Electrical Characteristics: Extended (E): TAMB = -40°C to +125°C; VDDA = 4.5V to 5.5V, VIO = 2.7V to 5.5V,
RL = 60; unless otherwise specified.

Characteristic Sym. Min. Typ. Max. Units Conditions

BUS LINE (CANH; CANL) RECEIVER
Recessive Differential Input Voltage VDIFF(R)(I) -1.0 — +0.5 V Normal mode;
-12V < V(CANH, CANL) < +12V;
see Figure 7-6 (Note 2)
-1.0 — +0.4 Standby mode;
-12V < V(CANH, CANL) < +12V;
see Figure 7-6 (Note 2)
Dominant Differential Input Voltage VDIFF(D)(I) 0.9 — VDDA V Normal mode;
-12V < V(CANH, CANL) < +12V;
see Figure 7-6 (Note 2)
1.0 — VDDA Standby mode;
-12V < V(CANH, CANL) < +12V;
see Figure 7-6 (Note 2)
Differential Receiver Threshold VTH(DIFF) 0.5 0.7 0.9 V Normal mode;
-12V < V(CANH, CANL) < +12V;
see Figure 7-6 (Note 2)
0.4 — 1.15 Standby mode;
-12V < V(CANH, CANL) < +12V;
see Figure 7-6 (Note 2)
Differential Input Hysteresis VHYS(DIFF) 50 — 200 mV Normal mode; see Figure 7-6
(Note 1)
Common-Mode Input Resistance RIN 10 — 30 k (Note 1)
Common-Mode Resistance RIN(M) -1 0 +1 % VCANH = VCANL (Note 1)
Matching
Differential Input Resistance RIN(DIFF) 10 — 100 k (Note 1)
Common-Mode Input Capacitance CIN(CM) — — 20 pF VTXD = VDDA (Note 1)
Differential Input Capacitance CIN(DIFF) — — 10 VTXD = VDDA (Note 1)
CANH, CANL: Input Leakage ILI -5 — +5 µA VDDA = VTXD = VSTBY = 0V,
VIO = 0V, VCANH = VCANL = 5V
DIGITAL INPUT PINS (TXD, STBY)
High-Level Input Voltage VIH 0.7 VIO — VIO + 0.3 V
Low-Level Input Voltage VIL -0.3 — 0.3 VIO V
High-Level Input Current IIH -1 — +1 µA
TXD: Low-Level Input Current IIL(TXD) -270 -150 -30 µA
STBY: Low-Level Input Current IIL(STBY) -30 — -1 µA
RECEIVE DATA (RXD) OUTPUT
High-Level Output Voltage VOH VIO – 0.4 — — V IOH = -1 mA; typical -2 mA
Low-Level Output Voltage VOL — — 0.4 V IOL = 4 mA; typical 8 mA
THERMAL SHUTDOWN
Shutdown Junction Temperature TJ(SD) 165 175 185 °C -12V < V(CANH, CANL) < +12V
(Note 1)
Shutdown Temperature Hysteresis TJ(HYST) 20 — 30 °C -12V < V(CANH, CANL) < +12V
(Note 1)
Note 1: Characterized; not 100% tested.
2: -12V to 12V is ensured by characterization, tested from -2V to 7V.

DS20005282C-page 72  2014-2019 Microchip Technology Inc.

 MCP25625
TABLE 7-8: AC CHARACTERISTICS
Electrical Characteristics: Extended (E): TAMB = -40°C to +125°C; VDDA = 4.5V to 5.5V, VIO = 2.7V to 5.5V,
RL = 60; unless otherwise specified.

Param.
Sym Characteristic Min Typ Max Units Conditions
No.
1 tBIT Bit Time 1 — 69.44 µs
2 fBIT Bit Frequency 14.4 — 1000 kHz
3 tTXD-BUSON Delay TXD Low to Bus Dominant — — 70 ns
4 tTXD-BUSOFF Delay TXD High to Bus Recessive — — 125 ns
5 tBUSON-RXD Delay Bus Dominant to RXD — — 70 ns
6 tBUSOFF-RXD Delay Bus Recessive to RXD — — 110 ns
7 tTXD-RXD Propagation Delay TXD to RXD — — 125 ns Negative edge on TXD
8 — — 235 Positive edge on TXD
9 tFLTR(WAKE) Delay Bus Dominant to RXD 0.5 1 4 µs Standby mode
(Standby mode)
10 tWAKE Delay Standby to Normal mode 5 25 40 µs Negative edge on STBY
11 tPDT Permanent Dominant Detect Time — 1.25 — ms TXD = 0V
12 tPDTR Permanent Dominant Timer Reset — 100 — ns The shortest Recessive
pulse on TXD or CAN
bus to reset permanent
Dominant timer

 2014-2019 Microchip Technology Inc. DS20005282C-page 73

MCP25625
FIGURE 7-2: PHYSICAL BIT REPRESENTATION AND SIMPLIFIED BIAS IMPLEMENTATION

Normal Mode Standby Mode

CANH

CANH, CANL

CANL
Recessive Dominant Recessive

Time

VDDA

CANH

VDDA/2 Normal RXD

Standby
Mode
CANL

FIGURE 7-3: TEST LOAD CONDITIONS

Load Condition 1 Load Condition 2

VDDA/2

Pin CL
RL
VSS

Pin CL

VSS

RL = 464 
CL = 50 pF for all digital pins

DS20005282C-page 74  2014-2019 Microchip Technology Inc.

 MCP25625
FIGURE 7-4: TEST CIRCUIT FOR ELECTRICAL CHARACTERISTICS

VDDA 0.1 µF

TXD CANH

CAN RL 100 pF
Transceiver
RXD

30 pF CANL
GND STBY

Note: VIO is connected to VDDA.

FIGURE 7-5: TEST CIRCUIT FOR AUTOMOTIVE TRANSIENTS

CANH 500 pF
TXD

CAN Transient
RL
Transceiver Generator
RXD
CANL 500 pF
GND STBY

Note: The waveforms of the applied transients shall be in accordance with ISO-7637, Part 1,
Test Pulses 1, 2, 3a and 3b.
VIO is connected to VDDA.

FIGURE 7-6: HYSTERESIS OF THE RECEIVER

RXD (Receive Data

VOH
Output Voltage)
VDIFF(R)(I) VDIFF(D)(I)

VOL

VDIFF(H)(I)

0.5 VDIFF (V) 0.9

 2014-2019 Microchip Technology Inc. DS20005282C-page 75

MCP25625
FIGURE 7-7: TIMING DIAGRAM FOR AC CHARACTERISTICS

VDDA
TXD (Transmit Data
Input Voltage)
0V

VDIFF (CANH,
CANL Differential
Voltage)

RXD (Receive Data

Output Voltage) 3
5
7 4 6
8

FIGURE 7-8: TIMING DIAGRAM FOR WAKE-UP FROM STANDBY

VDDA
VSTBY
Input Voltage
0V
VCANH/VCANL VDDA/2

0
VTXD = VDDA
10

FIGURE 7-9: PERMANENT DOMINANT TIMER RESET DETECT

Minimum Pulse Width Until CAN Bus Goes to Dominant After the Falling Edge

TXD

Driver is Off
VDIFF (VCANH – VCANL)

11 12

DS20005282C-page 76  2014-2019 Microchip Technology Inc.

 MCP25625
7.4 Thermal Specifications

TABLE 7-9: THERMAL SPECIFICATIONS

Parameter Symbol Min. Typ. Max. Units Test Conditions
Temperature Ranges
Specified Temperature Range TA -40 — +125 C
Operating Temperature Range TA -40 — +125 C
Storage Temperature Range TA -65 — +150 C
Thermal Package Resistances
Thermal Resistance, 28L-QFN 6x6 mm JA — 32.8 — C/W
Thermal Resistance, 28L-SSOP JA — 80 — C/W

7.5 Terms and Definitions 7.5.5 DIFFERENTIAL VOLTAGE, VDIFF

(OF CAN BUS)
A number of terms are defined in ISO-11898 that are
used to describe the electrical characteristics of a CAN Differential voltage of the two-wire CAN bus, value:
transceiver device. These terms and definitions are VDIFF = VCANH – VCANL.
summarized in this section.
7.5.6 INTERNAL CAPACITANCE, CIN
7.5.1 BUS VOLTAGE (OF A CAN NODE)
VCANL and VCANH denote the voltages of the bus line Capacitance seen between CANL (or CANH) and
wires, CANL and CANH, relative to the ground of each ground, during the Recessive state, when the CAN
individual CAN node. node is disconnected from the bus (see Figure 7-10).

7.5.2 COMMON-MODE BUS VOLTAGE 7.5.7 INTERNAL RESISTANCE, RIN

RANGE (OF A CAN NODE)
Boundary voltage levels of VCANL and VCANH, with Resistance seen between CANL (or CANH) and
respect to ground for which proper operation will occur, ground, during the Recessive state, when the CAN
if up to the maximum number of CAN nodes are node is disconnected from the bus (see Figure 7-10).
connected to the bus.
FIGURE 7-10: PHYSICAL LAYER
7.5.3 DIFFERENTIAL INTERNAL DEFINITIONS
CAPACITANCE, CDIFF
(OF A CAN NODE)
ECU
Capacitance seen between CANL and CANH during
the Recessive state, when the CAN node is RIN
disconnected from the bus (see Figure 7-10). CANL
7.5.4 DIFFERENTIAL INTERNAL RDIFF CDIFF
RIN
RESISTANCE, RDIFF CANH
(OF A CAN NODE) CIN CIN
Resistance seen between CANL and CANH during the GROUND
Recessive state when the CAN node is disconnected
from the bus (see Figure 7-10).

 2014-2019 Microchip Technology Inc. DS20005282C-page 77

MCP25625
NOTES:

DS20005282C-page 78  2014-2019 Microchip Technology Inc.

 MCP25625
8.0 PACKAGING INFORMATION
8.1 Package Marking Information

28-Lead QFN (6x6 mm) Example

XXXXXXXX MCP25625
XXXXXXXX E/ML e3
YYWWNNN 1644256

28-Lead SSOP (5.30 mm) Example

XXXXXXXXXXXX MCP25625
XXXXXXXXXXXX E/SS e3
YYWWNNN 1644256

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC® designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator (e3)
can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

 2014-2019 Microchip Technology Inc. DS20005282C-page 79

MCP25625

DS20005282C-page 80  2014-2019 Microchip Technology Inc.

 MCP25625

 2014-2019 Microchip Technology Inc. DS20005282C-page 81

MCP25625

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ZLWKPP&RQWDFW/HQJWK
1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWSZZZPLFURFKLSFRPSDFNDJLQJ

DS20005282C-page 82  2014-2019 Microchip Technology Inc.

 MCP25625

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 2014-2019 Microchip Technology Inc. DS20005282C-page 83

MCP25625

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS20005282C-page 84  2014-2019 Microchip Technology Inc.

 MCP25625
APPENDIX A: REVISION HISTORY
Revision C (January 2019)
The following is the list of modifications:
1. Updated Figure 1-2.
2. Updated Section 3.13.1, Oscillator Start-up
Timer.
3. Updated Table 4-2.
4. Updated Register 4-34.

Revision B (January 2017)

The following is the list of modifications:
1. The usage of the RXMx bits setting, ‘01’ and
‘10’, in the RXBxCTRL registers (Register 4-9
and Register 4-10) is not recommended.
2. Updated Figure 3-11.
3. Updated Table 3-3.

Revision A (March 2014)

• Original Release of this Document.

 2014-2019 Microchip Technology Inc. DS20005282C-page 85

MCP25625
NOTES:

DS20005282C-page 86  2014-2019 Microchip Technology Inc.

 MCP25625
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. [X] (1) -X /XX Examples:
a) MCP25625-E/ML: Extended Temperature,
Device Tape and Reel Temperature Package
28-Lead 6x6 QFN
Option Range
Package
b) MCP25625-E/SS: Extended Temperature,
28-Lead SSOP Package
c) MCP25625T-E/ML: Tape and Reel,
Device: MCP25625 CAN Controller with Integrated Transceiver
Extended Temperature,
28-Lead 6x6 QFN
Temperature E = -40°C to +125°C (Extended) Package
Range: d) MCP25625T-E/SS: Tape and Reel,
Extended Temperature,
28-Lead SSOP Package
Tape and Blank = Standard packaging (tube)
Reel Option: T = Tape and Reel Note 1: Tape and Reel identifier only appears in
the catalog part number description. This
identifier is used for ordering purposes
Package: ML = Plastic Quad Flat, No Lead Package – 6x6 mm and is not printed on the device package.
Body with 0.55 mm Terminal Length, 28-Lead Check with your Microchip Sales Office
SS = Plastic Shrink Small Outline – 5.30 mm Body for package availability with the Tape
28-Lead and Reel option.

 2014-2019 Microchip Technology Inc. DS20005282C-page 87

MCP25625
NOTES:

DS20005282C-page 88  2014-2019 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, AnyRate, AVR,
and may be superseded by updates. It is your responsibility to AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo,
ensure that your application meets with your specifications. CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo,
MICROCHIP MAKES NO REPRESENTATIONS OR JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus,
WARRANTIES OF ANY KIND WHETHER EXPRESS OR maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
IMPLIED, WRITTEN OR ORAL, STATUTORY OR OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
OTHERWISE, RELATED TO THE INFORMATION, Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
QUALITY, PERFORMANCE, MERCHANTABILITY OR trademarks of Microchip Technology Incorporated in the U.S.A.
FITNESS FOR PURPOSE. Microchip disclaims all liability and other countries.
arising from this information and its use. Use of Microchip ClockWorks, The Embedded Control Solutions Company,
devices in life support and/or safety applications is entirely at EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
the buyer’s risk, and the buyer agrees to defend, indemnify and mTouch, Precision Edge, and Quiet-Wire are registered
hold harmless Microchip from any and all damages, claims, trademarks of Microchip Technology Incorporated in the U.S.A.
suits, or expenses resulting from such use. No licenses are Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
conveyed, implicitly or otherwise, under any Microchip Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,
intellectual property rights unless otherwise stated. CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity,
JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation,
PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon,
QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O,
SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
Microchip received ISO/TS-16949:2009 certification for its worldwide SQTP is a service mark of Microchip Technology Incorporated in
headquarters, design and wafer fabrication facilities in Chandler and the U.S.A.
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures Silicon Storage Technology is a registered trademark of Microchip
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping Technology Inc. in other countries.
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
GestIC is a registered trademark of Microchip Technology
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified. Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
QUALITY MANAGEMENT SYSTEM respective companies.
© 2018, Microchip Technology Incorporated, All Rights Reserved.
CERTIFIED BY DNV ISBN: 978-1-5224-4057-4

== ISO/TS 16949 ==

 2014-2019 Microchip Technology Inc. DS20005282C-page 89

 Worldwide Sales and Service
AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
Corporate Office Australia - Sydney India - Bangalore Austria - Wels
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DS20005282C-page 90  2014-2019 Microchip Technology Inc.

08/15/18
Mouser Electronics

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